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8319429: Resetting MXCSR flags degrades ecore
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Reviewed-by: sviswanathan, thartmann
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vpaprotsk authored and Sandhya Viswanathan committed Nov 9, 2023
1 parent d7b0ba9 commit 636a351
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Showing 5 changed files with 19 additions and 9 deletions.
4 changes: 4 additions & 0 deletions src/hotspot/cpu/x86/globals_x86.hpp
Original file line number Diff line number Diff line change
Expand Up @@ -214,6 +214,10 @@ define_pd_global(intx, InitArrayShortSize, 8*BytesPerLong);
product(bool, UseLibmIntrinsic, true, DIAGNOSTIC, \
"Use Libm Intrinsics") \
\
/* Autodetected, see vm_version_x86.cpp */ \
product(bool, EnableX86ECoreOpts, false, DIAGNOSTIC, \
"Perform Ecore Optimization") \
\
/* Minimum array size in bytes to use AVX512 intrinsics */ \
/* for copy, inflate and fill which don't bail out early based on any */ \
/* condition. When this value is set to zero compare operations like */ \
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4 changes: 2 additions & 2 deletions src/hotspot/cpu/x86/stubGenerator_x86_32.cpp
Original file line number Diff line number Diff line change
Expand Up @@ -3965,8 +3965,8 @@ class StubGenerator: public StubCodeGenerator {
StubRoutines::x86::_fpu_cntrl_wrd_trunc = 0x0D7F;
// Round to nearest, 24-bit mode, exceptions masked
StubRoutines::x86::_fpu_cntrl_wrd_24 = 0x007F;
// Round to nearest, 64-bit mode, exceptions masked
StubRoutines::x86::_mxcsr_std = 0x1F80;
// Round to nearest, 64-bit mode, exceptions masked, flags specialized
StubRoutines::x86::_mxcsr_std = EnableX86ECoreOpts ? 0x1FBF : 0x1F80;
// Note: the following two constants are 80-bit values
// layout is critical for correct loading by FPU.
// Bias for strict fp multiply/divide
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8 changes: 4 additions & 4 deletions src/hotspot/cpu/x86/stubGenerator_x86_64.cpp
Original file line number Diff line number Diff line change
Expand Up @@ -3907,10 +3907,10 @@ address StubGenerator::generate_upcall_stub_exception_handler() {
}

void StubGenerator::create_control_words() {
// Round to nearest, 64-bit mode, exceptions masked
StubRoutines::x86::_mxcsr_std = 0x1F80;
// Round to zero, 64-bit mode, exceptions masked
StubRoutines::x86::_mxcsr_rz = 0x7F80;
// Round to nearest, 64-bit mode, exceptions masked, flags specialized
StubRoutines::x86::_mxcsr_std = EnableX86ECoreOpts ? 0x1FBF : 0x1F80;
// Round to zero, 64-bit mode, exceptions masked, flags specialized
StubRoutines::x86::_mxcsr_rz = EnableX86ECoreOpts ? 0x7FBF : 0x7F80;
}

// Initialization
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6 changes: 6 additions & 0 deletions src/hotspot/cpu/x86/vm_version_x86.cpp
Original file line number Diff line number Diff line change
Expand Up @@ -857,6 +857,12 @@ void VM_Version::get_processor_features() {
}
#endif

// Check if processor has Intel Ecore
if (FLAG_IS_DEFAULT(EnableX86ECoreOpts) && is_intel() && cpu_family() == 6 &&
(_model == 0x97 || _model == 0xAC || _model == 0xAF)) {
FLAG_SET_DEFAULT(EnableX86ECoreOpts, true);
}

if (UseSSE < 4) {
_features &= ~CPU_SSE4_1;
_features &= ~CPU_SSE4_2;
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6 changes: 3 additions & 3 deletions src/hotspot/cpu/x86/x86.ad
Original file line number Diff line number Diff line change
Expand Up @@ -7423,7 +7423,7 @@ instruct vround_float_avx(vec dst, vec src, rRegP tmp, vec xtmp1, vec xtmp2, vec
format %{ "vector_round_float $dst,$src\t! using $tmp, $xtmp1, $xtmp2, $xtmp3, $xtmp4 as TEMP" %}
ins_encode %{
int vlen_enc = vector_length_encoding(this);
InternalAddress new_mxcsr = $constantaddress((jint)0x3F80);
InternalAddress new_mxcsr = $constantaddress((jint)(EnableX86ECoreOpts ? 0x3FBF : 0x3F80));
__ vector_round_float_avx($dst$$XMMRegister, $src$$XMMRegister,
ExternalAddress(StubRoutines::x86::vector_float_sign_flip()), new_mxcsr, vlen_enc,
$tmp$$Register, $xtmp1$$XMMRegister, $xtmp2$$XMMRegister, $xtmp3$$XMMRegister, $xtmp4$$XMMRegister);
Expand All @@ -7440,7 +7440,7 @@ instruct vround_float_evex(vec dst, vec src, rRegP tmp, vec xtmp1, vec xtmp2, kR
format %{ "vector_round_float $dst,$src\t! using $tmp, $xtmp1, $xtmp2, $ktmp1, $ktmp2 as TEMP" %}
ins_encode %{
int vlen_enc = vector_length_encoding(this);
InternalAddress new_mxcsr = $constantaddress((jint)0x3F80);
InternalAddress new_mxcsr = $constantaddress((jint)(EnableX86ECoreOpts ? 0x3FBF : 0x3F80));
__ vector_round_float_evex($dst$$XMMRegister, $src$$XMMRegister,
ExternalAddress(StubRoutines::x86::vector_float_sign_flip()), new_mxcsr, vlen_enc,
$tmp$$Register, $xtmp1$$XMMRegister, $xtmp2$$XMMRegister, $ktmp1$$KRegister, $ktmp2$$KRegister);
Expand All @@ -7455,7 +7455,7 @@ instruct vround_reg_evex(vec dst, vec src, rRegP tmp, vec xtmp1, vec xtmp2, kReg
format %{ "vector_round_long $dst,$src\t! using $tmp, $xtmp1, $xtmp2, $ktmp1, $ktmp2 as TEMP" %}
ins_encode %{
int vlen_enc = vector_length_encoding(this);
InternalAddress new_mxcsr = $constantaddress((jint)0x3F80);
InternalAddress new_mxcsr = $constantaddress((jint)(EnableX86ECoreOpts ? 0x3FBF : 0x3F80));
__ vector_round_double_evex($dst$$XMMRegister, $src$$XMMRegister,
ExternalAddress(StubRoutines::x86::vector_double_sign_flip()), new_mxcsr, vlen_enc,
$tmp$$Register, $xtmp1$$XMMRegister, $xtmp2$$XMMRegister, $ktmp1$$KRegister, $ktmp2$$KRegister);
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