8332533: RISC-V: Enable vector variable shift instructions for machin…

…es with RVV Reviewed-by: fyang, mli
openjdk · May 22, 2024 · 67f03f2 · 67f03f2 · openjdk-notifier · May 22, 2024
1 parent 5f804b2
commit 67f03f2
Showing 1 changed file with 2 additions and 2 deletions.
diff --git a/src/hotspot/cpu/riscv/matcher_riscv.hpp b/src/hotspot/cpu/riscv/matcher_riscv.hpp
@@ -128,8 +128,8 @@
   static const bool int_in_long = true;
 
   // Does the CPU supports vector variable shift instructions?
-  static constexpr bool supports_vector_variable_shifts(void) {
-    return false;
+  static bool supports_vector_variable_shifts(void) {
+    return UseRVV;
   }
 
   // Does target support predicated operation emulation.