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8186670: Implement _onSpinWait() intrinsic for AArch64
Reviewed-by: phh, aph
  • Loading branch information
eastig authored and Paul Hohensee committed Nov 11, 2021
1 parent 3445e50 commit 6954b98f8faf29b6c2d13687a7a94e83302bdd85
Showing 13 changed files with 766 additions and 2 deletions.
@@ -2373,6 +2373,8 @@ const bool Matcher::match_rule_supported(int opcode) {

bool ret_value = true;
switch (opcode) {
case Op_OnSpinWait:
return VM_Version::supports_on_spin_wait();
case Op_CacheWB:
case Op_CacheWBPreSync:
case Op_CacheWBPostSync:
@@ -14333,6 +14335,18 @@ instruct signumF_reg(vRegF dst, vRegF src, vRegF zero, vRegF one) %{
ins_pipe(fp_uop_d);
%}

instruct onspinwait() %{
match(OnSpinWait);
ins_cost(INSN_COST);

format %{ "onspinwait" %}

ins_encode %{
__ spin_wait();
%}
ins_pipe(pipe_class_empty);
%}

// ============================================================================
// Logical Instructions

@@ -2984,7 +2984,7 @@ void LIR_Assembler::membar_loadstore() { __ membar(MacroAssembler::LoadStore); }
void LIR_Assembler::membar_storeload() { __ membar(MacroAssembler::StoreLoad); }

void LIR_Assembler::on_spin_wait() {
Unimplemented();
__ spin_wait();
}

void LIR_Assembler::get_thread(LIR_Opr result_reg) {
@@ -110,7 +110,15 @@ define_pd_global(intx, InlineSmallCode, 1000);
product(int, SoftwarePrefetchHintDistance, -1, \
"Use prfm hint with specified distance in compiled code." \
"Value -1 means off.") \
range(-1, 4096)
range(-1, 4096) \
product(ccstr, OnSpinWaitInst, "none", DIAGNOSTIC, \
"The instruction to use to implement " \
"java.lang.Thread.onSpinWait()." \
"Options: none, nop, isb, yield.") \
product(uint, OnSpinWaitInstCount, 1, DIAGNOSTIC, \
"The number of OnSpinWaitInst instructions to generate." \
"It cannot be used with OnSpinWaitInst=none.") \
range(1, 99)

// end of ARCH_FLAGS

@@ -5154,3 +5154,21 @@ void MacroAssembler::verify_cross_modify_fence_not_required() {
}
}
#endif

void MacroAssembler::spin_wait() {
for (int i = 0; i < VM_Version::spin_wait_desc().inst_count(); ++i) {
switch (VM_Version::spin_wait_desc().inst()) {
case SpinWait::NOP:
nop();
break;
case SpinWait::ISB:
isb();
break;
case SpinWait::YIELD:
yield();
break;
default:
ShouldNotReachHere();
}
}
}
@@ -1402,6 +1402,9 @@ class MacroAssembler: public Assembler {
void cache_wb(Address line);
void cache_wbsync(bool is_pre);

// Code for java.lang.Thread::onSpinWait() intrinsic.
void spin_wait();

private:
// Check the current thread doesn't need a cross modify fence.
void verify_cross_modify_fence_not_required() PRODUCT_RETURN;
@@ -0,0 +1,48 @@
/*
* Copyright (c) 2021, Amazon.com Inc. or its affiliates. All rights reserved.
* DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
*
* This code is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License version 2 only, as
* published by the Free Software Foundation.
*
* This code is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
* version 2 for more details (a copy is included in the LICENSE file that
* accompanied this code).
*
* You should have received a copy of the GNU General Public License version
* 2 along with this work; if not, write to the Free Software Foundation,
* Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
*
* Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
* or visit www.oracle.com if you need additional information or have any
* questions.
*
*/

#ifndef CPU_AARCH64_SPIN_WAIT_AARCH64_HPP
#define CPU_AARCH64_SPIN_WAIT_AARCH64_HPP

class SpinWait {
public:
enum Inst {
NONE = -1,
NOP,
ISB,
YIELD
};

private:
Inst _inst;
int _count;

public:
SpinWait(Inst inst = NONE, int count = 0) : _inst(inst), _count(count) {}

Inst inst() const { return _inst; }
int inst_count() const { return _count; }
};

#endif // CPU_AARCH64_SPIN_WAIT_AARCH64_HPP
@@ -46,6 +46,26 @@ int VM_Version::_dcache_line_size;
int VM_Version::_icache_line_size;
int VM_Version::_initial_sve_vector_length;

SpinWait VM_Version::_spin_wait;

static SpinWait get_spin_wait_desc() {
if (strcmp(OnSpinWaitInst, "nop") == 0) {
return SpinWait(SpinWait::NOP, OnSpinWaitInstCount);
} else if (strcmp(OnSpinWaitInst, "isb") == 0) {
return SpinWait(SpinWait::ISB, OnSpinWaitInstCount);
} else if (strcmp(OnSpinWaitInst, "yield") == 0) {
return SpinWait(SpinWait::YIELD, OnSpinWaitInstCount);
} else if (strcmp(OnSpinWaitInst, "none") != 0) {
vm_exit_during_initialization("The options for OnSpinWaitInst are nop, isb, yield, and none", OnSpinWaitInst);
}

if (!FLAG_IS_DEFAULT(OnSpinWaitInstCount) && OnSpinWaitInstCount > 0) {
vm_exit_during_initialization("OnSpinWaitInstCount cannot be used for OnSpinWaitInst 'none'");
}

return SpinWait{};
}

void VM_Version::initialize() {
_supports_cx8 = true;
_supports_atomic_getset4 = true;
@@ -451,5 +471,7 @@ void VM_Version::initialize() {
}
#endif

_spin_wait = get_spin_wait_desc();

UNSUPPORTED_OPTION(CriticalJNINatives);
}
@@ -26,6 +26,7 @@
#ifndef CPU_AARCH64_VM_VERSION_AARCH64_HPP
#define CPU_AARCH64_VM_VERSION_AARCH64_HPP

#include "spin_wait_aarch64.hpp"
#include "runtime/abstract_vm_version.hpp"
#include "utilities/sizes.hpp"

@@ -45,6 +46,8 @@ class VM_Version : public Abstract_VM_Version {
static int _icache_line_size;
static int _initial_sve_vector_length;

static SpinWait _spin_wait;

// Read additional info using OS-specific interfaces
static void get_os_cpu_info();

@@ -142,6 +145,10 @@ class VM_Version : public Abstract_VM_Version {

static void get_compatible_board(char *buf, int buflen);

static const SpinWait& spin_wait_desc() { return _spin_wait; }

static bool supports_on_spin_wait() { return _spin_wait.inst() != SpinWait::NONE; }

#ifdef __APPLE__
// Is the CPU running emulated (for example macOS Rosetta running x86_64 code on M1 ARM (aarch64)
static bool is_cpu_emulated();

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