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8319705: RISC-V: signumF/D intrinsics fails compiler/intrinsics/math/…
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…TestSignumIntrinsic.java

Reviewed-by: fyang, vkempik
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Hamlin Li committed Nov 9, 2023
1 parent f939542 commit 7b971c1
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Showing 4 changed files with 20 additions and 24 deletions.
19 changes: 7 additions & 12 deletions src/hotspot/cpu/riscv/c2_MacroAssembler_riscv.cpp
Original file line number Diff line number Diff line change
Expand Up @@ -1658,25 +1658,20 @@ void C2_MacroAssembler::round_double_mode(FloatRegister dst, FloatRegister src,
// otherwise return +/- 1.0 using sign of input.
// one - gives us a floating-point 1.0 (got from matching rule)
// bool is_double - specifies single or double precision operations will be used.
void C2_MacroAssembler::signum_fp(FloatRegister dst, FloatRegister src, FloatRegister one, bool is_double) {
Register tmp1 = t0;

void C2_MacroAssembler::signum_fp(FloatRegister dst, FloatRegister one, bool is_double) {
Label done;

is_double ? fclass_d(tmp1, src)
: fclass_s(tmp1, src);

is_double ? fmv_d(dst, src)
: fmv_s(dst, src);
is_double ? fclass_d(t0, dst)
: fclass_s(t0, dst);

// check if input is -0, +0, signaling NaN or quiet NaN
andi(tmp1, tmp1, fclass_mask::zero | fclass_mask::nan);
andi(t0, t0, fclass_mask::zero | fclass_mask::nan);

bnez(tmp1, done);
bnez(t0, done);

// use floating-point 1.0 with a sign of input
is_double ? fsgnj_d(dst, one, src)
: fsgnj_s(dst, one, src);
is_double ? fsgnj_d(dst, one, dst)
: fsgnj_s(dst, one, dst);

bind(done);
}
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3 changes: 1 addition & 2 deletions src/hotspot/cpu/riscv/c2_MacroAssembler_riscv.hpp
Original file line number Diff line number Diff line change
Expand Up @@ -157,8 +157,7 @@
void round_double_mode(FloatRegister dst, FloatRegister src, int round_mode,
Register tmp1, Register tmp2, Register tmp3);

void signum_fp(FloatRegister dst, FloatRegister src, FloatRegister one,
bool is_double);
void signum_fp(FloatRegister dst, FloatRegister one, bool is_double);

// intrinsic methods implemented by rvv instructions
void string_equals_v(Register r1, Register r2,
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18 changes: 8 additions & 10 deletions src/hotspot/cpu/riscv/riscv.ad
Original file line number Diff line number Diff line change
Expand Up @@ -7601,22 +7601,20 @@ instruct copySignF_reg(fRegF dst, fRegF src1, fRegF src2) %{
ins_pipe(fp_dop_reg_reg_s);
%}

instruct signumD_reg(fRegD dst, fRegD src, immD zero, fRegD one) %{
match(Set dst (SignumD src (Binary zero one)));
format %{ "signumD $dst, $src" %}
instruct signumD_reg(fRegD dst, immD zero, fRegD one) %{
match(Set dst (SignumD dst (Binary zero one)));
format %{ "signumD $dst, $dst" %}
ins_encode %{
__ signum_fp(as_FloatRegister($dst$$reg), as_FloatRegister($src$$reg),
as_FloatRegister($one$$reg), true /* is_double */);
__ signum_fp(as_FloatRegister($dst$$reg), as_FloatRegister($one$$reg), true /* is_double */);
%}
ins_pipe(pipe_class_default);
%}

instruct signumF_reg(fRegF dst, fRegF src, immF zero, fRegF one) %{
match(Set dst (SignumF src (Binary zero one)));
format %{ "signumF $dst, $src" %}
instruct signumF_reg(fRegF dst, immF zero, fRegF one) %{
match(Set dst (SignumF dst (Binary zero one)));
format %{ "signumF $dst, $dst" %}
ins_encode %{
__ signum_fp(as_FloatRegister($dst$$reg), as_FloatRegister($src$$reg),
as_FloatRegister($one$$reg), false /* is_double */);
__ signum_fp(as_FloatRegister($dst$$reg), as_FloatRegister($one$$reg), false /* is_double */);
%}
ins_pipe(pipe_class_default);
%}
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Original file line number Diff line number Diff line change
Expand Up @@ -35,6 +35,10 @@
* -XX:+IgnoreUnrecognizedVMOptions -XX:+UnlockDiagnosticVMOptions
* -XX:-UseSignumIntrinsic -XX:+UseCopySignIntrinsic
* compiler.intrinsics.math.TestSignumIntrinsic
* @run main/othervm
* -XX:+IgnoreUnrecognizedVMOptions -XX:+UnlockDiagnosticVMOptions
* -Xcomp -XX:+UseSignumIntrinsic
* compiler.intrinsics.math.TestSignumIntrinsic
*/

package compiler.intrinsics.math;
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