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8276976: Rename LIR_OprDesc to LIR_Opr
Co-authored-by: Chuck Rasbold <rasbold@openjdk.org>
Reviewed-by: thartmann, iveresov
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Man Cao and Chuck Rasbold committed Nov 18, 2021
1 parent 89b125f commit 839033baf61ca7f10437e8e53b2114b081d97ea9
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Showing 14 changed files with 229 additions and 238 deletions.
@@ -1564,7 +1564,7 @@ void LIR_Assembler::emit_compare_and_swap(LIR_OpCompareAndSwap* op) {
assert(op->addr()->is_address(), "what else?");
LIR_Address* addr_ptr = op->addr()->as_address_ptr();
assert(addr_ptr->disp() == 0, "need 0 disp");
assert(addr_ptr->index() == LIR_OprDesc::illegalOpr(), "need 0 index");
assert(addr_ptr->index() == LIR_Opr::illegalOpr(), "need 0 index");
addr = as_reg(addr_ptr->base());
}
Register newval = as_reg(op->new_value());
@@ -26,22 +26,22 @@
#include "asm/register.hpp"
#include "c1/c1_LIR.hpp"

FloatRegister LIR_OprDesc::as_float_reg() const {
FloatRegister LIR_Opr::as_float_reg() const {
return as_FloatRegister(fpu_regnr());
}

FloatRegister LIR_OprDesc::as_double_reg() const {
FloatRegister LIR_Opr::as_double_reg() const {
return as_FloatRegister(fpu_regnrLo());
}

// Reg2 unused.
LIR_Opr LIR_OprFact::double_fpu(int reg1, int reg2) {
assert(as_FloatRegister(reg2) == fnoreg, "Not used on this platform");
return (LIR_Opr)(intptr_t)((reg1 << LIR_OprDesc::reg1_shift) |
(reg1 << LIR_OprDesc::reg2_shift) |
LIR_OprDesc::double_type |
LIR_OprDesc::fpu_register |
LIR_OprDesc::double_size);
return (LIR_Opr)(intptr_t)((reg1 << LIR_Opr::reg1_shift) |
(reg1 << LIR_Opr::reg2_shift) |
LIR_Opr::double_type |
LIR_Opr::fpu_register |
LIR_Opr::double_size);
}

#ifndef PRODUCT
@@ -1381,7 +1381,7 @@ void LIR_Assembler::emit_compare_and_swap(LIR_OpCompareAndSwap* op) {
op->addr()->as_pointer_register() :
op->addr()->as_address_ptr()->base()->as_pointer_register();
assert(op->addr()->is_register() || op->addr()->as_address_ptr()->disp() == 0, "unexpected disp");
assert(op->addr()->is_register() || op->addr()->as_address_ptr()->index() == LIR_OprDesc::illegalOpr(), "unexpected index");
assert(op->addr()->is_register() || op->addr()->as_address_ptr()->index() == LIR_Opr::illegalOpr(), "unexpected index");
if (op->code() == lir_cas_int || op->code() == lir_cas_obj) {
Register cmpval = op->cmp_value()->as_register();
Register newval = op->new_value()->as_register();
@@ -25,21 +25,21 @@
#include "precompiled.hpp"
#include "c1/c1_LIR.hpp"

FloatRegister LIR_OprDesc::as_float_reg() const {
FloatRegister LIR_Opr::as_float_reg() const {
return as_FloatRegister(fpu_regnr());
}

FloatRegister LIR_OprDesc::as_double_reg() const {
FloatRegister LIR_Opr::as_double_reg() const {
return as_FloatRegister(fpu_regnrLo());
}

LIR_Opr LIR_OprFact::double_fpu(int reg1, int reg2) {
assert(as_FloatRegister(reg2) != fnoreg, "Arm32 holds double in two regs.");
return (LIR_Opr)(intptr_t)((reg1 << LIR_OprDesc::reg1_shift) |
(reg2 << LIR_OprDesc::reg2_shift) |
LIR_OprDesc::double_type |
LIR_OprDesc::fpu_register |
LIR_OprDesc::double_size);
return (LIR_Opr)(intptr_t)((reg1 << LIR_Opr::reg1_shift) |
(reg2 << LIR_Opr::reg2_shift) |
LIR_Opr::double_type |
LIR_Opr::fpu_register |
LIR_Opr::double_size);
}

#ifndef PRODUCT
@@ -27,22 +27,22 @@
#include "asm/register.hpp"
#include "c1/c1_LIR.hpp"

FloatRegister LIR_OprDesc::as_float_reg() const {
FloatRegister LIR_Opr::as_float_reg() const {
return as_FloatRegister(fpu_regnr());
}

FloatRegister LIR_OprDesc::as_double_reg() const {
FloatRegister LIR_Opr::as_double_reg() const {
return as_FloatRegister(fpu_regnrLo());
}

// Reg2 unused.
LIR_Opr LIR_OprFact::double_fpu(int reg1, int reg2) {
assert(!as_FloatRegister(reg2)->is_valid(), "Not used on this platform");
return (LIR_Opr)(intptr_t)((reg1 << LIR_OprDesc::reg1_shift) |
(reg1 << LIR_OprDesc::reg2_shift) |
LIR_OprDesc::double_type |
LIR_OprDesc::fpu_register |
LIR_OprDesc::double_size);
return (LIR_Opr)(intptr_t)((reg1 << LIR_Opr::reg1_shift) |
(reg1 << LIR_Opr::reg2_shift) |
LIR_Opr::double_type |
LIR_Opr::fpu_register |
LIR_Opr::double_size);
}

#ifndef PRODUCT
@@ -29,22 +29,22 @@
#include "c1/c1_LIR.hpp"


FloatRegister LIR_OprDesc::as_float_reg() const {
FloatRegister LIR_Opr::as_float_reg() const {
return FrameMap::nr2floatreg(fpu_regnr());
}

FloatRegister LIR_OprDesc::as_double_reg() const {
FloatRegister LIR_Opr::as_double_reg() const {
return FrameMap::nr2floatreg(fpu_regnrHi());
}

// Reg2 unused.
LIR_Opr LIR_OprFact::double_fpu(int reg1, int reg2) {
assert(!as_FloatRegister(reg2)->is_valid(), "Not used on this platform");
return (LIR_Opr)(intptr_t)((reg1 << LIR_OprDesc::reg1_shift) |
(reg1 << LIR_OprDesc::reg2_shift) |
LIR_OprDesc::double_type |
LIR_OprDesc::fpu_register |
LIR_OprDesc::double_size);
return (LIR_Opr)(intptr_t)((reg1 << LIR_Opr::reg1_shift) |
(reg1 << LIR_Opr::reg2_shift) |
LIR_Opr::double_type |
LIR_Opr::fpu_register |
LIR_Opr::double_size);
}

#ifndef PRODUCT
@@ -28,33 +28,33 @@
#include "c1/c1_LIR.hpp"


FloatRegister LIR_OprDesc::as_float_reg() const {
FloatRegister LIR_Opr::as_float_reg() const {
ShouldNotReachHere();
return fnoreg;
}

FloatRegister LIR_OprDesc::as_double_reg() const {
FloatRegister LIR_Opr::as_double_reg() const {
ShouldNotReachHere();
return fnoreg;
}

XMMRegister LIR_OprDesc::as_xmm_float_reg() const {
XMMRegister LIR_Opr::as_xmm_float_reg() const {
return FrameMap::nr2xmmreg(xmm_regnr());
}

XMMRegister LIR_OprDesc::as_xmm_double_reg() const {
XMMRegister LIR_Opr::as_xmm_double_reg() const {
assert(xmm_regnrLo() == xmm_regnrHi(), "assumed in calculation");
return FrameMap::nr2xmmreg(xmm_regnrLo());
}

// Reg2 unused.
LIR_Opr LIR_OprFact::double_fpu(int reg1, int reg2) {
assert(as_FloatRegister(reg2) == fnoreg, "Not used on this platform");
return (LIR_Opr)(intptr_t)((reg1 << LIR_OprDesc::reg1_shift) |
(reg1 << LIR_OprDesc::reg2_shift) |
LIR_OprDesc::double_type |
LIR_OprDesc::fpu_register |
LIR_OprDesc::double_size);
return (LIR_Opr)(intptr_t)((reg1 << LIR_Opr::reg1_shift) |
(reg1 << LIR_Opr::reg2_shift) |
LIR_Opr::double_type |
LIR_Opr::fpu_register |
LIR_Opr::double_size);
}

#ifndef PRODUCT
@@ -33,15 +33,15 @@
#include "runtime/sharedRuntime.hpp"
#include "runtime/vm_version.hpp"

Register LIR_OprDesc::as_register() const {
Register LIR_Opr::as_register() const {
return FrameMap::cpu_rnr2reg(cpu_regnr());
}

Register LIR_OprDesc::as_register_lo() const {
Register LIR_Opr::as_register_lo() const {
return FrameMap::cpu_rnr2reg(cpu_regnrLo());
}

Register LIR_OprDesc::as_register_hi() const {
Register LIR_Opr::as_register_hi() const {
return FrameMap::cpu_rnr2reg(cpu_regnrHi());
}

@@ -93,7 +93,7 @@ LIR_Address::Scale LIR_Address::scale(BasicType type) {

//---------------------------------------------------

char LIR_OprDesc::type_char(BasicType t) {
char LIR_Opr::type_char(BasicType t) {
switch (t) {
case T_ARRAY:
t = T_OBJECT;
@@ -121,7 +121,7 @@ char LIR_OprDesc::type_char(BasicType t) {
}

#ifndef PRODUCT
void LIR_OprDesc::validate_type() const {
void LIR_Opr::validate_type() const {

#ifdef ASSERT
if (!is_pointer() && !is_illegal()) {
@@ -173,7 +173,7 @@ void LIR_OprDesc::validate_type() const {
#endif // PRODUCT


bool LIR_OprDesc::is_oop() const {
bool LIR_Opr::is_oop() const {
if (is_pointer()) {
return pointer()->is_oop_pointer();
} else {
@@ -1373,7 +1373,7 @@ void LIR_List::unlock_object(LIR_Opr hdr, LIR_Opr obj, LIR_Opr lock, LIR_Opr scr

void check_LIR() {
// cannot do the proper checking as PRODUCT and other modes return different results
// guarantee(sizeof(LIR_OprDesc) == wordSize, "may not have a v-table");
// guarantee(sizeof(LIR_Opr) == wordSize, "may not have a v-table");
}


@@ -1448,12 +1448,12 @@ void print_LIR(BlockList* blocks) {
}

#else
// LIR_OprDesc
void LIR_OprDesc::print() const {
// LIR_Opr
void LIR_Opr::print() const {
print(tty);
}

void LIR_OprDesc::print(outputStream* out) const {
void LIR_Opr::print(outputStream* out) const {
if (is_illegal()) {
return;
}

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