8346478: RISC-V: Refactor add/sub assembler routines

Reviewed-by: fjiang, rehn, gcao

Author: RealFYang

src/hotspot/cpu/riscv/assembler_riscv.hpp

@@ -2015,10 +2015,10 @@ enum Nf {
   }
 
   INSN(add_uw,    0b0111011, 0b000, 0b0000100);
-  INSN(rol,       0b0110011, 0b001, 0b0110000);
-  INSN(rolw,      0b0111011, 0b001, 0b0110000);
-  INSN(ror,       0b0110011, 0b101, 0b0110000);
-  INSN(rorw,      0b0111011, 0b101, 0b0110000);
+  INSN(rolr,      0b0110011, 0b001, 0b0110000);
+  INSN(rolrw,     0b0111011, 0b001, 0b0110000);
+  INSN(rorr,      0b0110011, 0b101, 0b0110000);
+  INSN(rorrw,     0b0111011, 0b101, 0b0110000);
   INSN(sh1add,    0b0110011, 0b010, 0b0010000);
   INSN(sh2add,    0b0110011, 0b100, 0b0010000);
   INSN(sh3add,    0b0110011, 0b110, 0b0010000);

src/hotspot/cpu/riscv/c1_LIRAssembler_arraycopy_riscv.cpp

@@ -211,7 +211,7 @@ void LIR_Assembler::arraycopy_type_check(Register src, Register src_pos, Registe
     Label cont, slow;
 
 #define PUSH(r1, r2)                                     \
-    __ addi(sp, sp, -2 * wordSize);                      \
+    __ subi(sp, sp, 2 * wordSize);                       \
     __ sd(r1, Address(sp, 1 * wordSize));                \
     __ sd(r2, Address(sp, 0));
 
@@ -337,10 +337,10 @@ void LIR_Assembler::arraycopy_prepare_params(Register src, Register src_pos, Reg
                                              Register dst, Register dst_pos, BasicType basic_type) {
   int scale = array_element_size(basic_type);
   __ shadd(c_rarg0, src_pos, src, t0, scale);
-  __ add(c_rarg0, c_rarg0, arrayOopDesc::base_offset_in_bytes(basic_type));
+  __ addi(c_rarg0, c_rarg0, arrayOopDesc::base_offset_in_bytes(basic_type));
   assert_different_registers(c_rarg0, dst, dst_pos, length);
   __ shadd(c_rarg1, dst_pos, dst, t0, scale);
-  __ add(c_rarg1, c_rarg1, arrayOopDesc::base_offset_in_bytes(basic_type));
+  __ addi(c_rarg1, c_rarg1, arrayOopDesc::base_offset_in_bytes(basic_type));
   assert_different_registers(c_rarg1, dst, length);
   __ mv(c_rarg2, length);
   assert_different_registers(c_rarg2, dst);

src/hotspot/cpu/riscv/c1_LIRAssembler_riscv.cpp

@@ -1084,7 +1084,7 @@ void LIR_Assembler::typecheck_helper_slowcheck(ciKlass *k, Register obj, Registe
       // check for self
       __ beq(klass_RInfo, k_RInfo, *success_target);
 
-      __ addi(sp, sp, -2 * wordSize); // 2: store k_RInfo and klass_RInfo
+      __ subi(sp, sp, 2 * wordSize); // 2: store k_RInfo and klass_RInfo
       __ sd(k_RInfo, Address(sp, 0));             // sub klass
       __ sd(klass_RInfo, Address(sp, wordSize));  // super klass
       __ far_call(RuntimeAddress(Runtime1::entry_for(C1StubId::slow_subtype_check_id)));
@@ -1099,7 +1099,7 @@ void LIR_Assembler::typecheck_helper_slowcheck(ciKlass *k, Register obj, Registe
     // perform the fast part of the checking logic
     __ check_klass_subtype_fast_path(klass_RInfo, k_RInfo, Rtmp1, success_target, failure_target, nullptr);
     // call out-of-line instance of __ check_klass_subtytpe_slow_path(...)
-    __ addi(sp, sp, -2 * wordSize); // 2: store k_RInfo and klass_RInfo
+    __ subi(sp, sp, 2 * wordSize); // 2: store k_RInfo and klass_RInfo
     __ sd(klass_RInfo, Address(sp, wordSize));  // sub klass
     __ sd(k_RInfo, Address(sp, 0));             // super klass
     __ far_call(RuntimeAddress(Runtime1::entry_for(C1StubId::slow_subtype_check_id)));
@@ -2139,7 +2139,7 @@ void LIR_Assembler::lir_store_slowcheck(Register k_RInfo, Register klass_RInfo,
   // perform the fast part of the checking logic
   __ check_klass_subtype_fast_path(klass_RInfo, k_RInfo, Rtmp1, success_target, failure_target, nullptr);
   // call out-of-line instance of __ check_klass_subtype_slow_path(...)
-  __ addi(sp, sp, -2 * wordSize); // 2: store k_RInfo and klass_RInfo
+  __ subi(sp, sp, 2 * wordSize); // 2: store k_RInfo and klass_RInfo
   __ sd(klass_RInfo, Address(sp, wordSize));  // sub klass
   __ sd(k_RInfo, Address(sp, 0));             // super klass
   __ far_call(RuntimeAddress(Runtime1::entry_for(C1StubId::slow_subtype_check_id)));

src/hotspot/cpu/riscv/c1_MacroAssembler_riscv.cpp

@@ -199,16 +199,16 @@ void C1_MacroAssembler::initialize_body(Register obj, Register len_in_bytes, int
   Label done;
 
   // len_in_bytes is positive and ptr sized
-  sub(len_in_bytes, len_in_bytes, hdr_size_in_bytes);
+  subi(len_in_bytes, len_in_bytes, hdr_size_in_bytes);
   beqz(len_in_bytes, done);
 
   // Preserve obj
   if (hdr_size_in_bytes) {
-    add(obj, obj, hdr_size_in_bytes);
+    addi(obj, obj, hdr_size_in_bytes);
   }
   zero_memory(obj, len_in_bytes, tmp);
   if (hdr_size_in_bytes) {
-    sub(obj, obj, hdr_size_in_bytes);
+    subi(obj, obj, hdr_size_in_bytes);
   }
 
   bind(done);
@@ -262,7 +262,7 @@ void C1_MacroAssembler::initialize_object(Register obj, Register klass, Register
       j(entry_point);
 
       bind(loop);
-      sub(index, index, 1);
+      subi(index, index, 1);
       for (int i = -unroll; i < 0; i++) {
         if (-i == remainder) {
           bind(entry_point);
@@ -272,7 +272,7 @@ void C1_MacroAssembler::initialize_object(Register obj, Register klass, Register
       if (remainder == 0) {
         bind(entry_point);
       }
-      add(t0, t0, unroll * wordSize);
+      addi(t0, t0, unroll * wordSize);
       bnez(index, loop);
     }
   }

src/hotspot/cpu/riscv/c1_Runtime1_riscv.cpp

@@ -147,7 +147,7 @@ int StubAssembler::call_RT(Register oop_result, Register metadata_result, addres
     const int arg1_sp_offset = 0;
     const int arg2_sp_offset = 1;
     const int arg3_sp_offset = 2;
-    addi(sp, sp, -(arg_num + 1) * wordSize);
+    subi(sp, sp, (arg_num + 1) * wordSize);
     sd(arg1, Address(sp, arg1_sp_offset * wordSize));
     sd(arg2, Address(sp, arg2_sp_offset * wordSize));
     sd(arg3, Address(sp, arg3_sp_offset * wordSize));
@@ -301,14 +301,14 @@ static OopMap* save_live_registers(StubAssembler* sasm,
 
   if (save_fpu_registers) {
     // float registers
-    __ addi(sp, sp, -(FrameMap::nof_fpu_regs * wordSize));
+    __ subi(sp, sp, FrameMap::nof_fpu_regs * wordSize);
     for (int i = 0; i < FrameMap::nof_fpu_regs; i++) {
       __ fsd(as_FloatRegister(i), Address(sp, i * wordSize));
     }
   } else {
     // we define reg_save_layout = 62 as the fixed frame size,
     // we should also sub 32 * wordSize to sp when save_fpu_registers == false
-    __ addi(sp, sp, -32 * wordSize);
+    __ subi(sp, sp, 32 * wordSize);
   }
 
   return generate_oop_map(sasm, save_fpu_registers);
@@ -543,7 +543,7 @@ void Runtime1::generate_unwind_exception(StubAssembler *sasm) {
   // Save our return address because
   // exception_handler_for_return_address will destroy it.  We also
   // save exception_oop
-  __ addi(sp, sp, -2 * wordSize);
+  __ subi(sp, sp, 2 * wordSize);
   __ sd(exception_oop, Address(sp, wordSize));
   __ sd(ra, Address(sp));