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8255129: [PPC64, s390] Check vector_size_supported and add VectorRein…
…terpret node

Reviewed-by: lucy
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TheRealMDoerr committed Oct 23, 2020
1 parent df79257 commit 9007bc20b00b13b8424e4f10beb3e398ab614095
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Showing 2 changed files with 102 additions and 129 deletions.
@@ -2062,97 +2062,78 @@ static int frame_slots_bias(int reg_enc, PhaseRegAlloc* ra_) {
}

const bool Matcher::match_rule_supported(int opcode) {
if (!has_match_rule(opcode))
return false;
if (!has_match_rule(opcode)) {
return false; // no match rule present
}

bool ret_value = true;
switch (opcode) {
case Op_SqrtD:
return VM_Version::has_fsqrt();
case Op_CountLeadingZerosI:
case Op_CountLeadingZerosL:
if (!UseCountLeadingZerosInstructionsPPC64)
return false;
break;
case Op_CountTrailingZerosI:
case Op_CountTrailingZerosL:
if (!UseCountLeadingZerosInstructionsPPC64 &&
!UseCountTrailingZerosInstructionsPPC64)
return false;
break;

case Op_PopCountI:
case Op_PopCountL:
return (UsePopCountInstruction && VM_Version::has_popcntw());

case Op_StrComp:
return SpecialStringCompareTo;
case Op_StrEquals:
return SpecialStringEquals;
case Op_StrIndexOf:
case Op_StrIndexOfChar:
return SpecialStringIndexOf;
case Op_AddVB:
case Op_AddVS:
case Op_AddVI:
case Op_AddVF:
case Op_AddVD:
case Op_SubVB:
case Op_SubVS:
case Op_SubVI:
case Op_SubVF:
case Op_SubVD:
case Op_MulVS:
case Op_MulVF:
case Op_MulVD:
case Op_DivVF:
case Op_DivVD:
case Op_AbsVF:
case Op_AbsVD:
case Op_NegVF:
case Op_NegVD:
case Op_SqrtVF:
case Op_SqrtVD:
case Op_AddVL:
case Op_SubVL:
case Op_MulVI:
case Op_RoundDoubleModeV:
return SuperwordUseVSX;
case Op_PopCountVI:
return (SuperwordUseVSX && UsePopCountInstruction);
case Op_FmaVF:
case Op_FmaVD:
return (SuperwordUseVSX && UseFMA);
case Op_Digit:
return vmIntrinsics::is_intrinsic_available(vmIntrinsics::_isDigit);
case Op_LowerCase:
return vmIntrinsics::is_intrinsic_available(vmIntrinsics::_isLowerCase);
case Op_UpperCase:
return vmIntrinsics::is_intrinsic_available(vmIntrinsics::_isUpperCase);
case Op_Whitespace:
return vmIntrinsics::is_intrinsic_available(vmIntrinsics::_isWhitespace);

case Op_CacheWB:
case Op_CacheWBPreSync:
case Op_CacheWBPostSync:
if (!VM_Version::supports_data_cache_line_flush()) {
ret_value = false;
}
break;
case Op_SqrtD:
return VM_Version::has_fsqrt();
case Op_CountLeadingZerosI:
case Op_CountLeadingZerosL:
return UseCountLeadingZerosInstructionsPPC64;
case Op_CountTrailingZerosI:
case Op_CountTrailingZerosL:
return (UseCountLeadingZerosInstructionsPPC64 || UseCountTrailingZerosInstructionsPPC64);
case Op_PopCountI:
case Op_PopCountL:
return (UsePopCountInstruction && VM_Version::has_popcntw());

case Op_AddVB:
case Op_AddVS:
case Op_AddVI:
case Op_AddVF:
case Op_AddVD:
case Op_SubVB:
case Op_SubVS:
case Op_SubVI:
case Op_SubVF:
case Op_SubVD:
case Op_MulVS:
case Op_MulVF:
case Op_MulVD:
case Op_DivVF:
case Op_DivVD:
case Op_AbsVF:
case Op_AbsVD:
case Op_NegVF:
case Op_NegVD:
case Op_SqrtVF:
case Op_SqrtVD:
case Op_AddVL:
case Op_SubVL:
case Op_MulVI:
case Op_RoundDoubleModeV:
return SuperwordUseVSX;
case Op_PopCountVI:
return (SuperwordUseVSX && UsePopCountInstruction);
case Op_FmaVF:
case Op_FmaVD:
return (SuperwordUseVSX && UseFMA);

case Op_Digit:
return vmIntrinsics::is_intrinsic_available(vmIntrinsics::_isDigit);
case Op_LowerCase:
return vmIntrinsics::is_intrinsic_available(vmIntrinsics::_isLowerCase);
case Op_UpperCase:
return vmIntrinsics::is_intrinsic_available(vmIntrinsics::_isUpperCase);
case Op_Whitespace:
return vmIntrinsics::is_intrinsic_available(vmIntrinsics::_isWhitespace);

case Op_CacheWB:
case Op_CacheWBPreSync:
case Op_CacheWBPostSync:
return VM_Version::supports_data_cache_line_flush();
}

return ret_value; // Per default match rules are supported.
return true; // Per default match rules are supported.
}

const bool Matcher::match_rule_supported_vector(int opcode, int vlen, BasicType bt) {

// TODO
// identify extra cases that we might want to provide match rules for
// e.g. Op_ vector nodes and other intrinsics while guarding with vlen
bool ret_value = match_rule_supported(opcode);
// Add rules here.

return ret_value; // Per default match rules are supported.
if (!match_rule_supported(opcode) || !vector_size_supported(bt, vlen)) {
return false;
}
return true; // Per default match rules are supported.
}

const bool Matcher::has_predicated_vectors(void) {
@@ -6569,6 +6550,23 @@ instruct storeV16(indirect mem, vecX src) %{
ins_pipe(pipe_class_default);
%}

// Reinterpret: only one vector size used: either L or X
instruct reinterpretL(iRegLdst dst) %{
match(Set dst (VectorReinterpret dst));
ins_cost(0);
format %{ "reinterpret $dst" %}
ins_encode( /*empty*/ );
ins_pipe(pipe_class_empty);
%}

instruct reinterpretX(vecX dst) %{
match(Set dst (VectorReinterpret dst));
ins_cost(0);
format %{ "reinterpret $dst" %}
ins_encode( /*empty*/ );
ins_pipe(pipe_class_empty);
%}

// Store Compressed Oop
instruct storeN(memory dst, iRegN_P2N src) %{
match(Set dst (StoreN dst src));
@@ -1511,60 +1511,28 @@ static Register reg_to_register_object(int register_encoding) {
}

const bool Matcher::match_rule_supported(int opcode) {
if (!has_match_rule(opcode)) return false;
if (!has_match_rule(opcode)) {
return false; // no match rule present
}

switch (opcode) {
case Op_CountLeadingZerosI:
case Op_CountLeadingZerosL:
case Op_CountTrailingZerosI:
case Op_CountTrailingZerosL:
// Implementation requires FLOGR instruction, which is available since z9.
return true;

case Op_ReverseBytesI:
case Op_ReverseBytesL:
return UseByteReverseInstruction;

// PopCount supported by H/W from z/Architecture G5 (z196) on.
case Op_PopCountI:
case Op_PopCountL:
return UsePopCountInstruction && VM_Version::has_PopCount();

case Op_StrComp:
return SpecialStringCompareTo;
case Op_StrEquals:
return SpecialStringEquals;
case Op_StrIndexOf:
case Op_StrIndexOfChar:
return SpecialStringIndexOf;

case Op_GetAndAddI:
case Op_GetAndAddL:
return true;
// return VM_Version::has_AtomicMemWithImmALUOps();
case Op_GetAndSetI:
case Op_GetAndSetL:
case Op_GetAndSetP:
case Op_GetAndSetN:
return true; // General CAS implementation, always available.

default:
return true; // Per default match rules are supported.
// BUT: make sure match rule is not disabled by a false predicate!
// PopCount supported by H/W from z/Architecture G5 (z196) on.
return (UsePopCountInstruction && VM_Version::has_PopCount());
}

return true; // Per default match rules are supported.
// BUT: make sure match rule is not disabled by a false predicate!
return true; // Per default match rules are supported.
}

const bool Matcher::match_rule_supported_vector(int opcode, int vlen, BasicType bt) {
// TODO
// Identify extra cases that we might want to provide match rules for
// e.g. Op_ vector nodes and other intrinsics while guarding with vlen.
bool ret_value = match_rule_supported(opcode);
// Add rules here.

return ret_value; // Per default match rules are supported.
if (!match_rule_supported(opcode) || !vector_size_supported(bt, vlen)) {
return false;
}
return true; // Per default match rules are supported.
}

const bool Matcher::has_predicated_vectors(void) {
@@ -10807,7 +10775,7 @@ instruct Repl2F_imm0(iRegL dst, immFp0 src) %{
ins_pipe(pipe_class_dummy);
%}

// Store
// Load/Store vector

// Store Aligned Packed Byte register to memory (8 Bytes).
instruct storeA8B(memory mem, iRegL src) %{
@@ -10821,8 +10789,6 @@ instruct storeA8B(memory mem, iRegL src) %{
ins_pipe(pipe_class_dummy);
%}

// Load

instruct loadV8(iRegL dst, memory mem) %{
match(Set dst (LoadVector mem));
predicate(n->as_LoadVector()->memory_size() == 8);
@@ -10834,6 +10800,15 @@ instruct loadV8(iRegL dst, memory mem) %{
ins_pipe(pipe_class_dummy);
%}

// Reinterpret: only one vector size used
instruct reinterpret(iRegL dst) %{
match(Set dst (VectorReinterpret dst));
ins_cost(0);
format %{ "reinterpret $dst" %}
ins_encode( /*empty*/ );
ins_pipe(pipe_class_dummy);
%}

//----------POPULATION COUNT RULES--------------------------------------------

// Byte reverse

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