@@ -3757,6 +3757,15 @@ void Assembler::vpermb(XMMRegister dst, XMMRegister nds, XMMRegister src, int ve
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emit_int16 ((unsigned char )0x8D , (0xC0 | encode));
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}
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+ void Assembler::vpermb (XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
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+ assert (VM_Version::supports_avx512_vbmi (), " " );
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+ InstructionAttr attributes (vector_len, /* rex_w */ false , /* legacy_mode */ false , /* no_mask_reg */ true , /* uses_vl */ true );
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+ attributes.set_is_evex_instruction ();
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+ vex_prefix (src, nds->encoding (), dst->encoding (), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
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+ emit_int8 ((unsigned char )0x8D );
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+ emit_operand (dst, src);
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+ }
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+
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void Assembler::vpermw (XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
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assert (vector_len == AVX_128bit ? VM_Version::supports_avx512vlbw () :
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vector_len == AVX_256bit ? VM_Version::supports_avx512vlbw () :
@@ -3837,6 +3846,14 @@ void Assembler::evpermt2b(XMMRegister dst, XMMRegister nds, XMMRegister src, int
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emit_int16 (0x7D , (0xC0 | encode));
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}
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+ void Assembler::evpmultishiftqb (XMMRegister dst, XMMRegister ctl, XMMRegister src, int vector_len) {
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+ assert (VM_Version::supports_avx512_vbmi (), " " );
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+ InstructionAttr attributes (vector_len, /* vex_w */ true , /* legacy_mode */ false , /* no_mask_reg */ true , /* uses_vl */ true );
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+ attributes.set_is_evex_instruction ();
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+ int encode = vex_prefix_and_encode (dst->encoding (), ctl->encoding (), src->encoding (), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
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+ emit_int16 ((unsigned char )0x83 , (unsigned char )(0xC0 | encode));
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+ }
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+
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void Assembler::pause () {
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emit_int16 ((unsigned char )0xF3 , (unsigned char )0x90 );
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}
@@ -4135,6 +4152,15 @@ void Assembler::vpmovmskb(Register dst, XMMRegister src, int vec_enc) {
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emit_int16 ((unsigned char )0xD7 , (0xC0 | encode));
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}
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+ void Assembler::vpmaskmovd (XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
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+ assert ((VM_Version::supports_avx2 () && vector_len == AVX_256bit), " " );
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+ InstructionMark im (this );
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+ InstructionAttr attributes (vector_len, /* vex_w */ false , /* legacy_mode */ true , /* no_mask_reg */ false , /* uses_vl */ true );
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+ vex_prefix (src, nds->encoding (), dst->encoding (), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
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+ emit_int8 ((unsigned char )0x8C );
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+ emit_operand (dst, src);
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+ }
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+
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void Assembler::pextrd (Register dst, XMMRegister src, int imm8) {
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assert (VM_Version::supports_sse4_1 (), " " );
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InstructionAttr attributes (AVX_128bit, /* rex_w */ false , /* legacy_mode */ _legacy_mode_dq, /* no_mask_reg */ true , /* uses_vl */ false );
@@ -6564,6 +6590,13 @@ void Assembler::psubq(XMMRegister dst, XMMRegister src) {
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emit_int8 ((0xC0 | encode));
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}
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+ void Assembler::vpsubusb (XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
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+ assert (UseAVX > 0 , " requires some form of AVX" );
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+ InstructionAttr attributes (vector_len, /* vex_w */ false , /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true , /* uses_vl */ true );
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+ int encode = vex_prefix_and_encode (dst->encoding (), nds->encoding (), src->encoding (), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
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+ emit_int16 ((unsigned char )0xD8 , (0xC0 | encode));
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+ }
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+
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void Assembler::vpsubb (XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
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assert (UseAVX > 0 , " requires some form of AVX" );
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InstructionAttr attributes (vector_len, /* vex_w */ false , /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true , /* uses_vl */ true );
@@ -6655,6 +6688,15 @@ void Assembler::pmuludq(XMMRegister dst, XMMRegister src) {
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emit_int16 ((unsigned char )0xF4 , (0xC0 | encode));
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}
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+ void Assembler::vpmulhuw (XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
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+ assert ((vector_len == AVX_128bit && VM_Version::supports_avx ()) ||
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+ (vector_len == AVX_256bit && VM_Version::supports_avx2 ()) ||
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+ (vector_len == AVX_512bit && VM_Version::supports_avx512bw ()), " " );
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+ InstructionAttr attributes (vector_len, /* vex_w */ false , /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true , /* uses_vl */ true );
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+ int encode = vex_prefix_and_encode (dst->encoding (), nds->encoding (), src->encoding (), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
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+ emit_int16 ((unsigned char )0xE4 , (0xC0 | encode));
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+ }
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+
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void Assembler::vpmullw (XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
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assert (UseAVX > 0 , " requires some form of AVX" );
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InstructionAttr attributes (vector_len, /* vex_w */ false , /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true , /* uses_vl */ true );
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