diff --git a/test/hotspot/jtreg/compiler/c2/TestMinMaxSubword.java b/test/hotspot/jtreg/compiler/c2/TestMinMaxSubword.java index 129fdc7096a61..955aa4058f046 100644 --- a/test/hotspot/jtreg/compiler/c2/TestMinMaxSubword.java +++ b/test/hotspot/jtreg/compiler/c2/TestMinMaxSubword.java @@ -61,7 +61,7 @@ public class TestMinMaxSubword { // as Java APIs for Math.min/max do not support integer subword types and superword // should not generate vectorized Min/Max nodes for them. @Test - @IR(failOn = {IRNode.MIN_V}) + @IR(failOn = {IRNode.MIN_VI, IRNode.MIN_VF, IRNode.MIN_VD}) public static void testMinShort() { for (int i = 0; i < LENGTH; i++) { sb[i] = (short) Math.min(sa[i], val); @@ -77,7 +77,7 @@ public static void testMinShort_runner() { } @Test - @IR(failOn = {IRNode.MAX_V}) + @IR(failOn = {IRNode.MAX_VI, IRNode.MAX_VF, IRNode.MAX_VD}) public static void testMaxShort() { for (int i = 0; i < LENGTH; i++) { sb[i] = (short) Math.max(sa[i], val); @@ -92,7 +92,7 @@ public static void testMaxShort_runner() { } @Test - @IR(failOn = {IRNode.MIN_V}) + @IR(failOn = {IRNode.MIN_VI, IRNode.MIN_VF, IRNode.MIN_VD}) public static void testMinByte() { for (int i = 0; i < LENGTH; i++) { bb[i] = (byte) Math.min(ba[i], val); @@ -108,7 +108,7 @@ public static void testMinByte_runner() { } @Test - @IR(failOn = {IRNode.MAX_V}) + @IR(failOn = {IRNode.MAX_VI, IRNode.MAX_VF, IRNode.MAX_VD}) public static void testMaxByte() { for (int i = 0; i < LENGTH; i++) { bb[i] = (byte) Math.max(ba[i], val); diff --git a/test/hotspot/jtreg/compiler/c2/irTests/TestAutoVecCountingDownLoop.java b/test/hotspot/jtreg/compiler/c2/irTests/TestAutoVecCountingDownLoop.java index 9769f8d43a767..994ec1e9cc0bf 100644 --- a/test/hotspot/jtreg/compiler/c2/irTests/TestAutoVecCountingDownLoop.java +++ b/test/hotspot/jtreg/compiler/c2/irTests/TestAutoVecCountingDownLoop.java @@ -46,7 +46,7 @@ public static void main(String[] args) { @Test - @IR(counts = {IRNode.LOAD_VECTOR, " >0 "}) + @IR(counts = {IRNode.LOAD_VECTOR_I, " >0 "}) @IR(counts = {IRNode.STORE_VECTOR, " >0 "}) private static void testCountingDown(int[] a, int[] b) { for (int i = 2000; i > 0; i--) { diff --git a/test/hotspot/jtreg/compiler/c2/irTests/TestAutoVectorization2DArray.java b/test/hotspot/jtreg/compiler/c2/irTests/TestAutoVectorization2DArray.java index 31fc5361b6bbc..c9b2904d91c74 100644 --- a/test/hotspot/jtreg/compiler/c2/irTests/TestAutoVectorization2DArray.java +++ b/test/hotspot/jtreg/compiler/c2/irTests/TestAutoVectorization2DArray.java @@ -48,9 +48,12 @@ public static void main(String[] args) { } @Test - @IR(counts = { IRNode.LOAD_VECTOR, " >0 " }) - @IR(counts = { IRNode.ADD_VD, " >0 " }) - @IR(counts = { IRNode.STORE_VECTOR, " >0 " }) + // Given small iteration count, the unrolling factor is not very predictable, + // hence it is difficult to exactly predict the vector size. But let's at least + // check that there is some vectorization of any size. + @IR(counts = { IRNode.LOAD_VECTOR_D, IRNode.VECTOR_SIZE_ANY, " >0 " }) + @IR(counts = { IRNode.ADD_VD, IRNode.VECTOR_SIZE_ANY, " >0 " }) + @IR(counts = { IRNode.STORE_VECTOR, " >0 " }) private static void testDouble(double[][] a , double[][] b, double[][] c) { for(int i = 0; i < a.length; i++) { for (int j = 0; j < a[0].length; j++) { diff --git a/test/hotspot/jtreg/compiler/c2/irTests/TestDisableAutoVectOpcodes.java b/test/hotspot/jtreg/compiler/c2/irTests/TestDisableAutoVectOpcodes.java index f493b3fc3074c..31112a74eb11f 100644 --- a/test/hotspot/jtreg/compiler/c2/irTests/TestDisableAutoVectOpcodes.java +++ b/test/hotspot/jtreg/compiler/c2/irTests/TestDisableAutoVectOpcodes.java @@ -53,7 +53,7 @@ public static void main(String[] args) { } @Test - @IR(failOn = {IRNode.VECTOR_CAST_D2X}) + @IR(failOn = {IRNode.VECTOR_CAST_D2I}) private static void testConvD2I() { for(int i = 0; i < SIZE; i++) { inta[i] = (int) (doublea[i]); @@ -61,7 +61,7 @@ private static void testConvD2I() { } @Test - @IR(failOn = {IRNode.VECTOR_CAST_L2X}) + @IR(failOn = {IRNode.VECTOR_CAST_L2F}) private static void testConvL2F() { for(int i = 0; i < SIZE; i++) { floata[i] = (float) (longa[i]); diff --git a/test/hotspot/jtreg/compiler/c2/irTests/TestVectorConditionalMove.java b/test/hotspot/jtreg/compiler/c2/irTests/TestVectorConditionalMove.java index 6cd87f19339dc..f50b091719e22 100644 --- a/test/hotspot/jtreg/compiler/c2/irTests/TestVectorConditionalMove.java +++ b/test/hotspot/jtreg/compiler/c2/irTests/TestVectorConditionalMove.java @@ -203,7 +203,10 @@ private double cmoveDGTforD(double a, double b, double c, double d) { // Compare 2 values, and pick one of them @Test - @IR(counts = {IRNode.LOAD_VECTOR, ">0", IRNode.VECTOR_MASK_CMP, ">0", IRNode.VECTOR_BLEND, ">0", IRNode.STORE_VECTOR, ">0"}, + @IR(counts = {IRNode.LOAD_VECTOR_F, ">0", + IRNode.VECTOR_MASK_CMP_F, ">0", + IRNode.VECTOR_BLEND_F, ">0", + IRNode.STORE_VECTOR, ">0"}, applyIfCPUFeatureOr = {"avx", "true", "asimd", "true"}) private static void testCMoveVFGT(float[] a, float[] b, float[] c) { for (int i = 0; i < a.length; i++) { @@ -212,7 +215,10 @@ private static void testCMoveVFGT(float[] a, float[] b, float[] c) { } @Test - @IR(counts = {IRNode.LOAD_VECTOR, ">0", IRNode.VECTOR_MASK_CMP, ">0", IRNode.VECTOR_BLEND, ">0", IRNode.STORE_VECTOR, ">0"}, + @IR(counts = {IRNode.LOAD_VECTOR_F, ">0", + IRNode.VECTOR_MASK_CMP_F, ">0", + IRNode.VECTOR_BLEND_F, ">0", + IRNode.STORE_VECTOR, ">0"}, applyIfCPUFeatureOr = {"avx", "true", "asimd", "true"}) private static void testCMoveVFGTSwap(float[] a, float[] b, float[] c) { for (int i = 0; i < a.length; i++) { @@ -221,7 +227,10 @@ private static void testCMoveVFGTSwap(float[] a, float[] b, float[] c) { } @Test - @IR(counts = {IRNode.LOAD_VECTOR, ">0", IRNode.VECTOR_MASK_CMP, ">0", IRNode.VECTOR_BLEND, ">0", IRNode.STORE_VECTOR, ">0"}, + @IR(counts = {IRNode.LOAD_VECTOR_F, ">0", + IRNode.VECTOR_MASK_CMP_F, ">0", + IRNode.VECTOR_BLEND_F, ">0", + IRNode.STORE_VECTOR, ">0"}, applyIfCPUFeatureOr = {"avx", "true", "asimd", "true"}) private static void testCMoveVFLT(float[] a, float[] b, float[] c) { for (int i = 0; i < a.length; i++) { @@ -230,7 +239,10 @@ private static void testCMoveVFLT(float[] a, float[] b, float[] c) { } @Test - @IR(counts = {IRNode.LOAD_VECTOR, ">0", IRNode.VECTOR_MASK_CMP, ">0", IRNode.VECTOR_BLEND, ">0", IRNode.STORE_VECTOR, ">0"}, + @IR(counts = {IRNode.LOAD_VECTOR_F, ">0", + IRNode.VECTOR_MASK_CMP_F, ">0", + IRNode.VECTOR_BLEND_F, ">0", + IRNode.STORE_VECTOR, ">0"}, applyIfCPUFeatureOr = {"avx", "true", "asimd", "true"}) private static void testCMoveVFLTSwap(float[] a, float[] b, float[] c) { for (int i = 0; i < a.length; i++) { @@ -239,7 +251,10 @@ private static void testCMoveVFLTSwap(float[] a, float[] b, float[] c) { } @Test - @IR(counts = {IRNode.LOAD_VECTOR, ">0", IRNode.VECTOR_MASK_CMP, ">0", IRNode.VECTOR_BLEND, ">0", IRNode.STORE_VECTOR, ">0"}, + @IR(counts = {IRNode.LOAD_VECTOR_F, ">0", + IRNode.VECTOR_MASK_CMP_F, ">0", + IRNode.VECTOR_BLEND_F, ">0", + IRNode.STORE_VECTOR, ">0"}, applyIfCPUFeatureOr = {"avx", "true", "asimd", "true"}) private static void testCMoveVFEQ(float[] a, float[] b, float[] c) { for (int i = 0; i < a.length; i++) { @@ -248,7 +263,10 @@ private static void testCMoveVFEQ(float[] a, float[] b, float[] c) { } @Test - @IR(counts = {IRNode.LOAD_VECTOR, ">0", IRNode.VECTOR_MASK_CMP, ">0", IRNode.VECTOR_BLEND, ">0", IRNode.STORE_VECTOR, ">0"}, + @IR(counts = {IRNode.LOAD_VECTOR_D, ">0", + IRNode.VECTOR_MASK_CMP_D, ">0", + IRNode.VECTOR_BLEND_D, ">0", + IRNode.STORE_VECTOR, ">0"}, applyIfCPUFeatureOr = {"avx", "true", "asimd", "true"}) private static void testCMoveVDLE(double[] a, double[] b, double[] c) { for (int i = 0; i < a.length; i++) { @@ -257,7 +275,10 @@ private static void testCMoveVDLE(double[] a, double[] b, double[] c) { } @Test - @IR(counts = {IRNode.LOAD_VECTOR, ">0", IRNode.VECTOR_MASK_CMP, ">0", IRNode.VECTOR_BLEND, ">0", IRNode.STORE_VECTOR, ">0"}, + @IR(counts = {IRNode.LOAD_VECTOR_D, ">0", + IRNode.VECTOR_MASK_CMP_D, ">0", + IRNode.VECTOR_BLEND_D, ">0", + IRNode.STORE_VECTOR, ">0"}, applyIfCPUFeatureOr = {"avx", "true", "asimd", "true"}) private static void testCMoveVDLESwap(double[] a, double[] b, double[] c) { for (int i = 0; i < a.length; i++) { @@ -266,7 +287,10 @@ private static void testCMoveVDLESwap(double[] a, double[] b, double[] c) { } @Test - @IR(counts = {IRNode.LOAD_VECTOR, ">0", IRNode.VECTOR_MASK_CMP, ">0", IRNode.VECTOR_BLEND, ">0", IRNode.STORE_VECTOR, ">0"}, + @IR(counts = {IRNode.LOAD_VECTOR_D, ">0", + IRNode.VECTOR_MASK_CMP_D, ">0", + IRNode.VECTOR_BLEND_D, ">0", + IRNode.STORE_VECTOR, ">0"}, applyIfCPUFeatureOr = {"avx", "true", "asimd", "true"}) private static void testCMoveVDGE(double[] a, double[] b, double[] c) { for (int i = 0; i < a.length; i++) { @@ -275,7 +299,10 @@ private static void testCMoveVDGE(double[] a, double[] b, double[] c) { } @Test - @IR(counts = {IRNode.LOAD_VECTOR, ">0", IRNode.VECTOR_MASK_CMP, ">0", IRNode.VECTOR_BLEND, ">0", IRNode.STORE_VECTOR, ">0"}, + @IR(counts = {IRNode.LOAD_VECTOR_D, ">0", + IRNode.VECTOR_MASK_CMP_D, ">0", + IRNode.VECTOR_BLEND_D, ">0", + IRNode.STORE_VECTOR, ">0"}, applyIfCPUFeatureOr = {"avx", "true", "asimd", "true"}) private static void testCMoveVDGESwap(double[] a, double[] b, double[] c) { for (int i = 0; i < a.length; i++) { @@ -284,7 +311,10 @@ private static void testCMoveVDGESwap(double[] a, double[] b, double[] c) { } @Test - @IR(counts = {IRNode.LOAD_VECTOR, ">0", IRNode.VECTOR_MASK_CMP, ">0", IRNode.VECTOR_BLEND, ">0", IRNode.STORE_VECTOR, ">0"}, + @IR(counts = {IRNode.LOAD_VECTOR_D, ">0", + IRNode.VECTOR_MASK_CMP_D, ">0", + IRNode.VECTOR_BLEND_D, ">0", + IRNode.STORE_VECTOR, ">0"}, applyIfCPUFeatureOr = {"avx", "true", "asimd", "true"}) private static void testCMoveVDNE(double[] a, double[] b, double[] c) { for (int i = 0; i < a.length; i++) { @@ -294,7 +324,10 @@ private static void testCMoveVDNE(double[] a, double[] b, double[] c) { // Extensions: compare 2 values, and pick from 2 consts @Test - @IR(counts = {IRNode.LOAD_VECTOR, ">0", IRNode.VECTOR_MASK_CMP, ">0", IRNode.VECTOR_BLEND, ">0", IRNode.STORE_VECTOR, ">0"}, + @IR(counts = {IRNode.LOAD_VECTOR_F, ">0", + IRNode.VECTOR_MASK_CMP_F, ">0", + IRNode.VECTOR_BLEND_F, ">0", + IRNode.STORE_VECTOR, ">0"}, applyIfCPUFeatureOr = {"avx", "true", "asimd", "true"}) private static void testCMoveFGTforFConst(float[] a, float[] b, float[] c) { for (int i = 0; i < a.length; i++) { @@ -303,7 +336,10 @@ private static void testCMoveFGTforFConst(float[] a, float[] b, float[] c) { } @Test - @IR(counts = {IRNode.LOAD_VECTOR, ">0", IRNode.VECTOR_MASK_CMP, ">0", IRNode.VECTOR_BLEND, ">0", IRNode.STORE_VECTOR, ">0"}, + @IR(counts = {IRNode.LOAD_VECTOR_F, ">0", + IRNode.VECTOR_MASK_CMP_F, ">0", + IRNode.VECTOR_BLEND_F, ">0", + IRNode.STORE_VECTOR, ">0"}, applyIfCPUFeatureOr = {"avx", "true", "asimd", "true"}) private static void testCMoveFGEforFConst(float[] a, float[] b, float[] c) { for (int i = 0; i < a.length; i++) { @@ -312,7 +348,10 @@ private static void testCMoveFGEforFConst(float[] a, float[] b, float[] c) { } @Test - @IR(counts = {IRNode.LOAD_VECTOR, ">0", IRNode.VECTOR_MASK_CMP, ">0", IRNode.VECTOR_BLEND, ">0", IRNode.STORE_VECTOR, ">0"}, + @IR(counts = {IRNode.LOAD_VECTOR_F, ">0", + IRNode.VECTOR_MASK_CMP_F, ">0", + IRNode.VECTOR_BLEND_F, ">0", + IRNode.STORE_VECTOR, ">0"}, applyIfCPUFeatureOr = {"avx", "true", "asimd", "true"}) private static void testCMoveFLTforFConst(float[] a, float[] b, float[] c) { for (int i = 0; i < a.length; i++) { @@ -321,7 +360,10 @@ private static void testCMoveFLTforFConst(float[] a, float[] b, float[] c) { } @Test - @IR(counts = {IRNode.LOAD_VECTOR, ">0", IRNode.VECTOR_MASK_CMP, ">0", IRNode.VECTOR_BLEND, ">0", IRNode.STORE_VECTOR, ">0"}, + @IR(counts = {IRNode.LOAD_VECTOR_F, ">0", + IRNode.VECTOR_MASK_CMP_F, ">0", + IRNode.VECTOR_BLEND_F, ">0", + IRNode.STORE_VECTOR, ">0"}, applyIfCPUFeatureOr = {"avx", "true", "asimd", "true"}) private static void testCMoveFLEforFConst(float[] a, float[] b, float[] c) { for (int i = 0; i < a.length; i++) { @@ -330,7 +372,10 @@ private static void testCMoveFLEforFConst(float[] a, float[] b, float[] c) { } @Test - @IR(counts = {IRNode.LOAD_VECTOR, ">0", IRNode.VECTOR_MASK_CMP, ">0", IRNode.VECTOR_BLEND, ">0", IRNode.STORE_VECTOR, ">0"}, + @IR(counts = {IRNode.LOAD_VECTOR_F, ">0", + IRNode.VECTOR_MASK_CMP_F, ">0", + IRNode.VECTOR_BLEND_F, ">0", + IRNode.STORE_VECTOR, ">0"}, applyIfCPUFeatureOr = {"avx", "true", "asimd", "true"}) private static void testCMoveFEQforFConst(float[] a, float[] b, float[] c) { for (int i = 0; i < a.length; i++) { @@ -339,7 +384,10 @@ private static void testCMoveFEQforFConst(float[] a, float[] b, float[] c) { } @Test - @IR(counts = {IRNode.LOAD_VECTOR, ">0", IRNode.VECTOR_MASK_CMP, ">0", IRNode.VECTOR_BLEND, ">0", IRNode.STORE_VECTOR, ">0"}, + @IR(counts = {IRNode.LOAD_VECTOR_F, ">0", + IRNode.VECTOR_MASK_CMP_F, ">0", + IRNode.VECTOR_BLEND_F, ">0", + IRNode.STORE_VECTOR, ">0"}, applyIfCPUFeatureOr = {"avx", "true", "asimd", "true"}) private static void testCMoveFNEQforFConst(float[] a, float[] b, float[] c) { for (int i = 0; i < a.length; i++) { @@ -348,7 +396,10 @@ private static void testCMoveFNEQforFConst(float[] a, float[] b, float[] c) { } @Test - @IR(counts = {IRNode.LOAD_VECTOR, ">0", IRNode.VECTOR_MASK_CMP, ">0", IRNode.VECTOR_BLEND, ">0", IRNode.STORE_VECTOR, ">0"}, + @IR(counts = {IRNode.LOAD_VECTOR_D, ">0", + IRNode.VECTOR_MASK_CMP_D, ">0", + IRNode.VECTOR_BLEND_D, ">0", + IRNode.STORE_VECTOR, ">0"}, applyIfCPUFeatureOr = {"avx", "true", "asimd", "true"}) private static void testCMoveDGTforDConst(double[] a, double[] b, double[] c) { for (int i = 0; i < a.length; i++) { @@ -357,7 +408,10 @@ private static void testCMoveDGTforDConst(double[] a, double[] b, double[] c) { } @Test - @IR(counts = {IRNode.LOAD_VECTOR, ">0", IRNode.VECTOR_MASK_CMP, ">0", IRNode.VECTOR_BLEND, ">0", IRNode.STORE_VECTOR, ">0"}, + @IR(counts = {IRNode.LOAD_VECTOR_D, ">0", + IRNode.VECTOR_MASK_CMP_D, ">0", + IRNode.VECTOR_BLEND_D, ">0", + IRNode.STORE_VECTOR, ">0"}, applyIfCPUFeatureOr = {"avx", "true", "asimd", "true"}) private static void testCMoveDGEforDConst(double[] a, double[] b, double[] c) { for (int i = 0; i < a.length; i++) { @@ -366,7 +420,10 @@ private static void testCMoveDGEforDConst(double[] a, double[] b, double[] c) { } @Test - @IR(counts = {IRNode.LOAD_VECTOR, ">0", IRNode.VECTOR_MASK_CMP, ">0", IRNode.VECTOR_BLEND, ">0", IRNode.STORE_VECTOR, ">0"}, + @IR(counts = {IRNode.LOAD_VECTOR_D, ">0", + IRNode.VECTOR_MASK_CMP_D, ">0", + IRNode.VECTOR_BLEND_D, ">0", + IRNode.STORE_VECTOR, ">0"}, applyIfCPUFeatureOr = {"avx", "true", "asimd", "true"}) private static void testCMoveDLTforDConst(double[] a, double[] b, double[] c) { for (int i = 0; i < a.length; i++) { @@ -375,7 +432,10 @@ private static void testCMoveDLTforDConst(double[] a, double[] b, double[] c) { } @Test - @IR(counts = {IRNode.LOAD_VECTOR, ">0", IRNode.VECTOR_MASK_CMP, ">0", IRNode.VECTOR_BLEND, ">0", IRNode.STORE_VECTOR, ">0"}, + @IR(counts = {IRNode.LOAD_VECTOR_D, ">0", + IRNode.VECTOR_MASK_CMP_D, ">0", + IRNode.VECTOR_BLEND_D, ">0", + IRNode.STORE_VECTOR, ">0"}, applyIfCPUFeatureOr = {"avx", "true", "asimd", "true"}) private static void testCMoveDLEforDConst(double[] a, double[] b, double[] c) { for (int i = 0; i < a.length; i++) { @@ -384,7 +444,10 @@ private static void testCMoveDLEforDConst(double[] a, double[] b, double[] c) { } @Test - @IR(counts = {IRNode.LOAD_VECTOR, ">0", IRNode.VECTOR_MASK_CMP, ">0", IRNode.VECTOR_BLEND, ">0", IRNode.STORE_VECTOR, ">0"}, + @IR(counts = {IRNode.LOAD_VECTOR_D, ">0", + IRNode.VECTOR_MASK_CMP_D, ">0", + IRNode.VECTOR_BLEND_D, ">0", + IRNode.STORE_VECTOR, ">0"}, applyIfCPUFeatureOr = {"avx", "true", "asimd", "true"}) private static void testCMoveDEQforDConst(double[] a, double[] b, double[] c) { for (int i = 0; i < a.length; i++) { @@ -393,7 +456,10 @@ private static void testCMoveDEQforDConst(double[] a, double[] b, double[] c) { } @Test - @IR(counts = {IRNode.LOAD_VECTOR, ">0", IRNode.VECTOR_MASK_CMP, ">0", IRNode.VECTOR_BLEND, ">0", IRNode.STORE_VECTOR, ">0"}, + @IR(counts = {IRNode.LOAD_VECTOR_D, ">0", + IRNode.VECTOR_MASK_CMP_D, ">0", + IRNode.VECTOR_BLEND_D, ">0", + IRNode.STORE_VECTOR, ">0"}, applyIfCPUFeatureOr = {"avx", "true", "asimd", "true"}) private static void testCMoveDNEQforDConst(double[] a, double[] b, double[] c) { for (int i = 0; i < a.length; i++) { @@ -408,7 +474,7 @@ private static void testCMoveDNEQforDConst(double[] a, double[] b, double[] c) { // compilation does not know that). // So far, vectorization only works for CMoveF/D, with same data-width comparison (F/I for F, D/L for D). @Test - @IR(failOn = {IRNode.VECTOR_MASK_CMP, IRNode.VECTOR_BLEND}) + @IR(failOn = {IRNode.STORE_VECTOR}) private static void testCMoveIGTforI(int[] a, int[] b, int[] c, int[] d, int[] r, int[] r2) { for (int i = 0; i < a.length; i++) { int cc = c[i]; @@ -419,7 +485,7 @@ private static void testCMoveIGTforI(int[] a, int[] b, int[] c, int[] d, int[] r } @Test - @IR(failOn = {IRNode.VECTOR_MASK_CMP, IRNode.VECTOR_BLEND}) + @IR(failOn = {IRNode.STORE_VECTOR}) private static void testCMoveIGTforL(int[] a, int[] b, long[] c, long[] d, long[] r, long[] r2) { for (int i = 0; i < a.length; i++) { long cc = c[i]; @@ -430,7 +496,11 @@ private static void testCMoveIGTforL(int[] a, int[] b, long[] c, long[] d, long[ } @Test - @IR(counts = {IRNode.LOAD_VECTOR, ">0", IRNode.VECTOR_MASK_CMP, ">0", IRNode.VECTOR_BLEND, ">0", IRNode.STORE_VECTOR, ">0"}, + @IR(counts = {IRNode.LOAD_VECTOR_I, IRNode.VECTOR_SIZE + "min(max_int, max_float)", ">0", + IRNode.LOAD_VECTOR_F, IRNode.VECTOR_SIZE + "min(max_int, max_float)", ">0", + IRNode.VECTOR_MASK_CMP_I, IRNode.VECTOR_SIZE + "min(max_int, max_float)", ">0", + IRNode.VECTOR_BLEND_F, IRNode.VECTOR_SIZE + "min(max_int, max_float)", ">0", + IRNode.STORE_VECTOR, ">0"}, applyIfCPUFeatureOr = {"avx", "true", "asimd", "true"}) private static void testCMoveIGTforF(int[] a, int[] b, float[] c, float[] d, float[] r, float[] r2) { for (int i = 0; i < a.length; i++) { @@ -442,7 +512,7 @@ private static void testCMoveIGTforF(int[] a, int[] b, float[] c, float[] d, flo } @Test - @IR(failOn = {IRNode.VECTOR_MASK_CMP, IRNode.VECTOR_BLEND}) + @IR(failOn = {IRNode.STORE_VECTOR}) private static void testCMoveIGTforD(int[] a, int[] b, double[] c, double[] d, double[] r, double[] r2) { for (int i = 0; i < a.length; i++) { double cc = c[i]; @@ -453,7 +523,7 @@ private static void testCMoveIGTforD(int[] a, int[] b, double[] c, double[] d, d } @Test - @IR(failOn = {IRNode.VECTOR_MASK_CMP, IRNode.VECTOR_BLEND}) + @IR(failOn = {IRNode.STORE_VECTOR}) private static void testCMoveLGTforI(long[] a, long[] b, int[] c, int[] d, int[] r, int[] r2) { for (int i = 0; i < a.length; i++) { int cc = c[i]; @@ -464,7 +534,7 @@ private static void testCMoveLGTforI(long[] a, long[] b, int[] c, int[] d, int[] } @Test - @IR(failOn = {IRNode.VECTOR_MASK_CMP, IRNode.VECTOR_BLEND}) + @IR(failOn = {IRNode.STORE_VECTOR}) private static void testCMoveLGTforL(long[] a, long[] b, long[] c, long[] d, long[] r, long[] r2) { for (int i = 0; i < a.length; i++) { long cc = c[i]; @@ -475,7 +545,7 @@ private static void testCMoveLGTforL(long[] a, long[] b, long[] c, long[] d, lon } @Test - @IR(failOn = {IRNode.VECTOR_MASK_CMP, IRNode.VECTOR_BLEND}) + @IR(failOn = {IRNode.STORE_VECTOR}) private static void testCMoveLGTforF(long[] a, long[] b, float[] c, float[] d, float[] r, float[] r2) { for (int i = 0; i < a.length; i++) { float cc = c[i]; @@ -486,7 +556,11 @@ private static void testCMoveLGTforF(long[] a, long[] b, float[] c, float[] d, f } @Test - @IR(counts = {IRNode.LOAD_VECTOR, ">0", IRNode.VECTOR_MASK_CMP, ">0", IRNode.VECTOR_BLEND, ">0", IRNode.STORE_VECTOR, ">0"}, + @IR(counts = {IRNode.LOAD_VECTOR_L, IRNode.VECTOR_SIZE + "min(max_long, max_double)", ">0", + IRNode.LOAD_VECTOR_D, IRNode.VECTOR_SIZE + "min(max_long, max_double)", ">0", + IRNode.VECTOR_MASK_CMP_L, IRNode.VECTOR_SIZE + "min(max_long, max_double)", ">0", + IRNode.VECTOR_BLEND_D, IRNode.VECTOR_SIZE + "min(max_long, max_double)", ">0", + IRNode.STORE_VECTOR, ">0"}, applyIfCPUFeatureOr = {"avx2", "true", "asimd", "true"}) // Requires avx2, else L is restricted to 16 byte, and D has 32. That leads to a vector elements mismatch of 2 to 4. private static void testCMoveLGTforD(long[] a, long[] b, double[] c, double[] d, double[] r, double[] r2) { @@ -499,7 +573,7 @@ private static void testCMoveLGTforD(long[] a, long[] b, double[] c, double[] d, } @Test - @IR(failOn = {IRNode.VECTOR_MASK_CMP, IRNode.VECTOR_BLEND}) + @IR(failOn = {IRNode.STORE_VECTOR}) private static void testCMoveFGTforI(float[] a, float[] b, int[] c, int[] d, int[] r, int[] r2) { for (int i = 0; i < a.length; i++) { int cc = c[i]; @@ -510,7 +584,7 @@ private static void testCMoveFGTforI(float[] a, float[] b, int[] c, int[] d, int } @Test - @IR(failOn = {IRNode.VECTOR_MASK_CMP, IRNode.VECTOR_BLEND}) + @IR(failOn = {IRNode.STORE_VECTOR}) private static void testCMoveFGTforL(float[] a, float[] b, long[] c, long[] d, long[] r, long[] r2) { for (int i = 0; i < a.length; i++) { long cc = c[i]; @@ -521,7 +595,10 @@ private static void testCMoveFGTforL(float[] a, float[] b, long[] c, long[] d, l } @Test - @IR(counts = {IRNode.LOAD_VECTOR, ">0", IRNode.VECTOR_MASK_CMP, ">0", IRNode.VECTOR_BLEND, ">0", IRNode.STORE_VECTOR, ">0"}, + @IR(counts = {IRNode.LOAD_VECTOR_F, ">0", + IRNode.VECTOR_MASK_CMP_F, ">0", + IRNode.VECTOR_BLEND_F, ">0", + IRNode.STORE_VECTOR, ">0"}, applyIfCPUFeatureOr = {"avx", "true", "asimd", "true"}) private static void testCMoveFGTforF(float[] a, float[] b, float[] c, float[] d, float[] r, float[] r2) { for (int i = 0; i < a.length; i++) { @@ -533,7 +610,7 @@ private static void testCMoveFGTforF(float[] a, float[] b, float[] c, float[] d, } @Test - @IR(failOn = {IRNode.VECTOR_MASK_CMP, IRNode.VECTOR_BLEND}) + @IR(failOn = {IRNode.STORE_VECTOR}) private static void testCMoveFGTforD(float[] a, float[] b, double[] c, double[] d, double[] r, double[] r2) { for (int i = 0; i < a.length; i++) { double cc = c[i]; @@ -544,7 +621,7 @@ private static void testCMoveFGTforD(float[] a, float[] b, double[] c, double[] } @Test - @IR(failOn = {IRNode.VECTOR_MASK_CMP, IRNode.VECTOR_BLEND}) + @IR(failOn = {IRNode.STORE_VECTOR}) private static void testCMoveDGTforI(double[] a, double[] b, int[] c, int[] d, int[] r, int[] r2) { for (int i = 0; i < a.length; i++) { int cc = c[i]; @@ -555,7 +632,7 @@ private static void testCMoveDGTforI(double[] a, double[] b, int[] c, int[] d, i } @Test - @IR(failOn = {IRNode.VECTOR_MASK_CMP, IRNode.VECTOR_BLEND}) + @IR(failOn = {IRNode.STORE_VECTOR}) private static void testCMoveDGTforL(double[] a, double[] b, long[] c, long[] d, long[] r, long[] r2) { for (int i = 0; i < a.length; i++) { long cc = c[i]; @@ -566,7 +643,7 @@ private static void testCMoveDGTforL(double[] a, double[] b, long[] c, long[] d, } @Test - @IR(failOn = {IRNode.VECTOR_MASK_CMP, IRNode.VECTOR_BLEND}) + @IR(failOn = {IRNode.STORE_VECTOR}) private static void testCMoveDGTforF(double[] a, double[] b, float[] c, float[] d, float[] r, float[] r2) { for (int i = 0; i < a.length; i++) { float cc = c[i]; @@ -577,7 +654,10 @@ private static void testCMoveDGTforF(double[] a, double[] b, float[] c, float[] } @Test - @IR(counts = {IRNode.LOAD_VECTOR, ">0", IRNode.VECTOR_MASK_CMP, ">0", IRNode.VECTOR_BLEND, ">0", IRNode.STORE_VECTOR, ">0"}, + @IR(counts = {IRNode.LOAD_VECTOR_D, ">0", + IRNode.VECTOR_MASK_CMP_D, ">0", + IRNode.VECTOR_BLEND_D, ">0", + IRNode.STORE_VECTOR, ">0"}, applyIfCPUFeatureOr = {"avx", "true", "asimd", "true"}) private static void testCMoveDGTforD(double[] a, double[] b, double[] c, double[] d, double[] r, double[] r2) { for (int i = 0; i < a.length; i++) { @@ -590,7 +670,10 @@ private static void testCMoveDGTforD(double[] a, double[] b, double[] c, double[ // Use some constants in the comparison @Test - @IR(counts = {IRNode.LOAD_VECTOR, ">0", IRNode.VECTOR_MASK_CMP, ">0", IRNode.VECTOR_BLEND, ">0", IRNode.STORE_VECTOR, ">0"}, + @IR(counts = {IRNode.LOAD_VECTOR_F, ">0", + IRNode.VECTOR_MASK_CMP_F, ">0", + IRNode.VECTOR_BLEND_F, ">0", + IRNode.STORE_VECTOR, ">0"}, applyIfCPUFeatureOr = {"avx", "true", "asimd", "true"}) private static void testCMoveFGTforFCmpCon1(float a, float[] b, float[] c, float[] d, float[] r, float[] r2) { for (int i = 0; i < b.length; i++) { @@ -602,7 +685,10 @@ private static void testCMoveFGTforFCmpCon1(float a, float[] b, float[] c, float } @Test - @IR(counts = {IRNode.LOAD_VECTOR, ">0", IRNode.VECTOR_MASK_CMP, ">0", IRNode.VECTOR_BLEND, ">0", IRNode.STORE_VECTOR, ">0"}, + @IR(counts = {IRNode.LOAD_VECTOR_F, ">0", + IRNode.VECTOR_MASK_CMP_F, ">0", + IRNode.VECTOR_BLEND_F, ">0", + IRNode.STORE_VECTOR, ">0"}, applyIfCPUFeatureOr = {"avx", "true", "asimd", "true"}) private static void testCMoveFGTforFCmpCon2(float[] a, float b, float[] c, float[] d, float[] r, float[] r2) { for (int i = 0; i < a.length; i++) { @@ -615,7 +701,7 @@ private static void testCMoveFGTforFCmpCon2(float[] a, float b, float[] c, float // A case that is currently not supported and is not expected to vectorize @Test - @IR(failOn = {IRNode.VECTOR_MASK_CMP, IRNode.VECTOR_BLEND}) + @IR(failOn = {IRNode.STORE_VECTOR}) private static void testCMoveVDUnsupported() { double[] doublec = new double[SIZE]; int seed = 1001; diff --git a/test/hotspot/jtreg/compiler/c2/irTests/TestVectorizationMismatchedAccess.java b/test/hotspot/jtreg/compiler/c2/irTests/TestVectorizationMismatchedAccess.java index 0e9e48160b59d..3b7bf23173051 100644 --- a/test/hotspot/jtreg/compiler/c2/irTests/TestVectorizationMismatchedAccess.java +++ b/test/hotspot/jtreg/compiler/c2/irTests/TestVectorizationMismatchedAccess.java @@ -150,7 +150,7 @@ static private void runAndVerify3(Runnable test, int offset) { } @Test - @IR(counts = { IRNode.LOAD_VECTOR, ">=1", IRNode.STORE_VECTOR, ">=1" }) + @IR(counts = { IRNode.LOAD_VECTOR_L, ">=1", IRNode.STORE_VECTOR, ">=1" }) public static void testByteLong1(byte[] dest, long[] src) { for (int i = 0; i < src.length; i++) { UNSAFE.putLongUnaligned(dest, UNSAFE.ARRAY_BYTE_BASE_OFFSET + 8 * i, src[i]); @@ -163,7 +163,7 @@ public static void testByteLong1_runner() { } @Test - @IR(counts = { IRNode.LOAD_VECTOR, ">=1", IRNode.STORE_VECTOR, ">=1" }) + @IR(counts = { IRNode.LOAD_VECTOR_L, ">=1", IRNode.STORE_VECTOR, ">=1" }) public static void testByteLong2(byte[] dest, long[] src) { for (int i = 1; i < src.length; i++) { UNSAFE.putLongUnaligned(dest, UNSAFE.ARRAY_BYTE_BASE_OFFSET + 8 * (i - 1), src[i]); @@ -176,7 +176,7 @@ public static void testByteLong2_runner() { } @Test - @IR(counts = { IRNode.LOAD_VECTOR, ">=1", IRNode.STORE_VECTOR, ">=1" }) + @IR(counts = { IRNode.LOAD_VECTOR_L, ">=1", IRNode.STORE_VECTOR, ">=1" }) public static void testByteLong3(byte[] dest, long[] src) { for (int i = 0; i < src.length - 1; i++) { UNSAFE.putLongUnaligned(dest, UNSAFE.ARRAY_BYTE_BASE_OFFSET + 8 * (i + 1), src[i]); @@ -189,7 +189,7 @@ public static void testByteLong3_runner() { } @Test - @IR(counts = { IRNode.LOAD_VECTOR, ">=1", IRNode.STORE_VECTOR, ">=1" }) + @IR(counts = { IRNode.LOAD_VECTOR_L, ">=1", IRNode.STORE_VECTOR, ">=1" }) public static void testByteLong4(byte[] dest, long[] src, int start, int stop) { for (int i = start; i < stop; i++) { UNSAFE.putLongUnaligned(dest, 8 * i + baseOffset, src[i]); @@ -203,7 +203,7 @@ public static void testByteLong4_runner() { } @Test - @IR(counts = { IRNode.LOAD_VECTOR, ">=1", IRNode.STORE_VECTOR, ">=1" }) + @IR(counts = { IRNode.LOAD_VECTOR_L, ">=1", IRNode.STORE_VECTOR, ">=1" }) public static void testByteLong5(byte[] dest, long[] src, int start, int stop) { for (int i = start; i < stop; i++) { UNSAFE.putLongUnaligned(dest, UNSAFE.ARRAY_BYTE_BASE_OFFSET + 8 * (i + baseOffset), src[i]); @@ -217,7 +217,7 @@ public static void testByteLong5_runner() { } @Test - @IR(counts = { IRNode.LOAD_VECTOR, ">=1", IRNode.STORE_VECTOR, ">=1" }) + @IR(counts = { IRNode.LOAD_VECTOR_L, ">=1", IRNode.STORE_VECTOR, ">=1" }) public static void testByteByte1(byte[] dest, byte[] src) { for (int i = 0; i < src.length / 8; i++) { UNSAFE.putLongUnaligned(dest, UNSAFE.ARRAY_BYTE_BASE_OFFSET + 8 * i, UNSAFE.getLongUnaligned(src, UNSAFE.ARRAY_BYTE_BASE_OFFSET + 8 * i)); @@ -229,9 +229,8 @@ public static void testByteByte1_runner() { runAndVerify2(() -> testByteByte1(byteArray, byteArray), 0); } - // It would be legal to vectorize this one but it's not currently @Test - //@IR(counts = { IRNode.LOAD_VECTOR, ">=1", IRNode.STORE_VECTOR, ">=1" }) + @IR(counts = { IRNode.LOAD_VECTOR_L, ">=1", IRNode.STORE_VECTOR, ">=1" }) public static void testByteByte2(byte[] dest, byte[] src) { for (int i = 1; i < src.length / 8; i++) { UNSAFE.putLongUnaligned(dest, UNSAFE.ARRAY_BYTE_BASE_OFFSET + 8 * (i - 1), UNSAFE.getLongUnaligned(src, UNSAFE.ARRAY_BYTE_BASE_OFFSET + 8 * i)); @@ -244,7 +243,7 @@ public static void testByteByte2_runner() { } @Test - @IR(failOn = { IRNode.LOAD_VECTOR, IRNode.STORE_VECTOR }) + @IR(failOn = { IRNode.LOAD_VECTOR_L, IRNode.STORE_VECTOR }) public static void testByteByte3(byte[] dest, byte[] src) { for (int i = 0; i < src.length / 8 - 1; i++) { UNSAFE.putLongUnaligned(dest, UNSAFE.ARRAY_BYTE_BASE_OFFSET + 8 * (i + 1), UNSAFE.getLongUnaligned(src, UNSAFE.ARRAY_BYTE_BASE_OFFSET + 8 * i)); @@ -257,7 +256,7 @@ public static void testByteByte3_runner() { } @Test - @IR(failOn = { IRNode.LOAD_VECTOR, IRNode.STORE_VECTOR }) + @IR(failOn = { IRNode.LOAD_VECTOR_L, IRNode.STORE_VECTOR }) public static void testByteByte4(byte[] dest, byte[] src, int start, int stop) { for (int i = start; i < stop; i++) { UNSAFE.putLongUnaligned(dest, 8 * i + baseOffset, UNSAFE.getLongUnaligned(src, UNSAFE.ARRAY_BYTE_BASE_OFFSET + 8 * i)); @@ -271,7 +270,7 @@ public static void testByteByte4_runner() { } @Test - @IR(failOn = { IRNode.LOAD_VECTOR, IRNode.STORE_VECTOR }) + @IR(failOn = { IRNode.LOAD_VECTOR_L, IRNode.STORE_VECTOR }) public static void testByteByte5(byte[] dest, byte[] src, int start, int stop) { for (int i = start; i < stop; i++) { UNSAFE.putLongUnaligned(dest, UNSAFE.ARRAY_BYTE_BASE_OFFSET + 8 * (i + baseOffset), UNSAFE.getLongUnaligned(src, UNSAFE.ARRAY_BYTE_BASE_OFFSET + 8 * i)); @@ -285,7 +284,7 @@ public static void testByteByte5_runner() { } @Test - @IR(counts = { IRNode.LOAD_VECTOR, ">=1", IRNode.STORE_VECTOR, ">=1" }) + @IR(counts = { IRNode.LOAD_VECTOR_L, ">=1", IRNode.STORE_VECTOR, ">=1" }) public static void testOffHeapLong1(long dest, long[] src) { for (int i = 0; i < src.length; i++) { UNSAFE.putLongUnaligned(null, dest + 8 * i, src[i]); @@ -298,7 +297,7 @@ public static void testOffHeapLong1_runner() { } @Test - @IR(counts = { IRNode.LOAD_VECTOR, ">=1", IRNode.STORE_VECTOR, ">=1" }) + @IR(counts = { IRNode.LOAD_VECTOR_L, ">=1", IRNode.STORE_VECTOR, ">=1" }) public static void testOffHeapLong2(long dest, long[] src) { for (int i = 1; i < src.length; i++) { UNSAFE.putLongUnaligned(null, dest + 8 * (i - 1), src[i]); @@ -311,7 +310,7 @@ public static void testOffHeapLong2_runner() { } @Test - @IR(counts = { IRNode.LOAD_VECTOR, ">=1", IRNode.STORE_VECTOR, ">=1" }) + @IR(counts = { IRNode.LOAD_VECTOR_L, ">=1", IRNode.STORE_VECTOR, ">=1" }) public static void testOffHeapLong3(long dest, long[] src) { for (int i = 0; i < src.length - 1; i++) { UNSAFE.putLongUnaligned(null, dest + 8 * (i + 1), src[i]); @@ -324,7 +323,7 @@ public static void testOffHeapLong3_runner() { } @Test - @IR(counts = { IRNode.LOAD_VECTOR, ">=1", IRNode.STORE_VECTOR, ">=1" }) + @IR(counts = { IRNode.LOAD_VECTOR_L, ">=1", IRNode.STORE_VECTOR, ">=1" }) public static void testOffHeapLong4(long dest, long[] src, int start, int stop) { for (int i = start; i < stop; i++) { UNSAFE.putLongUnaligned(null, dest + 8 * i + baseOffset, src[i]); diff --git a/test/hotspot/jtreg/compiler/c2/irTests/TestVectorizationMultiInvar.java b/test/hotspot/jtreg/compiler/c2/irTests/TestVectorizationMultiInvar.java index 6b5c886cf8648..72276254ab224 100644 --- a/test/hotspot/jtreg/compiler/c2/irTests/TestVectorizationMultiInvar.java +++ b/test/hotspot/jtreg/compiler/c2/irTests/TestVectorizationMultiInvar.java @@ -60,7 +60,7 @@ public static void main(String[] args) { static long baseOffset = 0; @Test - @IR(counts = { IRNode.LOAD_VECTOR, ">=1", IRNode.STORE_VECTOR, ">=1" }) + @IR(counts = { IRNode.LOAD_VECTOR_L, ">=1", IRNode.STORE_VECTOR, ">=1" }) public static void testByteLong1(byte[] dest, long[] src) { for (int i = 0; i < src.length; i++) { long j = Objects.checkIndex(i * 8, (long)(src.length * 8)); @@ -75,7 +75,7 @@ public static void testByteLong1_runner() { } @Test - @IR(counts = { IRNode.LOAD_VECTOR, ">=1", IRNode.STORE_VECTOR, ">=1" }) + @IR(counts = { IRNode.LOAD_VECTOR_B, ">=1", IRNode.STORE_VECTOR, ">=1" }) public static void testLoopNest1(byte[] dest, byte[] src, long start1, long stop1, long start2, long stop2, @@ -106,7 +106,7 @@ public static void testLoopNest1_runner() { } @Test - @IR(counts = { IRNode.LOAD_VECTOR, ">=1", IRNode.STORE_VECTOR, ">=1" }) + @IR(counts = { IRNode.LOAD_VECTOR_I, ">=1", IRNode.STORE_VECTOR, ">=1" }) public static void testLoopNest2(int[] dest, int[] src, long start1, long stop1, long start2, long stop2, diff --git a/test/hotspot/jtreg/compiler/c2/irTests/TestVectorizationNotRun.java b/test/hotspot/jtreg/compiler/c2/irTests/TestVectorizationNotRun.java index 26a4550c5c875..5968b7221c70c 100644 --- a/test/hotspot/jtreg/compiler/c2/irTests/TestVectorizationNotRun.java +++ b/test/hotspot/jtreg/compiler/c2/irTests/TestVectorizationNotRun.java @@ -51,7 +51,7 @@ public static void main(String[] args) { static long[] longArray = new long[size]; @Test - @IR(counts = { IRNode.LOAD_VECTOR, ">=1", IRNode.STORE_VECTOR, ">=1" }) + @IR(counts = { IRNode.LOAD_VECTOR_L, ">=1", IRNode.STORE_VECTOR, ">=1" }) public static void test(byte[] dest, long[] src) { for (int i = 0; i < src.length; i++) { if ((i < 0) || (8 > sizeBytes - i)) { diff --git a/test/hotspot/jtreg/compiler/c2/irTests/TestVectorizeTypeConversion.java b/test/hotspot/jtreg/compiler/c2/irTests/TestVectorizeTypeConversion.java index 9255bf4aeeef6..67c26ecbddfc3 100644 --- a/test/hotspot/jtreg/compiler/c2/irTests/TestVectorizeTypeConversion.java +++ b/test/hotspot/jtreg/compiler/c2/irTests/TestVectorizeTypeConversion.java @@ -55,8 +55,9 @@ public static void main(String[] args) { } @Test - @IR(counts = {IRNode.LOAD_VECTOR, ">0", - IRNode.VECTOR_CAST_I2X, ">0", + // Mixing types of different sizes has the effect that some vectors are shorter than the type allows. + @IR(counts = {IRNode.LOAD_VECTOR_I, IRNode.VECTOR_SIZE + "min(max_int, max_double)", ">0", + IRNode.VECTOR_CAST_I2D, IRNode.VECTOR_SIZE + "min(max_int, max_double)", ">0", IRNode.STORE_VECTOR, ">0"}, // The vectorization of some conversions may fail when `+AlignVector`. // We can remove the condition after JDK-8303827. @@ -68,9 +69,11 @@ private static void testConvI2D(double[] d, int[] a) { } @Test - @IR(counts = {IRNode.LOAD_VECTOR, ">0", - IRNode.VECTOR_CAST_I2X, ">0", - IRNode.VECTOR_CAST_L2X, ">0", + // Mixing types of different sizes has the effect that some vectors are shorter than the type allows. + @IR(counts = {IRNode.LOAD_VECTOR_L, IRNode.VECTOR_SIZE + "min(max_int, max_long)", ">0", + IRNode.LOAD_VECTOR_I, IRNode.VECTOR_SIZE + "min(max_int, max_long)", ">0", + IRNode.VECTOR_CAST_I2L, IRNode.VECTOR_SIZE + "min(max_int, max_long)", ">0", + IRNode.VECTOR_CAST_L2I, IRNode.VECTOR_SIZE + "min(max_int, max_long)", ">0", IRNode.STORE_VECTOR, ">0"}) private static void testConvI2L(int[] d1, int d2[], long[] a1, long[] a2) { for(int i = 0; i < d1.length; i++) { @@ -80,9 +83,11 @@ private static void testConvI2L(int[] d1, int d2[], long[] a1, long[] a2) { } @Test - @IR(counts = {IRNode.LOAD_VECTOR, ">0", - IRNode.VECTOR_CAST_D2X, ">0", - IRNode.VECTOR_CAST_F2X, ">0", + // Mixing types of different sizes has the effect that some vectors are shorter than the type allows. + @IR(counts = {IRNode.LOAD_VECTOR_F, IRNode.VECTOR_SIZE + "min(max_float, max_double)", ">0", + IRNode.LOAD_VECTOR_D, IRNode.VECTOR_SIZE + "min(max_float, max_double)", ">0", + IRNode.VECTOR_CAST_D2F, IRNode.VECTOR_SIZE + "min(max_float, max_double)", ">0", + IRNode.VECTOR_CAST_F2D, IRNode.VECTOR_SIZE + "min(max_float, max_double)", ">0", IRNode.STORE_VECTOR, ">0"}) private static void testConvF2D(double[] d1, double[] d2, float[] a1, float[] a2) { for(int i = 0; i < d1.length; i++) { diff --git a/test/hotspot/jtreg/compiler/c2/irTests/TestVectorizeURShiftSubword.java b/test/hotspot/jtreg/compiler/c2/irTests/TestVectorizeURShiftSubword.java index 187e05855ffa7..ebe3fe63ccfda 100644 --- a/test/hotspot/jtreg/compiler/c2/irTests/TestVectorizeURShiftSubword.java +++ b/test/hotspot/jtreg/compiler/c2/irTests/TestVectorizeURShiftSubword.java @@ -70,7 +70,7 @@ public static void main(String[] args) { } @Test - @IR(counts = {IRNode.LOAD_VECTOR, ">0", IRNode.RSHIFT_VB, ">0", IRNode.STORE_VECTOR, ">0"}) + @IR(counts = {IRNode.LOAD_VECTOR_B, ">0", IRNode.RSHIFT_VB, ">0", IRNode.STORE_VECTOR, ">0"}) public void testByte0() { for(int i = 0; i < NUM; i++) { byteb[i] = (byte) (bytea[i] >>> 3); @@ -78,7 +78,7 @@ public void testByte0() { } @Test - @IR(counts = {IRNode.LOAD_VECTOR, ">0", IRNode.RSHIFT_VB, ">0", IRNode.STORE_VECTOR, ">0"}) + @IR(counts = {IRNode.LOAD_VECTOR_B, ">0", IRNode.RSHIFT_VB, ">0", IRNode.STORE_VECTOR, ">0"}) public void testByte1() { for(int i = 0; i < NUM; i++) { byteb[i] = (byte) (bytea[i] >>> 24); @@ -86,7 +86,7 @@ public void testByte1() { } @Test - @IR(failOn = {IRNode.LOAD_VECTOR, IRNode.RSHIFT_VB, IRNode.STORE_VECTOR}) + @IR(failOn = {IRNode.LOAD_VECTOR_B, IRNode.RSHIFT_VB, IRNode.STORE_VECTOR}) public void testByte2() { for(int i = 0; i < NUM; i++) { byteb[i] = (byte) (bytea[i] >>> 25); @@ -94,7 +94,7 @@ public void testByte2() { } @Test - @IR(counts = {IRNode.LOAD_VECTOR, ">0", IRNode.RSHIFT_VS, ">0", IRNode.STORE_VECTOR, ">0"}) + @IR(counts = {IRNode.LOAD_VECTOR_S, ">0", IRNode.RSHIFT_VS, ">0", IRNode.STORE_VECTOR, ">0"}) public void testShort0() { for(int i = 0; i < NUM; i++) { shortb[i] = (short) (shorta[i] >>> 10); @@ -102,7 +102,7 @@ public void testShort0() { } @Test - @IR(counts = {IRNode.LOAD_VECTOR, ">0", IRNode.RSHIFT_VS, ">0", IRNode.STORE_VECTOR, ">0"}) + @IR(counts = {IRNode.LOAD_VECTOR_S, ">0", IRNode.RSHIFT_VS, ">0", IRNode.STORE_VECTOR, ">0"}) public void testShort1() { for(int i = 0; i < NUM; i++) { shortb[i] = (short) (shorta[i] >>> 16); @@ -110,7 +110,7 @@ public void testShort1() { } @Test - @IR(failOn = {IRNode.LOAD_VECTOR, IRNode.RSHIFT_VS, IRNode.STORE_VECTOR}) + @IR(failOn = {IRNode.LOAD_VECTOR_S, IRNode.RSHIFT_VS, IRNode.STORE_VECTOR}) public void testShort2() { for(int i = 0; i < NUM; i++) { shortb[i] = (short) (shorta[i] >>> 17); diff --git a/test/hotspot/jtreg/compiler/lib/ir_framework/IRNode.java b/test/hotspot/jtreg/compiler/lib/ir_framework/IRNode.java index cbd95fcac24fc..3e2db1541dd2f 100644 --- a/test/hotspot/jtreg/compiler/lib/ir_framework/IRNode.java +++ b/test/hotspot/jtreg/compiler/lib/ir_framework/IRNode.java @@ -24,6 +24,7 @@ package compiler.lib.ir_framework; import compiler.lib.ir_framework.driver.irmatching.mapping.*; +import compiler.lib.ir_framework.driver.irmatching.parser.VMInfo; import compiler.lib.ir_framework.shared.CheckedTestFrameworkException; import compiler.lib.ir_framework.shared.TestFormat; import compiler.lib.ir_framework.shared.TestFormatException; @@ -69,6 +70,17 @@ * Using this IR node expects another user provided string in the constraint list of * {@link IR#failOn()} and {@link IR#counts()}. They cannot be used as normal IR nodes. * Trying to do so will result in a format violation error. + *

  • Vector IR nodes: The IR node placeholder string contains an additional {@link #VECTOR_PREFIX}. + * Using this IR node, one can check for the type and size of a vector. The type must + * be directly specified in {@link #vectorNode}. The size can be specified directly with + * an additional argument using {@link #VECTOR_SIZE}, followed by a size tag or a comma + * separated list of sizes. If the size argument is not given, then a default size of + * {@link #VECTOR_SIZE_MAX} is taken, which is the number of elements that can fit in a + * vector of the specified type (depends on the VM flag MaxVectorSize and CPU features). + * However, when using {@link IR#failOn} or {@link IR#counts()} with comparison {@code <}, + * or {@code <=} or {@code =0}, the default size is {@link #VECTOR_SIZE_ANY}, allowing any + * size. The motivation for these default values is that in most cases one wants to have + * vectorization with maximal vector width, or no vectorization of any vector width. * */ public class IRNode { @@ -80,6 +92,11 @@ public class IRNode { * Prefix for composite IR nodes. */ private static final String COMPOSITE_PREFIX = PREFIX + "C#"; + /** + * Prefix for vector IR nodes. + */ + private static final String VECTOR_PREFIX = PREFIX + "V#"; + private static final String POSTFIX = "#_"; private static final String START = "(\\d+(\\s){2}("; @@ -90,20 +107,44 @@ public class IRNode { public static final String IS_REPLACED = "#IS_REPLACED#"; // Is replaced by an additional user-defined string. + public static final String VECTOR_SIZE = "_@"; + public static final String VECTOR_SIZE_TAG_ANY = "any"; + public static final String VECTOR_SIZE_TAG_MAX = "max_for_type"; + public static final String VECTOR_SIZE_ANY = VECTOR_SIZE + VECTOR_SIZE_TAG_ANY; // default for counts "=0" and failOn + public static final String VECTOR_SIZE_MAX = VECTOR_SIZE + VECTOR_SIZE_TAG_MAX; // default in counts + public static final String VECTOR_SIZE_2 = VECTOR_SIZE + "2"; + public static final String VECTOR_SIZE_4 = VECTOR_SIZE + "4"; + public static final String VECTOR_SIZE_8 = VECTOR_SIZE + "8"; + public static final String VECTOR_SIZE_16 = VECTOR_SIZE + "16"; + public static final String VECTOR_SIZE_32 = VECTOR_SIZE + "32"; + public static final String VECTOR_SIZE_64 = VECTOR_SIZE + "64"; + + private static final String TYPE_BYTE = "byte"; + private static final String TYPE_CHAR = "char"; + private static final String TYPE_SHORT = "short"; + private static final String TYPE_INT = "int"; + private static final String TYPE_LONG = "long"; + private static final String TYPE_FLOAT = "float"; + private static final String TYPE_DOUBLE = "double"; /** * IR placeholder string to regex-for-compile-phase map. */ private static final Map IR_NODE_MAPPINGS = new HashMap<>(); + /** + * Map every vectorNode to a type string. + */ + private static final Map VECTOR_NODE_TYPE = new HashMap<>(); + /* * Start of IR placeholder string definitions followed by a static block defining the regex-for-compile-phase mapping. * An IR node placeholder string must start with PREFIX for normal IR nodes or COMPOSITE_PREFIX for composite IR - * nodes (see class description above). + * nodes, or VECTOR_PREFIX for vector nodes (see class description above). * * An IR node definition looks like this: * - * public static final String IR_NODE = [PREFIX|COMPOSITE_PREFIX] + "IR_NODE" + POSTFIX; + * public static final String IR_NODE = [PREFIX|COMPOSITE_PREFIX|VECTOR_PREFIX] + "IR_NODE" + POSTFIX; * static { * // Define IR_NODE to regex-for-compile-phase mapping. Create a new IRNodeMapEntry object and add it to * // IR_NODE_MAPPINGS. This can be done by using the helper methods defined after all IR node placeholder string @@ -131,9 +172,36 @@ public class IRNode { beforeMatchingNameRegex(ABS_L, "AbsL"); } - public static final String ABS_V = PREFIX + "ABS_V" + POSTFIX; + public static final String ABS_VB = VECTOR_PREFIX + "ABS_VB" + POSTFIX; + static { + vectorNode(ABS_VB, "AbsVB", TYPE_BYTE); + } + + // ABS_VC / AbsVC does not exist (char is 2 byte unsigned) + + public static final String ABS_VS = VECTOR_PREFIX + "ABS_VS" + POSTFIX; + static { + vectorNode(ABS_VS, "AbsVS", TYPE_SHORT); + } + + public static final String ABS_VI = VECTOR_PREFIX + "ABS_VI" + POSTFIX; + static { + vectorNode(ABS_VI, "AbsVI", TYPE_INT); + } + + public static final String ABS_VL = VECTOR_PREFIX + "ABS_VL" + POSTFIX; + static { + vectorNode(ABS_VL, "AbsVL", TYPE_LONG); + } + + public static final String ABS_VF = VECTOR_PREFIX + "ABS_VF" + POSTFIX; + static { + vectorNode(ABS_VF, "AbsVF", TYPE_FLOAT); + } + + public static final String ABS_VD = VECTOR_PREFIX + "ABS_VD" + POSTFIX; static { - beforeMatchingNameRegex(ABS_V, "AbsV(B|S|I|L|F|D)"); + vectorNode(ABS_VD, "AbsVD", TYPE_DOUBLE); } public static final String ADD = PREFIX + "ADD" + POSTFIX; @@ -151,24 +219,34 @@ public class IRNode { beforeMatchingNameRegex(ADD_L, "AddL"); } - public static final String ADD_V = PREFIX + "ADD_V" + POSTFIX; + public static final String ADD_VD = VECTOR_PREFIX + "ADD_VD" + POSTFIX; + static { + vectorNode(ADD_VD, "AddVD", TYPE_DOUBLE); + } + + public static final String ADD_VI = VECTOR_PREFIX + "ADD_VI" + POSTFIX; static { - beforeMatchingNameRegex(ADD_V, "AddV(B|S|I|L|F|D)"); + vectorNode(ADD_VI, "AddVI", TYPE_INT); } - public static final String ADD_VD = PREFIX + "ADD_VD" + POSTFIX; + public static final String ADD_VF = VECTOR_PREFIX + "ADD_VF" + POSTFIX; static { - beforeMatchingNameRegex(ADD_VD, "AddVD"); + vectorNode(ADD_VF, "AddVF", TYPE_FLOAT); } - public static final String ADD_VI = PREFIX + "ADD_VI" + POSTFIX; + public static final String ADD_VB = VECTOR_PREFIX + "ADD_VB" + POSTFIX; static { - beforeMatchingNameRegex(ADD_VI, "AddVI"); + vectorNode(ADD_VB, "AddVB", TYPE_BYTE); } - public static final String ADD_VF = PREFIX + "ADD_VF" + POSTFIX; + public static final String ADD_VS = VECTOR_PREFIX + "ADD_VS" + POSTFIX; static { - beforeMatchingNameRegex(ADD_VF, "AddVF"); + vectorNode(ADD_VS, "AddVS", TYPE_SHORT); + } + + public static final String ADD_VL = VECTOR_PREFIX + "ADD_VL" + POSTFIX; + static { + vectorNode(ADD_VL, "AddVL", TYPE_LONG); } public static final String ADD_REDUCTION_V = PREFIX + "ADD_REDUCTION_V" + POSTFIX; @@ -235,9 +313,29 @@ public class IRNode { beforeMatchingNameRegex(AND_L, "AndL"); } - public static final String AND_V = PREFIX + "AND_V" + POSTFIX; + public static final String AND_VB = VECTOR_PREFIX + "AND_VB" + POSTFIX; + static { + vectorNode(AND_VB, "AndV", TYPE_BYTE); + } + + public static final String AND_VC = VECTOR_PREFIX + "AND_VC" + POSTFIX; + static { + vectorNode(AND_VC, "AndV", TYPE_CHAR); + } + + public static final String AND_VS = VECTOR_PREFIX + "AND_VS" + POSTFIX; + static { + vectorNode(AND_VS, "AndV", TYPE_SHORT); + } + + public static final String AND_VI = VECTOR_PREFIX + "AND_VI" + POSTFIX; + static { + vectorNode(AND_VI, "AndV", TYPE_INT); + } + + public static final String AND_VL = VECTOR_PREFIX + "AND_VL" + POSTFIX; static { - beforeMatchingNameRegex(AND_V, "AndV"); + vectorNode(AND_VL, "AndV", TYPE_LONG); } public static final String AND_V_MASK = PREFIX + "AND_V_MASK" + POSTFIX; @@ -386,9 +484,14 @@ public class IRNode { beforeMatchingNameRegex(DIV_L, "DivL"); } - public static final String DIV_V = PREFIX + "DIV_V" + POSTFIX; + public static final String DIV_VF = VECTOR_PREFIX + "DIV_VF" + POSTFIX; static { - beforeMatchingNameRegex(DIV_V, "DivV(F|D)"); + vectorNode(DIV_VF, "DivVF", TYPE_FLOAT); + } + + public static final String DIV_VD = VECTOR_PREFIX + "DIV_VD" + POSTFIX; + static { + vectorNode(DIV_VD, "DivVD", TYPE_DOUBLE); } public static final String DYNAMIC_CALL_OF_METHOD = COMPOSITE_PREFIX + "DYNAMIC_CALL_OF_METHOD" + POSTFIX; @@ -418,9 +521,14 @@ public class IRNode { optoOnly(FIELD_ACCESS, regex); } - public static final String FMA_V = PREFIX + "FMA_V" + POSTFIX; + public static final String FMA_VF = VECTOR_PREFIX + "FMA_VF" + POSTFIX; + static { + vectorNode(FMA_VF, "FmaVF", TYPE_FLOAT); + } + + public static final String FMA_VD = VECTOR_PREFIX + "FMA_VD" + POSTFIX; static { - beforeMatchingNameRegex(FMA_V, "FmaV(F|D)"); + vectorNode(FMA_VD, "FmaVD", TYPE_DOUBLE); } public static final String IF = PREFIX + "IF" + POSTFIX; @@ -582,9 +690,39 @@ public class IRNode { loadOfNodes(LOAD_US_OF_CLASS, "LoadUS"); } - public static final String LOAD_VECTOR = PREFIX + "LOAD_VECTOR" + POSTFIX; + public static final String LOAD_VECTOR_B = VECTOR_PREFIX + "LOAD_VECTOR_B" + POSTFIX; + static { + vectorNode(LOAD_VECTOR_B, "LoadVector", TYPE_BYTE); + } + + public static final String LOAD_VECTOR_C = VECTOR_PREFIX + "LOAD_VECTOR_C" + POSTFIX; + static { + vectorNode(LOAD_VECTOR_C, "LoadVector", TYPE_CHAR); + } + + public static final String LOAD_VECTOR_S = VECTOR_PREFIX + "LOAD_VECTOR_S" + POSTFIX; + static { + vectorNode(LOAD_VECTOR_S, "LoadVector", TYPE_SHORT); + } + + public static final String LOAD_VECTOR_I = VECTOR_PREFIX + "LOAD_VECTOR_I" + POSTFIX; + static { + vectorNode(LOAD_VECTOR_I, "LoadVector", TYPE_INT); + } + + public static final String LOAD_VECTOR_L = VECTOR_PREFIX + "LOAD_VECTOR_L" + POSTFIX; + static { + vectorNode(LOAD_VECTOR_L, "LoadVector", TYPE_LONG); + } + + public static final String LOAD_VECTOR_F = VECTOR_PREFIX + "LOAD_VECTOR_F" + POSTFIX; static { - beforeMatchingNameRegex(LOAD_VECTOR, "LoadVector"); + vectorNode(LOAD_VECTOR_F, "LoadVector", TYPE_FLOAT); + } + + public static final String LOAD_VECTOR_D = VECTOR_PREFIX + "LOAD_VECTOR_D" + POSTFIX; + static { + vectorNode(LOAD_VECTOR_D, "LoadVector", TYPE_DOUBLE); } public static final String LOAD_VECTOR_GATHER = PREFIX + "LOAD_VECTOR_GATHER" + POSTFIX; @@ -624,9 +762,29 @@ public class IRNode { beforeMatchingNameRegex(LSHIFT_L, "LShiftL"); } - public static final String LSHIFT_V = PREFIX + "LSHIFT_V" + POSTFIX; + public static final String LSHIFT_VB = VECTOR_PREFIX + "LSHIFT_VB" + POSTFIX; + static { + vectorNode(LSHIFT_VB, "LShiftVB", TYPE_BYTE); + } + + public static final String LSHIFT_VS = VECTOR_PREFIX + "LSHIFT_VS" + POSTFIX; + static { + vectorNode(LSHIFT_VS, "LShiftVS", TYPE_SHORT); + } + + public static final String LSHIFT_VC = VECTOR_PREFIX + "LSHIFT_VC" + POSTFIX; static { - beforeMatchingNameRegex(LSHIFT_V, "LShiftV(B|S|I|L)"); + vectorNode(LSHIFT_VC, "LShiftVS", TYPE_CHAR); // using short op with char type + } + + public static final String LSHIFT_VI = VECTOR_PREFIX + "LSHIFT_VI" + POSTFIX; + static { + vectorNode(LSHIFT_VI, "LShiftVI", TYPE_INT); + } + + public static final String LSHIFT_VL = VECTOR_PREFIX + "LSHIFT_VL" + POSTFIX; + static { + vectorNode(LSHIFT_VL, "LShiftVL", TYPE_LONG); } public static final String MACRO_LOGIC_V = PREFIX + "MACRO_LOGIC_V" + POSTFIX; @@ -669,9 +827,19 @@ public class IRNode { beforeMatchingNameRegex(MAX_L, "MaxL"); } - public static final String MAX_V = PREFIX + "MAX_V" + POSTFIX; + public static final String MAX_VI = VECTOR_PREFIX + "MAX_VI" + POSTFIX; static { - beforeMatchingNameRegex(MAX_V, "MaxV"); + vectorNode(MAX_VI, "MaxV", TYPE_INT); + } + + public static final String MAX_VF = VECTOR_PREFIX + "MAX_VF" + POSTFIX; + static { + vectorNode(MAX_VF, "MaxV", TYPE_FLOAT); + } + + public static final String MAX_VD = VECTOR_PREFIX + "MAX_VD" + POSTFIX; + static { + vectorNode(MAX_VD, "MaxV", TYPE_DOUBLE); } public static final String MEMBAR = PREFIX + "MEMBAR" + POSTFIX; @@ -719,9 +887,19 @@ public class IRNode { beforeMatchingNameRegex(MIN_L, "MinL"); } - public static final String MIN_V = PREFIX + "MIN_V" + POSTFIX; + public static final String MIN_VI = VECTOR_PREFIX + "MIN_VI" + POSTFIX; + static { + vectorNode(MIN_VI, "MinV", TYPE_INT); + } + + public static final String MIN_VF = VECTOR_PREFIX + "MIN_VF" + POSTFIX; static { - beforeMatchingNameRegex(MIN_V, "MinV"); + vectorNode(MIN_VF, "MinV", TYPE_FLOAT); + } + + public static final String MIN_VD = VECTOR_PREFIX + "MIN_VD" + POSTFIX; + static { + vectorNode(MIN_VD, "MinV", TYPE_DOUBLE); } public static final String MUL = PREFIX + "MUL" + POSTFIX; @@ -749,29 +927,34 @@ public class IRNode { beforeMatchingNameRegex(MUL_L, "MulL"); } - public static final String MUL_V = PREFIX + "MUL_V" + POSTFIX; + public static final String MUL_VL = VECTOR_PREFIX + "MUL_VL" + POSTFIX; + static { + vectorNode(MUL_VL, "MulVL", TYPE_LONG); + } + + public static final String MUL_VI = VECTOR_PREFIX + "MUL_VI" + POSTFIX; static { - beforeMatchingNameRegex(MUL_V, "MulV(B|S|I|L|F|D)"); + vectorNode(MUL_VI, "MulVI", TYPE_INT); } - public static final String MUL_VL = PREFIX + "MUL_VL" + POSTFIX; + public static final String MUL_VF = VECTOR_PREFIX + "MUL_VF" + POSTFIX; static { - beforeMatchingNameRegex(MUL_VL, "MulVL"); + vectorNode(MUL_VF, "MulVF", TYPE_FLOAT); } - public static final String MUL_VI = PREFIX + "MUL_VI" + POSTFIX; + public static final String MUL_VD = VECTOR_PREFIX + "MUL_VD" + POSTFIX; static { - beforeMatchingNameRegex(MUL_VI, "MulVI"); + vectorNode(MUL_VD, "MulVD", TYPE_DOUBLE); } - public static final String MUL_VF = PREFIX + "MUL_VF" + POSTFIX; + public static final String MUL_VB = VECTOR_PREFIX + "MUL_VB" + POSTFIX; static { - beforeMatchingNameRegex(MUL_VF, "MulVF"); + vectorNode(MUL_VB, "MulVB", TYPE_BYTE); } - public static final String MUL_VD = PREFIX + "MUL_VD" + POSTFIX; + public static final String MUL_VS = VECTOR_PREFIX + "MUL_VS" + POSTFIX; static { - beforeMatchingNameRegex(MUL_VD, "MulVD"); + vectorNode(MUL_VS, "MulVS", TYPE_SHORT); } public static final String MUL_REDUCTION_VD = PREFIX + "MUL_REDUCTION_VD" + POSTFIX; @@ -804,9 +987,14 @@ public class IRNode { superWordNodes(MAX_REDUCTION_V, "MaxReductionV"); } - public static final String NEG_V = PREFIX + "NEG_V" + POSTFIX; + public static final String NEG_VF = VECTOR_PREFIX + "NEG_VF" + POSTFIX; static { - beforeMatchingNameRegex(NEG_V, "NegV(F|D)"); + vectorNode(NEG_VF, "NegVF", TYPE_FLOAT); + } + + public static final String NEG_VD = VECTOR_PREFIX + "NEG_VD" + POSTFIX; + static { + vectorNode(NEG_VD, "NegVD", TYPE_DOUBLE); } public static final String NOP = PREFIX + "NOP" + POSTFIX; @@ -824,9 +1012,24 @@ public class IRNode { trapNodes(NULL_CHECK_TRAP,"null_check"); } - public static final String OR_V = PREFIX + "OR_V" + POSTFIX; + public static final String OR_VB = VECTOR_PREFIX + "OR_VB" + POSTFIX; + static { + vectorNode(OR_VB, "OrV", TYPE_BYTE); + } + + public static final String OR_VS = VECTOR_PREFIX + "OR_VS" + POSTFIX; + static { + vectorNode(OR_VS, "OrV", TYPE_SHORT); + } + + public static final String OR_VI = VECTOR_PREFIX + "OR_VI" + POSTFIX; static { - beforeMatchingNameRegex(OR_V, "OrV"); + vectorNode(OR_VI, "OrV", TYPE_INT); + } + + public static final String OR_VL = VECTOR_PREFIX + "OR_VL" + POSTFIX; + static { + vectorNode(OR_VL, "OrV", TYPE_LONG); } public static final String OR_V_MASK = PREFIX + "OR_V_MASK" + POSTFIX; @@ -855,24 +1058,24 @@ public class IRNode { beforeMatchingNameRegex(POPCOUNT_L, "PopCountL"); } - public static final String POPCOUNT_VI = PREFIX + "POPCOUNT_VI" + POSTFIX; + public static final String POPCOUNT_VI = VECTOR_PREFIX + "POPCOUNT_VI" + POSTFIX; static { - superWordNodes(POPCOUNT_VI, "PopCountVI"); + vectorNode(POPCOUNT_VI, "PopCountVI", TYPE_INT); } - public static final String POPCOUNT_VL = PREFIX + "POPCOUNT_VL" + POSTFIX; + public static final String POPCOUNT_VL = VECTOR_PREFIX + "POPCOUNT_VL" + POSTFIX; static { - superWordNodes(POPCOUNT_VL, "PopCountVL"); + vectorNode(POPCOUNT_VL, "PopCountVL", TYPE_LONG); } - public static final String COUNTTRAILINGZEROS_VL = PREFIX + "COUNTTRAILINGZEROS_VL" + POSTFIX; + public static final String COUNTTRAILINGZEROS_VL = VECTOR_PREFIX + "COUNTTRAILINGZEROS_VL" + POSTFIX; static { - superWordNodes(COUNTTRAILINGZEROS_VL, "CountTrailingZerosV"); + vectorNode(COUNTTRAILINGZEROS_VL, "CountTrailingZerosV", TYPE_LONG); } - public static final String COUNTLEADINGZEROS_VL = PREFIX + "COUNTLEADINGZEROS_VL" + POSTFIX; + public static final String COUNTLEADINGZEROS_VL = VECTOR_PREFIX + "COUNTLEADINGZEROS_VL" + POSTFIX; static { - superWordNodes(COUNTLEADINGZEROS_VL, "CountLeadingZerosV"); + vectorNode(COUNTLEADINGZEROS_VL, "CountLeadingZerosV", TYPE_LONG); } public static final String POPULATE_INDEX = PREFIX + "POPULATE_INDEX" + POSTFIX; @@ -941,9 +1144,24 @@ public class IRNode { CompilePhase.BEFORE_MATCHING)); } - public static final String REVERSE_BYTES_V = PREFIX + "REVERSE_BYTES_V" + POSTFIX; + public static final String REVERSE_BYTES_VB = VECTOR_PREFIX + "REVERSE_BYTES_VB" + POSTFIX; + static { + vectorNode(REVERSE_BYTES_VB, "ReverseBytesV", TYPE_BYTE); + } + + public static final String REVERSE_BYTES_VS = VECTOR_PREFIX + "REVERSE_BYTES_VS" + POSTFIX; + static { + vectorNode(REVERSE_BYTES_VS, "ReverseBytesV", TYPE_SHORT); + } + + public static final String REVERSE_BYTES_VI = VECTOR_PREFIX + "REVERSE_BYTES_VI" + POSTFIX; + static { + vectorNode(REVERSE_BYTES_VI, "ReverseBytesV", TYPE_INT); + } + + public static final String REVERSE_BYTES_VL = VECTOR_PREFIX + "REVERSE_BYTES_VL" + POSTFIX; static { - beforeMatchingNameRegex(REVERSE_BYTES_V, "ReverseBytesV"); + vectorNode(REVERSE_BYTES_VL, "ReverseBytesV", TYPE_LONG); } public static final String REVERSE_I = PREFIX + "REVERSE_I" + POSTFIX; @@ -956,19 +1174,24 @@ public class IRNode { beforeMatchingNameRegex(REVERSE_L, "ReverseL"); } - public static final String REVERSE_V = PREFIX + "REVERSE_V" + POSTFIX; + public static final String REVERSE_VI = VECTOR_PREFIX + "REVERSE_VI" + POSTFIX; + static { + vectorNode(REVERSE_VI, "ReverseV", TYPE_INT); + } + + public static final String REVERSE_VL = VECTOR_PREFIX + "REVERSE_VL" + POSTFIX; static { - beforeMatchingNameRegex(REVERSE_V, "ReverseV"); + vectorNode(REVERSE_VL, "ReverseV", TYPE_LONG); } - public static final String ROUND_VD = PREFIX + "ROUND_VD" + POSTFIX; + public static final String ROUND_VD = VECTOR_PREFIX + "ROUND_VD" + POSTFIX; static { - beforeMatchingNameRegex(ROUND_VD, "RoundVD"); + vectorNode(ROUND_VD, "RoundVD", TYPE_LONG); } - public static final String ROUND_VF = PREFIX + "ROUND_VF" + POSTFIX; + public static final String ROUND_VF = VECTOR_PREFIX + "ROUND_VF" + POSTFIX; static { - beforeMatchingNameRegex(ROUND_VF, "RoundVF"); + vectorNode(ROUND_VF, "RoundVF", TYPE_INT); } public static final String ROTATE_LEFT = PREFIX + "ROTATE_LEFT" + POSTFIX; @@ -991,9 +1214,9 @@ public class IRNode { beforeMatchingNameRegex(ROTATE_RIGHT_V, "RotateRightV"); } - public static final String ROUND_DOUBLE_MODE_V = PREFIX + "ROUND_DOUBLE_MODE_V" + POSTFIX; + public static final String ROUND_DOUBLE_MODE_V = VECTOR_PREFIX + "ROUND_DOUBLE_MODE_V" + POSTFIX; static { - beforeMatchingNameRegex(ROUND_DOUBLE_MODE_V, "RoundDoubleModeV"); + vectorNode(ROUND_DOUBLE_MODE_V, "RoundDoubleModeV", TYPE_DOUBLE); } public static final String RSHIFT = PREFIX + "RSHIFT" + POSTFIX; @@ -1011,19 +1234,29 @@ public class IRNode { beforeMatchingNameRegex(RSHIFT_L, "RShiftL"); } - public static final String RSHIFT_VB = PREFIX + "RSHIFT_VB" + POSTFIX; + public static final String RSHIFT_VB = VECTOR_PREFIX + "RSHIFT_VB" + POSTFIX; static { - beforeMatchingNameRegex(RSHIFT_VB, "RShiftVB"); + vectorNode(RSHIFT_VB, "RShiftVB", TYPE_BYTE); } - public static final String RSHIFT_VS = PREFIX + "RSHIFT_VS" + POSTFIX; + public static final String RSHIFT_VS = VECTOR_PREFIX + "RSHIFT_VS" + POSTFIX; static { - beforeMatchingNameRegex(RSHIFT_VS, "RShiftVS"); + vectorNode(RSHIFT_VS, "RShiftVS", TYPE_SHORT); } - public static final String RSHIFT_V = PREFIX + "RSHIFT_V" + POSTFIX; + public static final String RSHIFT_VC = VECTOR_PREFIX + "RSHIFT_VC" + POSTFIX; static { - beforeMatchingNameRegex(RSHIFT_V, "RShiftV(B|S|I|L)"); + vectorNode(RSHIFT_VC, "RShiftVS", TYPE_CHAR); // short computation with char type + } + + public static final String RSHIFT_VI = VECTOR_PREFIX + "RSHIFT_VI" + POSTFIX; + static { + vectorNode(RSHIFT_VI, "RShiftVI", TYPE_INT); + } + + public static final String RSHIFT_VL = VECTOR_PREFIX + "RSHIFT_VL" + POSTFIX; + static { + vectorNode(RSHIFT_VL, "RShiftVL", TYPE_LONG); } public static final String SAFEPOINT = PREFIX + "SAFEPOINT" + POSTFIX; @@ -1037,19 +1270,24 @@ public class IRNode { optoOnly(SCOPE_OBJECT, regex); } - public static final String SIGNUM_VD = PREFIX + "SIGNUM_VD" + POSTFIX; + public static final String SIGNUM_VD = VECTOR_PREFIX + "SIGNUM_VD" + POSTFIX; static { - beforeMatchingNameRegex(SIGNUM_VD, "SignumVD"); + vectorNode(SIGNUM_VD, "SignumVD", TYPE_DOUBLE); } - public static final String SIGNUM_VF = PREFIX + "SIGNUM_VF" + POSTFIX; + public static final String SIGNUM_VF = VECTOR_PREFIX + "SIGNUM_VF" + POSTFIX; static { - beforeMatchingNameRegex(SIGNUM_VF, "SignumVF"); + vectorNode(SIGNUM_VF, "SignumVF", TYPE_FLOAT); } - public static final String SQRT_V = PREFIX + "SQRT_V" + POSTFIX; + public static final String SQRT_VF = VECTOR_PREFIX + "SQRT_VF" + POSTFIX; static { - beforeMatchingNameRegex(SQRT_V, "SqrtV(F|D)"); + vectorNode(SQRT_VF, "SqrtVF", TYPE_FLOAT); + } + + public static final String SQRT_VD = VECTOR_PREFIX + "SQRT_VD" + POSTFIX; + static { + vectorNode(SQRT_VD, "SqrtVD", TYPE_DOUBLE); } public static final String STORE = PREFIX + "STORE" + POSTFIX; @@ -1188,9 +1426,34 @@ public class IRNode { beforeMatchingNameRegex(SUB_L, "SubL"); } - public static final String SUB_V = PREFIX + "SUB_V" + POSTFIX; + public static final String SUB_VB = VECTOR_PREFIX + "SUB_VB" + POSTFIX; + static { + vectorNode(SUB_VB, "SubVB", TYPE_BYTE); + } + + public static final String SUB_VS = VECTOR_PREFIX + "SUB_VS" + POSTFIX; + static { + vectorNode(SUB_VS, "SubVS", TYPE_SHORT); + } + + public static final String SUB_VI = VECTOR_PREFIX + "SUB_VI" + POSTFIX; static { - beforeMatchingNameRegex(SUB_V, "SubV(B|S|I|L|F|D)"); + vectorNode(SUB_VI, "SubVI", TYPE_INT); + } + + public static final String SUB_VL = VECTOR_PREFIX + "SUB_VL" + POSTFIX; + static { + vectorNode(SUB_VL, "SubVL", TYPE_LONG); + } + + public static final String SUB_VF = VECTOR_PREFIX + "SUB_VF" + POSTFIX; + static { + vectorNode(SUB_VF, "SubVF", TYPE_FLOAT); + } + + public static final String SUB_VD = VECTOR_PREFIX + "SUB_VD" + POSTFIX; + static { + vectorNode(SUB_VD, "SubVD", TYPE_DOUBLE); } public static final String SUBTYPE_CHECK = PREFIX + "SUBTYPE_CHECK" + POSTFIX; @@ -1268,9 +1531,29 @@ public class IRNode { beforeMatchingNameRegex(URSHIFT_S, "URShiftS"); } - public static final String URSHIFT_V = PREFIX + "URSHIFT_V" + POSTFIX; + public static final String URSHIFT_VB = VECTOR_PREFIX + "URSHIFT_VB" + POSTFIX; static { - beforeMatchingNameRegex(URSHIFT_V, "URShiftV(B|S|I|L)"); + vectorNode(URSHIFT_VB, "URShiftVB", TYPE_BYTE); + } + + public static final String URSHIFT_VS = VECTOR_PREFIX + "URSHIFT_VS" + POSTFIX; + static { + vectorNode(URSHIFT_VS, "URShiftVS", TYPE_SHORT); + } + + public static final String URSHIFT_VC = VECTOR_PREFIX + "URSHIFT_VC" + POSTFIX; + static { + vectorNode(URSHIFT_VC, "URShiftVS", TYPE_CHAR); // short computation with char type + } + + public static final String URSHIFT_VI = VECTOR_PREFIX + "URSHIFT_VI" + POSTFIX; + static { + vectorNode(URSHIFT_VI, "URShiftVI", TYPE_INT); + } + + public static final String URSHIFT_VL = VECTOR_PREFIX + "URSHIFT_VL" + POSTFIX; + static { + vectorNode(URSHIFT_VL, "URShiftVL", TYPE_LONG); } public static final String VAND_NOT_I = PREFIX + "VAND_NOT_I" + POSTFIX; @@ -1283,54 +1566,199 @@ public class IRNode { machOnlyNameRegex(VAND_NOT_L, "vand_notL"); } - public static final String VECTOR_BLEND = PREFIX + "VECTOR_BLEND" + POSTFIX; + public static final String VECTOR_BLEND_B = VECTOR_PREFIX + "VECTOR_BLEND_B" + POSTFIX; + static { + vectorNode(VECTOR_BLEND_B, "VectorBlend", TYPE_BYTE); + } + + public static final String VECTOR_BLEND_F = VECTOR_PREFIX + "VECTOR_BLEND_F" + POSTFIX; + static { + vectorNode(VECTOR_BLEND_F, "VectorBlend", TYPE_FLOAT); + } + + public static final String VECTOR_BLEND_D = VECTOR_PREFIX + "VECTOR_BLEND_D" + POSTFIX; + static { + vectorNode(VECTOR_BLEND_D, "VectorBlend", TYPE_DOUBLE); + } + + public static final String VECTOR_MASK_CMP_I = VECTOR_PREFIX + "VECTOR_MASK_CMP_I" + POSTFIX; + static { + vectorNode(VECTOR_MASK_CMP_I, "VectorMaskCmp", TYPE_INT); + } + + public static final String VECTOR_MASK_CMP_L = VECTOR_PREFIX + "VECTOR_MASK_CMP_L" + POSTFIX; + static { + vectorNode(VECTOR_MASK_CMP_L, "VectorMaskCmp", TYPE_LONG); + } + + public static final String VECTOR_MASK_CMP_F = VECTOR_PREFIX + "VECTOR_MASK_CMP_F" + POSTFIX; + static { + vectorNode(VECTOR_MASK_CMP_F, "VectorMaskCmp", TYPE_FLOAT); + } + + public static final String VECTOR_MASK_CMP_D = VECTOR_PREFIX + "VECTOR_MASK_CMP_D" + POSTFIX; + static { + vectorNode(VECTOR_MASK_CMP_D, "VectorMaskCmp", TYPE_DOUBLE); + } + + public static final String VECTOR_CAST_B2S = VECTOR_PREFIX + "VECTOR_CAST_B2S" + POSTFIX; + static { + vectorNode(VECTOR_CAST_B2S, "VectorCastB2X", TYPE_SHORT); + } + + public static final String VECTOR_CAST_B2I = VECTOR_PREFIX + "VECTOR_CAST_B2I" + POSTFIX; + static { + vectorNode(VECTOR_CAST_B2I, "VectorCastB2X", TYPE_INT); + } + + public static final String VECTOR_CAST_B2L = VECTOR_PREFIX + "VECTOR_CAST_B2L" + POSTFIX; + static { + vectorNode(VECTOR_CAST_B2L, "VectorCastB2X", TYPE_LONG); + } + + public static final String VECTOR_CAST_B2F = VECTOR_PREFIX + "VECTOR_CAST_B2F" + POSTFIX; + static { + vectorNode(VECTOR_CAST_B2F, "VectorCastB2X", TYPE_FLOAT); + } + + public static final String VECTOR_CAST_B2D = VECTOR_PREFIX + "VECTOR_CAST_B2D" + POSTFIX; + static { + vectorNode(VECTOR_CAST_B2D, "VectorCastB2X", TYPE_DOUBLE); + } + + public static final String VECTOR_CAST_D2B = VECTOR_PREFIX + "VECTOR_CAST_D2B" + POSTFIX; + static { + vectorNode(VECTOR_CAST_D2B, "VectorCastD2X", TYPE_BYTE); + } + + public static final String VECTOR_CAST_D2S = VECTOR_PREFIX + "VECTOR_CAST_D2S" + POSTFIX; + static { + vectorNode(VECTOR_CAST_D2S, "VectorCastD2X", TYPE_SHORT); + } + + public static final String VECTOR_CAST_D2I = VECTOR_PREFIX + "VECTOR_CAST_D2I" + POSTFIX; + static { + vectorNode(VECTOR_CAST_D2I, "VectorCastD2X", TYPE_INT); + } + + public static final String VECTOR_CAST_D2L = VECTOR_PREFIX + "VECTOR_CAST_D2L" + POSTFIX; + static { + vectorNode(VECTOR_CAST_D2L, "VectorCastD2X", TYPE_LONG); + } + + public static final String VECTOR_CAST_D2F = VECTOR_PREFIX + "VECTOR_CAST_D2F" + POSTFIX; static { - beforeMatchingNameRegex(VECTOR_BLEND, "VectorBlend"); + vectorNode(VECTOR_CAST_D2F, "VectorCastD2X", TYPE_FLOAT); } - public static final String VECTOR_MASK_CMP = PREFIX + "VECTOR_MASK_CMP" + POSTFIX; + public static final String VECTOR_CAST_F2B = VECTOR_PREFIX + "VECTOR_CAST_F2B" + POSTFIX; static { - beforeMatchingNameRegex(VECTOR_MASK_CMP, "VectorMaskCmp"); + vectorNode(VECTOR_CAST_F2B, "VectorCastF2X", TYPE_BYTE); } - public static final String VECTOR_CAST_B2X = PREFIX + "VECTOR_CAST_B2X" + POSTFIX; + public static final String VECTOR_CAST_F2S = VECTOR_PREFIX + "VECTOR_CAST_F2S" + POSTFIX; static { - beforeMatchingNameRegex(VECTOR_CAST_B2X, "VectorCastB2X"); + vectorNode(VECTOR_CAST_F2S, "VectorCastF2X", TYPE_SHORT); } - public static final String VECTOR_CAST_D2X = PREFIX + "VECTOR_CAST_D2X" + POSTFIX; + public static final String VECTOR_CAST_F2I = VECTOR_PREFIX + "VECTOR_CAST_F2I" + POSTFIX; static { - beforeMatchingNameRegex(VECTOR_CAST_D2X, "VectorCastD2X"); + vectorNode(VECTOR_CAST_F2I, "VectorCastF2X", TYPE_INT); } - public static final String VECTOR_CAST_F2X = PREFIX + "VECTOR_CAST_F2X" + POSTFIX; + public static final String VECTOR_CAST_F2L = VECTOR_PREFIX + "VECTOR_CAST_F2L" + POSTFIX; static { - beforeMatchingNameRegex(VECTOR_CAST_F2X, "VectorCastF2X"); + vectorNode(VECTOR_CAST_F2L, "VectorCastF2X", TYPE_LONG); } - public static final String VECTOR_CAST_I2X = PREFIX + "VECTOR_CAST_I2X" + POSTFIX; + public static final String VECTOR_CAST_F2D = VECTOR_PREFIX + "VECTOR_CAST_F2D" + POSTFIX; static { - beforeMatchingNameRegex(VECTOR_CAST_I2X, "VectorCastI2X"); + vectorNode(VECTOR_CAST_F2D, "VectorCastF2X", TYPE_DOUBLE); } - public static final String VECTOR_CAST_L2X = PREFIX + "VECTOR_CAST_L2X" + POSTFIX; + public static final String VECTOR_CAST_I2B = VECTOR_PREFIX + "VECTOR_CAST_I2B" + POSTFIX; static { - beforeMatchingNameRegex(VECTOR_CAST_L2X, "VectorCastL2X"); + vectorNode(VECTOR_CAST_I2B, "VectorCastI2X", TYPE_BYTE); } - public static final String VECTOR_CAST_S2X = PREFIX + "VECTOR_CAST_S2X" + POSTFIX; + public static final String VECTOR_CAST_I2S = VECTOR_PREFIX + "VECTOR_CAST_I2S" + POSTFIX; static { - beforeMatchingNameRegex(VECTOR_CAST_S2X, "VectorCastS2X"); + vectorNode(VECTOR_CAST_I2S, "VectorCastI2X", TYPE_SHORT); } - public static final String VECTOR_CAST_F2HF = PREFIX + "VECTOR_CAST_F2HF" + POSTFIX; + public static final String VECTOR_CAST_I2L = VECTOR_PREFIX + "VECTOR_CAST_I2L" + POSTFIX; static { - beforeMatchingNameRegex(VECTOR_CAST_F2HF, "VectorCastF2HF"); + vectorNode(VECTOR_CAST_I2L, "VectorCastI2X", TYPE_LONG); } - public static final String VECTOR_CAST_HF2F = PREFIX + "VECTOR_CAST_HF2F" + POSTFIX; + public static final String VECTOR_CAST_I2F = VECTOR_PREFIX + "VECTOR_CAST_I2F" + POSTFIX; static { - beforeMatchingNameRegex(VECTOR_CAST_HF2F, "VectorCastHF2F"); + vectorNode(VECTOR_CAST_I2F, "VectorCastI2X", TYPE_FLOAT); + } + + public static final String VECTOR_CAST_I2D = VECTOR_PREFIX + "VECTOR_CAST_I2D" + POSTFIX; + static { + vectorNode(VECTOR_CAST_I2D, "VectorCastI2X", TYPE_DOUBLE); + } + + public static final String VECTOR_CAST_L2B = VECTOR_PREFIX + "VECTOR_CAST_L2B" + POSTFIX; + static { + vectorNode(VECTOR_CAST_L2B, "VectorCastL2X", TYPE_BYTE); + } + + public static final String VECTOR_CAST_L2S = VECTOR_PREFIX + "VECTOR_CAST_L2S" + POSTFIX; + static { + vectorNode(VECTOR_CAST_L2S, "VectorCastL2X", TYPE_SHORT); + } + + public static final String VECTOR_CAST_L2I = VECTOR_PREFIX + "VECTOR_CAST_L2I" + POSTFIX; + static { + vectorNode(VECTOR_CAST_L2I, "VectorCastL2X", TYPE_INT); + } + + public static final String VECTOR_CAST_L2F = VECTOR_PREFIX + "VECTOR_CAST_L2F" + POSTFIX; + static { + vectorNode(VECTOR_CAST_L2F, "VectorCastL2X", TYPE_FLOAT); + } + + public static final String VECTOR_CAST_L2D = VECTOR_PREFIX + "VECTOR_CAST_L2D" + POSTFIX; + static { + vectorNode(VECTOR_CAST_L2D, "VectorCastL2X", TYPE_DOUBLE); + } + + public static final String VECTOR_CAST_S2B = VECTOR_PREFIX + "VECTOR_CAST_S2B" + POSTFIX; + static { + vectorNode(VECTOR_CAST_S2B, "VectorCastS2X", TYPE_BYTE); + } + + public static final String VECTOR_CAST_S2I = VECTOR_PREFIX + "VECTOR_CAST_S2I" + POSTFIX; + static { + vectorNode(VECTOR_CAST_S2I, "VectorCastS2X", TYPE_INT); + } + + public static final String VECTOR_CAST_S2L = VECTOR_PREFIX + "VECTOR_CAST_S2L" + POSTFIX; + static { + vectorNode(VECTOR_CAST_S2L, "VectorCastS2X", TYPE_LONG); + } + + public static final String VECTOR_CAST_S2F = VECTOR_PREFIX + "VECTOR_CAST_S2F" + POSTFIX; + static { + vectorNode(VECTOR_CAST_S2F, "VectorCastS2X", TYPE_FLOAT); + } + + public static final String VECTOR_CAST_S2D = VECTOR_PREFIX + "VECTOR_CAST_S2D" + POSTFIX; + static { + vectorNode(VECTOR_CAST_S2D, "VectorCastS2X", TYPE_DOUBLE); + } + + public static final String VECTOR_CAST_F2HF = VECTOR_PREFIX + "VECTOR_CAST_F2HF" + POSTFIX; + static { + vectorNode(VECTOR_CAST_F2HF, "VectorCastF2HF", TYPE_SHORT); + } + + public static final String VECTOR_CAST_HF2F = VECTOR_PREFIX + "VECTOR_CAST_HF2F" + POSTFIX; + static { + vectorNode(VECTOR_CAST_HF2F, "VectorCastHF2F", TYPE_FLOAT); } public static final String VECTOR_MASK_CAST = PREFIX + "VECTOR_MASK_CAST" + POSTFIX; @@ -1343,19 +1771,34 @@ public class IRNode { beforeMatchingNameRegex(VECTOR_REINTERPRET, "VectorReinterpret"); } - public static final String VECTOR_UCAST_B2X = PREFIX + "VECTOR_UCAST_B2X" + POSTFIX; + public static final String VECTOR_UCAST_B2S = VECTOR_PREFIX + "VECTOR_UCAST_B2S" + POSTFIX; static { - beforeMatchingNameRegex(VECTOR_UCAST_B2X, "VectorUCastB2X"); + vectorNode(VECTOR_UCAST_B2S, "VectorUCastB2X", TYPE_SHORT); } - public static final String VECTOR_UCAST_I2X = PREFIX + "VECTOR_UCAST_I2X" + POSTFIX; + public static final String VECTOR_UCAST_B2I = VECTOR_PREFIX + "VECTOR_UCAST_B2I" + POSTFIX; static { - beforeMatchingNameRegex(VECTOR_UCAST_I2X, "VectorUCastI2X"); + vectorNode(VECTOR_UCAST_B2I, "VectorUCastB2X", TYPE_INT); } - public static final String VECTOR_UCAST_S2X = PREFIX + "VECTOR_UCAST_S2X" + POSTFIX; + public static final String VECTOR_UCAST_B2L = VECTOR_PREFIX + "VECTOR_UCAST_B2L" + POSTFIX; static { - beforeMatchingNameRegex(VECTOR_UCAST_S2X, "VectorUCastS2X"); + vectorNode(VECTOR_UCAST_B2L, "VectorUCastB2X", TYPE_LONG); + } + + public static final String VECTOR_UCAST_I2L = VECTOR_PREFIX + "VECTOR_UCAST_I2L" + POSTFIX; + static { + vectorNode(VECTOR_UCAST_I2L, "VectorUCastI2X", TYPE_LONG); + } + + public static final String VECTOR_UCAST_S2I = VECTOR_PREFIX + "VECTOR_UCAST_S2I" + POSTFIX; + static { + vectorNode(VECTOR_UCAST_S2I, "VectorUCastS2X", TYPE_INT); + } + + public static final String VECTOR_UCAST_S2L = VECTOR_PREFIX + "VECTOR_UCAST_S2L" + POSTFIX; + static { + vectorNode(VECTOR_UCAST_S2L, "VectorUCastS2X", TYPE_LONG); } public static final String VECTOR_TEST = PREFIX + "VECTOR_TEST" + POSTFIX; @@ -1538,9 +1981,24 @@ public class IRNode { beforeMatchingNameRegex(XOR_L, "XorL"); } - public static final String XOR_V = PREFIX + "XOR_V" + POSTFIX; + public static final String XOR_VB = VECTOR_PREFIX + "XOR_VB" + POSTFIX; + static { + vectorNode(XOR_VB, "XorV", TYPE_BYTE); + } + + public static final String XOR_VS = VECTOR_PREFIX + "XOR_VS" + POSTFIX; + static { + vectorNode(XOR_VS, "XorV", TYPE_SHORT); + } + + public static final String XOR_VI = VECTOR_PREFIX + "XOR_VI" + POSTFIX; + static { + vectorNode(XOR_VI, "XorV", TYPE_INT); + } + + public static final String XOR_VL = VECTOR_PREFIX + "XOR_VL" + POSTFIX; static { - beforeMatchingNameRegex(XOR_V, "XorV"); + vectorNode(XOR_VL, "XorV", TYPE_LONG); } public static final String XOR_V_MASK = PREFIX + "XOR_V_MASK" + POSTFIX; @@ -1563,14 +2021,24 @@ public class IRNode { machOnlyNameRegex(XOR3_SVE, "veor3_sve"); } - public static final String COMPRESS_BITSV = PREFIX + "COMPRESS_BITSV" + POSTFIX; + public static final String COMPRESS_BITS_VI = VECTOR_PREFIX + "COMPRESS_BITS_VI" + POSTFIX; + static { + vectorNode(COMPRESS_BITS_VI, "CompressBitsV", TYPE_INT); + } + + public static final String COMPRESS_BITS_VL = VECTOR_PREFIX + "COMPRESS_BITS_VL" + POSTFIX; static { - beforeMatchingNameRegex(COMPRESS_BITSV, "CompressBitsV"); + vectorNode(COMPRESS_BITS_VL, "CompressBitsV", TYPE_LONG); } - public static final String EXPAND_BITSV = PREFIX + "EXPAND_BITSV" + POSTFIX; + public static final String EXPAND_BITS_VI = VECTOR_PREFIX + "EXPAND_BITS_VI" + POSTFIX; static { - beforeMatchingNameRegex(EXPAND_BITSV, "ExpandBitsV"); + vectorNode(EXPAND_BITS_VI, "ExpandBitsV", TYPE_INT); + } + + public static final String EXPAND_BITS_VL = VECTOR_PREFIX + "EXPAND_BITS_VL" + POSTFIX; + static { + vectorNode(EXPAND_BITS_VL, "ExpandBitsV", TYPE_LONG); } public static final String Z_LOAD_P_WITH_BARRIER_FLAG = COMPOSITE_PREFIX + "Z_LOAD_P_WITH_BARRIER_FLAG" + POSTFIX; @@ -1672,6 +2140,20 @@ private static void beforeMatchingNameRegex(String irNodePlaceholder, String irN IR_NODE_MAPPINGS.put(irNodePlaceholder, new RegexTypeEntry(RegexType.IDEAL_INDEPENDENT, regex)); } + /** + * Apply {@code irNodeRegex} as regex for the IR vector node name on all machine independent ideal graph phases up to and + * including {@link CompilePhase#BEFORE_MATCHING}. Since this is a vector node, we can also check the vector element + * type {@code typeString} and the vector size (number of elements), {@see VECTOR_SIZE}. + */ + private static void vectorNode(String irNodePlaceholder, String irNodeRegex, String typeString) { + TestFramework.check(isVectorIRNode(irNodePlaceholder), "vectorNode: failed prefix check for irNodePlaceholder " + + irNodePlaceholder + " -> did you use VECTOR_PREFIX?"); + // IS_REPLACED is later replaced with the specific type and size of the vector. + String regex = START + irNodeRegex + MID + IS_REPLACED + END; + IR_NODE_MAPPINGS.put(irNodePlaceholder, new RegexTypeEntry(RegexType.IDEAL_INDEPENDENT, regex)); + VECTOR_NODE_TYPE.put(irNodePlaceholder, typeString); + } + private static void allocNodes(String irNode, String irNodeName, String optoRegex) { String idealIndependentRegex = START + irNodeName + "\\b" + MID + END; Map intervalToRegexMap = new HashMap<>(); @@ -1787,6 +2269,149 @@ public static boolean isCompositeIRNode(String irCompositeNodeString) { return irCompositeNodeString.startsWith(COMPOSITE_PREFIX); } + /** + * Is {@code irVectorNodeString} an IR vector node placeholder string? + */ + public static boolean isVectorIRNode(String irVectorNodeString) { + return irVectorNodeString.startsWith(VECTOR_PREFIX); + } + + /** + * Is {@code irVectorSizeString} a vector size string? + */ + public static boolean isVectorSize(String irVectorSizeString) { + return irVectorSizeString.startsWith(VECTOR_SIZE); + } + + /** + * Parse {@code sizeString} and generate a regex pattern to match for the size in the IR dump. + */ + public static String parseVectorNodeSize(String sizeString, String typeString, VMInfo vmInfo) { + if (sizeString.equals(VECTOR_SIZE_TAG_ANY)) { + return "\\\\d+"; // match with any number + } + // Try to parse any tags, convert to comma separated list of ints + sizeString = parseVectorNodeSizeTag(sizeString, typeString, vmInfo); + // Parse comma separated list of numbers + String[] sizes = sizeString.split(","); + String regex = ""; + for (int i = 0; i < sizes.length; i++) { + int size = 0; + try { + size = Integer.parseInt(sizes[i]); + } catch (NumberFormatException e) { + throw new TestFormatException("Vector node has invalid size \"" + sizes[i] + "\", in \"" + sizeString + "\""); + } + TestFormat.checkNoReport(size > 1, "Vector node size must be 2 or larger, but got \"" + sizes[i] + "\", in \"" + sizeString + "\""); + regex += ((i > 0) ? "|" : "") + size; + } + if (sizes.length > 1) { + regex = "(" + regex + ")"; + } + return regex; + } + + /** + * If {@code sizeTagString} is a size tag, return the list of accepted sizes, else return sizeTagString. + */ + public static String parseVectorNodeSizeTag(String sizeTagString, String typeString, VMInfo vmInfo) { + // Parse out "min(a,b,c,...)" + if (sizeTagString.startsWith("min(") && sizeTagString.endsWith(")")) { + return parseVectorNodeSizeTagMin(sizeTagString, typeString, vmInfo); + } + + // Parse individual tags + return switch (sizeTagString) { + case VECTOR_SIZE_TAG_MAX -> String.valueOf(getMaxElementsForType(typeString, vmInfo)); + case "max_byte" -> String.valueOf(getMaxElementsForType(TYPE_BYTE, vmInfo)); + case "max_char" -> String.valueOf(getMaxElementsForType(TYPE_CHAR, vmInfo)); + case "max_short" -> String.valueOf(getMaxElementsForType(TYPE_SHORT, vmInfo)); + case "max_int" -> String.valueOf(getMaxElementsForType(TYPE_INT, vmInfo)); + case "max_long" -> String.valueOf(getMaxElementsForType(TYPE_LONG, vmInfo)); + case "max_float" -> String.valueOf(getMaxElementsForType(TYPE_FLOAT, vmInfo)); + case "max_double" -> String.valueOf(getMaxElementsForType(TYPE_DOUBLE, vmInfo)); + case "LoopMaxUnroll" -> String.valueOf(vmInfo.getLongValue("LoopMaxUnroll")); + default -> sizeTagString; + }; + } + + /** + * Parse {@code sizeTagString}, which must be a min-clause. + */ + public static String parseVectorNodeSizeTagMin(String sizeTagString, String typeString, VMInfo vmInfo) { + String[] tags = sizeTagString.substring(4, sizeTagString.length() - 1).split(","); + TestFormat.checkNoReport(tags.length > 1, "Vector node size \"min(...)\" must have at least 2 comma separated arguments, got \"" + sizeTagString + "\""); + int minVal = 1024; + for (int i = 0; i < tags.length; i++) { + String tag = parseVectorNodeSizeTag(tags[i].trim(), typeString, vmInfo); + int tag_val = 0; + try { + tag_val = Integer.parseInt(tag); + } catch (NumberFormatException e) { + throw new TestFormatException("Vector node has invalid size in \"min(...)\", argument " + i + ", \"" + tag + "\", in \"" + sizeTagString + "\""); + } + minVal = Math.min(minVal, tag_val); + } + return String.valueOf(minVal); + } + + /** + * Return maximal number of elements that can fit in a vector of the specified type. + */ + public static long getMaxElementsForType(String typeString, VMInfo vmInfo) { + long maxVectorSize = vmInfo.getLongValue("MaxVectorSize"); + TestFormat.checkNoReport(maxVectorSize > 0, "VMInfo: MaxVectorSize is not larger than zero"); + long maxBytes = maxVectorSize; + + if (Platform.isX64() || Platform.isX86()) { + maxBytes = Math.min(maxBytes, getMaxElementsForTypeOnX86(typeString, vmInfo)); + } + + // compute elements per vector: vector bytes divided by bytes per element + int bytes = getTypeSizeInBytes(typeString); + return maxBytes / bytes; + } + + /** + * Return maximal number of elements that can fit in a vector of the specified type, on x86 / x64. + */ + public static long getMaxElementsForTypeOnX86(String typeString, VMInfo vmInfo) { + // restrict maxBytes for specific features, see Matcher::vector_width_in_bytes in x86.ad: + boolean avx1 = vmInfo.hasCPUFeature("avx"); + boolean avx2 = vmInfo.hasCPUFeature("avx2"); + boolean avx512 = vmInfo.hasCPUFeature("avx512f"); + boolean avx512bw = vmInfo.hasCPUFeature("avx512bw"); + long maxBytes; + if (avx512) { + maxBytes = 64; + } else if (avx2) { + maxBytes = 32; + } else { + maxBytes = 16; + } + if (avx1 && (typeString.equals(TYPE_FLOAT) || typeString.equals(TYPE_DOUBLE))) { + maxBytes = avx512 ? 64 : 32; + } + if (avx512 && (typeString.equals(TYPE_BYTE) || typeString.equals(TYPE_SHORT) || typeString.equals(TYPE_CHAR))) { + maxBytes = avx512bw ? 64 : 32; + } + + return maxBytes; + } + + /** + * Return size in bytes of type named by {@code typeString}, return 0 if it does not name a type. + */ + public static int getTypeSizeInBytes(String typeString) { + return switch (typeString) { + case TYPE_BYTE -> 1; + case TYPE_CHAR, TYPE_SHORT -> 2; + case TYPE_INT, TYPE_FLOAT -> 4; + case TYPE_LONG, TYPE_DOUBLE -> 8; + default -> 0; + }; + } + /** * Returns "IRNode.XYZ", where XYZ is one of the IR node placeholder variable names defined above. */ @@ -1796,6 +2421,10 @@ public static String getIRNodeAccessString(String irNodeString) { TestFramework.check(irNodeString.length() > COMPOSITE_PREFIX.length() + POSTFIX.length(), "Invalid composite node placeholder: " + irNodeString); prefixLength = COMPOSITE_PREFIX.length(); + } else if (isVectorIRNode(irNodeString)) { + TestFramework.check(irNodeString.length() > VECTOR_PREFIX.length() + POSTFIX.length(), + "Invalid vector node placeholder: " + irNodeString); + prefixLength = VECTOR_PREFIX.length(); } else { prefixLength = PREFIX.length(); } @@ -1870,4 +2499,11 @@ public static CompilePhase getDefaultPhase(String irNode) { TestFormat.checkNoReport(entry != null, failMsg); return entry.defaultCompilePhase(); } + + public static String getVectorNodeType(String irNode) { + String typeString = VECTOR_NODE_TYPE.get(irNode); + String failMsg = "\"" + irNode + "\" is not a Vector IR node defined in class IRNode"; + TestFormat.check(typeString != null, failMsg); + return typeString; + } } diff --git a/test/hotspot/jtreg/compiler/lib/ir_framework/README.md b/test/hotspot/jtreg/compiler/lib/ir_framework/README.md index 90ac86740966a..2297b6bbc17c4 100644 --- a/test/hotspot/jtreg/compiler/lib/ir_framework/README.md +++ b/test/hotspot/jtreg/compiler/lib/ir_framework/README.md @@ -71,6 +71,26 @@ public void test() { } ``` +#### Vector IR Nodes +For vector nodes, we not only check for the presence of the node, but also its type and size (number of elements in the vector). Every node has an associated type, for example `IRNode.LOAD_VECTOR_I` has type `int` and `IRNode.LOAD_VECTOR_F` has type `float`. The size can be explicitly specified as an additional argument. For example: + +``` +@IR(counts = {IRNode.LOAD_VECTOR_F, IRNode.VECTOR_SIZE_16, "> 0"}, + applyIf = {"MaxVectorSize", "=64"}, + applyIfCPUFeatureOr = {"sse2", "true", "asimd", "true"}) +static float[] test() { + float[] a = new float[1024*8]; + for (int i = 0; i < a.length; i++) { + a[i]++; + } + return a; +} +``` + +However, the size does not have to be specified. In most cases, one either wants to have vectorization at the maximal possible vector width, or no vectorization at all. Hence, for lower bound counts ('>' or '>=') and equal count comparisons with strictly positive count (e.g. "=2") the default size is `IRNode.VECTOR_SIZE_MAX`, and for upper bound counts ('<' or '<=' or '=0' or failOn) the default is `IRNode.VECTOR_SIZE_ANY`. On machines with 'canTrustVectorSize == false' (default Cascade Lake) the maximal vector width is not predictable currently (32 byte for SuperWord and 64 byte for VectorAPI). Hence, on such a machine we have to automatically weaken the IR rules. All lower bound counts are performed checking with `IRNode.VECTOR_SIZE_ANY`. Upper bound counts with no user specified size are performed with `IRNode.VECTOR_SIZE_ANY` but upper bound counts with a user specified size are not checked at all. Equal count comparisons with strictly positive count are also not checked at all. Details and reasoning can be found in [RawIRNode](./driver/irmatching/irrule/checkattribute/parsing/RawIRNode.java). + +More examples can be found in [IRExample](../../../testlibrary_tests/ir_framework/examples/IRExample.java). You can also find many examples in the Vector API and SuperWord tests, when searching for `IRNode.VECTOR_SIZE` or `IRNode.LOAD_VECTOR`. + #### User-defined Regexes The user can also directly specify user-defined regexes in combination with a required compile phase (there is no default compile phase known by the framework for custom regexes). If such a user-defined regex represents a not yet supported C2 IR node, it is highly encouraged to directly add a new IR node placeholder string definition to [IRNode](./IRNode.java) for it instead together with a static regex mapping block. diff --git a/test/hotspot/jtreg/compiler/lib/ir_framework/driver/SuccessOnlyConstraintException.java b/test/hotspot/jtreg/compiler/lib/ir_framework/driver/SuccessOnlyConstraintException.java new file mode 100644 index 0000000000000..452e9a666c9d9 --- /dev/null +++ b/test/hotspot/jtreg/compiler/lib/ir_framework/driver/SuccessOnlyConstraintException.java @@ -0,0 +1,35 @@ +/* + * Copyright (c) 2023, Oracle and/or its affiliates. All rights reserved. + * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. + * + * This code is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 only, as + * published by the Free Software Foundation. + * + * This code is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License + * version 2 for more details (a copy is included in the LICENSE file that + * accompanied this code). + * + * You should have received a copy of the GNU General Public License version + * 2 along with this work; if not, write to the Free Software Foundation, + * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA. + * + * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA + * or visit www.oracle.com if you need additional information or have any + * questions. + */ + +package compiler.lib.ir_framework.driver; + +import compiler.lib.ir_framework.driver.irmatching.irrule.constraint.Constraint; + +/** + * Exception used to signal that a {@link Constraint} should always succeed. + */ +public class SuccessOnlyConstraintException extends RuntimeException { + public SuccessOnlyConstraintException(String message) { + super("Unhandled SuccessOnlyConstraintException, should have created a Constraint that always succeeds:" + System.lineSeparator() + message); + } +} diff --git a/test/hotspot/jtreg/compiler/lib/ir_framework/driver/irmatching/irmethod/IRMethod.java b/test/hotspot/jtreg/compiler/lib/ir_framework/driver/irmatching/irmethod/IRMethod.java index 40d36a6090ede..dbd431d22e048 100644 --- a/test/hotspot/jtreg/compiler/lib/ir_framework/driver/irmatching/irmethod/IRMethod.java +++ b/test/hotspot/jtreg/compiler/lib/ir_framework/driver/irmatching/irmethod/IRMethod.java @@ -31,6 +31,7 @@ import compiler.lib.ir_framework.driver.irmatching.Matchable; import compiler.lib.ir_framework.driver.irmatching.MatchableMatcher; import compiler.lib.ir_framework.driver.irmatching.irrule.IRRule; +import compiler.lib.ir_framework.driver.irmatching.parser.VMInfo; import compiler.lib.ir_framework.shared.TestFormat; import compiler.lib.ir_framework.shared.TestFormatException; @@ -50,16 +51,16 @@ public class IRMethod implements IRMethodMatchable { private final Method method; private final MatchableMatcher matcher; - public IRMethod(Method method, int[] ruleIds, IR[] irAnnos, Compilation compilation) { + public IRMethod(Method method, int[] ruleIds, IR[] irAnnos, Compilation compilation, VMInfo vmInfo) { this.method = method; - this.matcher = new MatchableMatcher(createIRRules(method, ruleIds, irAnnos, compilation)); + this.matcher = new MatchableMatcher(createIRRules(method, ruleIds, irAnnos, compilation, vmInfo)); } - private List createIRRules(Method method, int[] ruleIds, IR[] irAnnos, Compilation compilation) { + private List createIRRules(Method method, int[] ruleIds, IR[] irAnnos, Compilation compilation, VMInfo vmInfo) { List irRules = new ArrayList<>(); for (int ruleId : ruleIds) { try { - irRules.add(new IRRule(ruleId, irAnnos[ruleId - 1], compilation)); + irRules.add(new IRRule(ruleId, irAnnos[ruleId - 1], compilation, vmInfo)); } catch (TestFormatException e) { String postfixErrorMsg = " for IR rule " + ruleId + " at " + method + "."; TestFormat.failNoThrow(e.getMessage() + postfixErrorMsg); diff --git a/test/hotspot/jtreg/compiler/lib/ir_framework/driver/irmatching/irrule/IRRule.java b/test/hotspot/jtreg/compiler/lib/ir_framework/driver/irmatching/irrule/IRRule.java index ff768d6540f80..749942eabd622 100644 --- a/test/hotspot/jtreg/compiler/lib/ir_framework/driver/irmatching/irrule/IRRule.java +++ b/test/hotspot/jtreg/compiler/lib/ir_framework/driver/irmatching/irrule/IRRule.java @@ -31,6 +31,7 @@ import compiler.lib.ir_framework.driver.irmatching.MatchableMatcher; import compiler.lib.ir_framework.driver.irmatching.irrule.phase.CompilePhaseIRRule; import compiler.lib.ir_framework.driver.irmatching.irrule.phase.CompilePhaseIRRuleBuilder; +import compiler.lib.ir_framework.driver.irmatching.parser.VMInfo; /** * This class represents a generic {@link IR @IR} rule of an IR method. It contains a list of compile phase specific @@ -44,10 +45,10 @@ public class IRRule implements Matchable { private final IR irAnno; private final MatchableMatcher matcher; - public IRRule(int ruleId, IR irAnno, Compilation compilation) { + public IRRule(int ruleId, IR irAnno, Compilation compilation, VMInfo vmInfo) { this.ruleId = ruleId; this.irAnno = irAnno; - this.matcher = new MatchableMatcher(new CompilePhaseIRRuleBuilder(irAnno, compilation).build()); + this.matcher = new MatchableMatcher(new CompilePhaseIRRuleBuilder(irAnno, compilation).build(vmInfo)); } @Override diff --git a/test/hotspot/jtreg/compiler/lib/ir_framework/driver/irmatching/irrule/checkattribute/parsing/CheckAttributeReader.java b/test/hotspot/jtreg/compiler/lib/ir_framework/driver/irmatching/irrule/checkattribute/parsing/CheckAttributeReader.java index 14ba26aeb38fe..ab3a897156256 100644 --- a/test/hotspot/jtreg/compiler/lib/ir_framework/driver/irmatching/irrule/checkattribute/parsing/CheckAttributeReader.java +++ b/test/hotspot/jtreg/compiler/lib/ir_framework/driver/irmatching/irrule/checkattribute/parsing/CheckAttributeReader.java @@ -60,16 +60,34 @@ public void read(Collection result) { public final CheckAttributeString readUserPostfix(String node) { if (IRNode.isCompositeIRNode(node)) { - String irNode = IRNode.getIRNodeAccessString(node); - int nextIndex = iterator.nextIndex(); - TestFormat.checkNoReport(iterator.hasNext(), "Must provide additional value at index " + - nextIndex + " right after " + irNode); - CheckAttributeString userPostfix = new CheckAttributeString(iterator.next()); - TestFormat.checkNoReport(userPostfix.isValidUserPostfix(), "Provided empty string for composite node " + - irNode + " at index " + nextIndex); - return userPostfix; + return readUserPostfixForCompositeIRNode(node); + } else if (IRNode.isVectorIRNode(node)) { + return readUserPostfixForVectorIRNode(node); } else { return CheckAttributeString.invalid(); } } + + private final CheckAttributeString readUserPostfixForCompositeIRNode(String node) { + String irNode = IRNode.getIRNodeAccessString(node); + int nextIndex = iterator.nextIndex(); + TestFormat.checkNoReport(iterator.hasNext(), "Must provide additional value at index " + + nextIndex + " right after " + irNode); + CheckAttributeString userPostfix = new CheckAttributeString(iterator.next()); + TestFormat.checkNoReport(userPostfix.isValidUserPostfix(), "Provided empty string for composite node " + + irNode + " at index " + nextIndex); + return userPostfix; + } + + private final CheckAttributeString readUserPostfixForVectorIRNode(String node) { + if (iterator.hasNext()) { + String maybeVectorType = iterator.next(); + if (IRNode.isVectorSize(maybeVectorType)) { + return new CheckAttributeString(maybeVectorType); + } + // If we do not find that pattern, then revert the iterator once + iterator.previous(); + } + return CheckAttributeString.invalid(); + } } diff --git a/test/hotspot/jtreg/compiler/lib/ir_framework/driver/irmatching/irrule/checkattribute/parsing/RawIRNode.java b/test/hotspot/jtreg/compiler/lib/ir_framework/driver/irmatching/irrule/checkattribute/parsing/RawIRNode.java index 2684e14344ab6..e7db6c4844ca2 100644 --- a/test/hotspot/jtreg/compiler/lib/ir_framework/driver/irmatching/irrule/checkattribute/parsing/RawIRNode.java +++ b/test/hotspot/jtreg/compiler/lib/ir_framework/driver/irmatching/irrule/checkattribute/parsing/RawIRNode.java @@ -1,5 +1,5 @@ /* - * Copyright (c) 2022, Oracle and/or its affiliates. All rights reserved. + * Copyright (c) 2022, 2023, Oracle and/or its affiliates. All rights reserved. * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. * * This code is free software; you can redistribute it and/or modify it @@ -25,6 +25,10 @@ import compiler.lib.ir_framework.CompilePhase; import compiler.lib.ir_framework.IRNode; +import compiler.lib.ir_framework.shared.Comparison; +import compiler.lib.ir_framework.shared.TestFormat; +import compiler.lib.ir_framework.driver.irmatching.parser.VMInfo; +import compiler.lib.ir_framework.driver.SuccessOnlyConstraintException; /** * This class represents a "raw IR node" as read from a check attribute. It has a node part that either represents an @@ -51,14 +55,85 @@ public CompilePhase defaultCompilePhase() { return IRNode.getDefaultPhase(node); } - public String regex(CompilePhase compilePhase) { + public String regex(CompilePhase compilePhase, VMInfo vmInfo, Comparison.Bound bound) { String nodeRegex = node; if (IRNode.isIRNode(node)) { nodeRegex = IRNode.getRegexForCompilePhase(node, compilePhase); - if (userPostfix.isValid()) { + if (IRNode.isVectorIRNode(node)) { + nodeRegex = regexForVectorIRNode(nodeRegex, vmInfo, bound); + } else if (userPostfix.isValid()) { nodeRegex = nodeRegex.replaceAll(IRNode.IS_REPLACED, userPostfix.value()); } } return nodeRegex; } + + private String regexForVectorIRNode(String nodeRegex, VMInfo vmInfo, Comparison.Bound bound) { + String type = IRNode.getVectorNodeType(node); + TestFormat.checkNoReport(IRNode.getTypeSizeInBytes(type) > 0, + "Vector node's type must have valid type, got \"" + type + "\" for \"" + node + "\""); + String size = null; + if (userPostfix.isValid()) { + // Size is explicitly stated + String value = userPostfix.value(); + TestFormat.checkNoReport(value.startsWith(IRNode.VECTOR_SIZE), + "Vector node's vector size must start with IRNode.VECTOR_SIZE, got: \"" + value + "\""); + size = value.substring(2); + + if (!vmInfo.canTrustVectorSize()) { + // Parse it already just to get errors before we overwrite size + IRNode.parseVectorNodeSize(size, type, vmInfo); + } + } + + // Set default values in some cases: + if (!userPostfix.isValid() || !vmInfo.canTrustVectorSize()) { + switch (bound) { + case LOWER -> { + // For lower bound we check for the maximal size by default. But if we cannot trust the + // vector size we at least check there are vectors of any size. + if (vmInfo.canTrustVectorSize()) { + // No size specified, so assume maximal size + size = IRNode.VECTOR_SIZE_TAG_MAX; + } else { + System.out.println("WARNING: you are on a system with \"canTrustVectorSize == false\" (default Cascade Lake)."); + System.out.println(" The lower bound rule for \"" + node + "\" is now performed with"); + System.out.println(" \"IRNode.VECTOR_SIZE_TAG_ANY\" instead of \"IRNode.VECTOR_SIZE_TAG_MAX\"."); + size = IRNode.VECTOR_SIZE_TAG_ANY; + } + } + case UPPER -> { + if (userPostfix.isValid()) { + TestFormat.checkNoReport(!vmInfo.canTrustVectorSize(), "sanity"); + // If we have a size specified but cannot trust the size, and must check an upper + // bound, this can be impossible to count correctly - if we have an incorrect size + // we may count either too many nodes. We just create an impossible regex which will + // always have count zero and make the upper bound rule pass. + System.out.println("WARNING: you are on a system with \"canTrustVectorSize == false\" (default Cascade Lake)."); + System.out.println(" The upper bound rule for \"" + node + "\" cannot be checked."); + throw new SuccessOnlyConstraintException("upper bound with specified size"); + } else { + // For upper bound we check for vectors of any size by default. + size = IRNode.VECTOR_SIZE_TAG_ANY; + } + } + case EQUAL -> { + if (vmInfo.canTrustVectorSize()) { + // No size specified, so assume maximal size + size = IRNode.VECTOR_SIZE_TAG_MAX; + } else { + // Equal comparison to a strictly positive number would lead us to an impossible + // situation: we might have to know the exact vector size or else we count too many + // or too few cases. We therefore skip such a constraint and treat it as success. + System.out.println("WARNING: you are on a system with \"canTrustVectorSize == false\" (default Cascade Lake)."); + System.out.println(" The equal count comparison rule for \"" + node + "\" cannot be checked."); + throw new SuccessOnlyConstraintException("equal count comparison"); + } + } + } + } + String sizeRegex = IRNode.parseVectorNodeSize(size, type, vmInfo); + return nodeRegex.replaceAll(IRNode.IS_REPLACED, + "vector[A-Za-z]\\\\[" + sizeRegex + "\\\\]:\\\\{" + type + "\\\\}"); + } } diff --git a/test/hotspot/jtreg/compiler/lib/ir_framework/driver/irmatching/irrule/constraint/Constraint.java b/test/hotspot/jtreg/compiler/lib/ir_framework/driver/irmatching/irrule/constraint/Constraint.java index 42c1b10e518b2..02a2d5a4918ff 100644 --- a/test/hotspot/jtreg/compiler/lib/ir_framework/driver/irmatching/irrule/constraint/Constraint.java +++ b/test/hotspot/jtreg/compiler/lib/ir_framework/driver/irmatching/irrule/constraint/Constraint.java @@ -61,6 +61,12 @@ public static Constraint createCounts(String nodeRegex, int constraintId, Compar return new Constraint(new CountsConstraintCheck(nodeRegex, constraintId, comparison), nodeRegex, compilationOutput); } + public static Constraint createSuccess() { + String nodeRegex = "impossible_regex"; + String compilationOutput = ""; // empty + return new Constraint(new SuccessConstraintCheck(), nodeRegex, compilationOutput); + } + public String nodeRegex() { return nodeRegex; } diff --git a/test/hotspot/jtreg/compiler/lib/ir_framework/driver/irmatching/irrule/constraint/SuccessConstraintCheck.java b/test/hotspot/jtreg/compiler/lib/ir_framework/driver/irmatching/irrule/constraint/SuccessConstraintCheck.java new file mode 100644 index 0000000000000..f74e31828ec93 --- /dev/null +++ b/test/hotspot/jtreg/compiler/lib/ir_framework/driver/irmatching/irrule/constraint/SuccessConstraintCheck.java @@ -0,0 +1,41 @@ +/* + * Copyright (c) 2023, Oracle and/or its affiliates. All rights reserved. + * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. + * + * This code is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 only, as + * published by the Free Software Foundation. + * + * This code is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License + * version 2 for more details (a copy is included in the LICENSE file that + * accompanied this code). + * + * You should have received a copy of the GNU General Public License version + * 2 along with this work; if not, write to the Free Software Foundation, + * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA. + * + * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA + * or visit www.oracle.com if you need additional information or have any + * questions. + */ + +package compiler.lib.ir_framework.driver.irmatching.irrule.constraint; + +import compiler.lib.ir_framework.driver.irmatching.MatchResult; + +import java.util.List; + +/** + * This class provides a check that always succeeds. + * + * @see Constraint + */ +class SuccessConstraintCheck implements ConstraintCheck { + + @Override + public MatchResult check(List matchedNodes) { + return SuccessResult.getInstance(); + } +} diff --git a/test/hotspot/jtreg/compiler/lib/ir_framework/driver/irmatching/irrule/constraint/raw/RawConstraint.java b/test/hotspot/jtreg/compiler/lib/ir_framework/driver/irmatching/irrule/constraint/raw/RawConstraint.java index 03a7f127f3dbf..1c2fba218db82 100644 --- a/test/hotspot/jtreg/compiler/lib/ir_framework/driver/irmatching/irrule/constraint/raw/RawConstraint.java +++ b/test/hotspot/jtreg/compiler/lib/ir_framework/driver/irmatching/irrule/constraint/raw/RawConstraint.java @@ -27,6 +27,7 @@ import compiler.lib.ir_framework.IR; import compiler.lib.ir_framework.IRNode; import compiler.lib.ir_framework.driver.irmatching.irrule.constraint.Constraint; +import compiler.lib.ir_framework.driver.irmatching.parser.VMInfo; /** * Interface to represent a single raw constraint as found in the {@link IR @IR} annotation (i.e. {@link IRNode} @@ -38,5 +39,5 @@ */ public interface RawConstraint { CompilePhase defaultCompilePhase(); - Constraint parse(CompilePhase compilePhase, String compilationOutput); + Constraint parse(CompilePhase compilePhase, String compilationOutput, VMInfo vmInfo); } diff --git a/test/hotspot/jtreg/compiler/lib/ir_framework/driver/irmatching/irrule/constraint/raw/RawCountsConstraint.java b/test/hotspot/jtreg/compiler/lib/ir_framework/driver/irmatching/irrule/constraint/raw/RawCountsConstraint.java index 76c4a65483ce7..9934a830a0690 100644 --- a/test/hotspot/jtreg/compiler/lib/ir_framework/driver/irmatching/irrule/constraint/raw/RawCountsConstraint.java +++ b/test/hotspot/jtreg/compiler/lib/ir_framework/driver/irmatching/irrule/constraint/raw/RawCountsConstraint.java @@ -26,10 +26,15 @@ import compiler.lib.ir_framework.CompilePhase; import compiler.lib.ir_framework.IR; +import compiler.lib.ir_framework.IRNode; import compiler.lib.ir_framework.TestFramework; import compiler.lib.ir_framework.driver.irmatching.irrule.checkattribute.parsing.RawIRNode; import compiler.lib.ir_framework.driver.irmatching.irrule.constraint.Constraint; +import compiler.lib.ir_framework.driver.irmatching.parser.VMInfo; +import compiler.lib.ir_framework.driver.SuccessOnlyConstraintException; import compiler.lib.ir_framework.shared.Comparison; +import compiler.lib.ir_framework.shared.TestFormat; +import compiler.lib.ir_framework.shared.TestFormatException; /** * This class represents a raw constraint of a {@link IR#counts()} attribute. @@ -52,9 +57,49 @@ public CompilePhase defaultCompilePhase() { return rawIRNode.defaultCompilePhase(); } + private Comparison.Bound getComparisonBound() { + switch (comparison.getComparator()) { + case "<" -> { + TestFormat.checkNoReport(comparison.getGivenValue() > 0, "Node count comparison \"<" + + comparison.getGivenValue() + "\" is not allowed: always false."); + TestFormat.checkNoReport(comparison.getGivenValue() > 1, "Node count comparison \"<" + + comparison.getGivenValue() + "\" should be rewritten as \"=0\""); + return Comparison.Bound.UPPER; + } + case "<=" -> { + TestFormat.checkNoReport(comparison.getGivenValue() >= 0, "Node count comparison \"<=" + + comparison.getGivenValue() + "\" is not allowed: always false."); + TestFormat.checkNoReport(comparison.getGivenValue() >= 1, "Node count comparison \"<=" + + comparison.getGivenValue() + "\" should be rewritten as \"=0\""); + return Comparison.Bound.UPPER; + } + case "=" -> { + // "=0" is same as setting upper bound - just like for failOn. But if we compare equals a + // strictly positive number it is like setting both upper and lower bound (equal). + return comparison.getGivenValue() > 0 ? Comparison.Bound.EQUAL : Comparison.Bound.UPPER; + } + case ">" -> { + TestFormat.checkNoReport(comparison.getGivenValue() >= 0, "Node count comparison \">" + + comparison.getGivenValue() + "\" is useless, please only use positive numbers."); + return Comparison.Bound.LOWER; + } + case ">=" -> { + TestFormat.checkNoReport(comparison.getGivenValue() > 0, "Node count comparison \">=" + + comparison.getGivenValue() + "\" is useless, please only use strictly positive numbers with greater-equal."); + return Comparison.Bound.LOWER; + } + case "!=" -> throw new TestFormatException("Not-equal comparator not supported. Please rewrite the rule."); + default -> throw new TestFormatException("Comparator not handled: " + comparison.getComparator()); + } + } + @Override - public Constraint parse(CompilePhase compilePhase, String compilationOutput) { + public Constraint parse(CompilePhase compilePhase, String compilationOutput, VMInfo vmInfo) { TestFramework.check(compilePhase != CompilePhase.DEFAULT, "must not be default"); - return Constraint.createCounts(rawIRNode.regex(compilePhase), constraintIndex, comparison, compilationOutput); + try { + return Constraint.createCounts(rawIRNode.regex(compilePhase, vmInfo, getComparisonBound()), constraintIndex, comparison, compilationOutput); + } catch (SuccessOnlyConstraintException e) { + return Constraint.createSuccess(); + } } } diff --git a/test/hotspot/jtreg/compiler/lib/ir_framework/driver/irmatching/irrule/constraint/raw/RawFailOnConstraint.java b/test/hotspot/jtreg/compiler/lib/ir_framework/driver/irmatching/irrule/constraint/raw/RawFailOnConstraint.java index 18ec1936273fb..83d564ba13df7 100644 --- a/test/hotspot/jtreg/compiler/lib/ir_framework/driver/irmatching/irrule/constraint/raw/RawFailOnConstraint.java +++ b/test/hotspot/jtreg/compiler/lib/ir_framework/driver/irmatching/irrule/constraint/raw/RawFailOnConstraint.java @@ -25,9 +25,12 @@ import compiler.lib.ir_framework.CompilePhase; import compiler.lib.ir_framework.IR; +import compiler.lib.ir_framework.IRNode; import compiler.lib.ir_framework.TestFramework; +import compiler.lib.ir_framework.shared.Comparison; import compiler.lib.ir_framework.driver.irmatching.irrule.checkattribute.parsing.RawIRNode; import compiler.lib.ir_framework.driver.irmatching.irrule.constraint.Constraint; +import compiler.lib.ir_framework.driver.irmatching.parser.VMInfo; /** * This class represents a raw constraint of a {@link IR#failOn()} attribute. @@ -49,9 +52,9 @@ public CompilePhase defaultCompilePhase() { } @Override - public Constraint parse(CompilePhase compilePhase, String compilationOutput) { + public Constraint parse(CompilePhase compilePhase, String compilationOutput, VMInfo vmInfo) { TestFramework.check(compilePhase != CompilePhase.DEFAULT, "must not be default"); - return Constraint.createFailOn(rawIRNode.regex(compilePhase), constraintIndex, compilationOutput); + return Constraint.createFailOn(rawIRNode.regex(compilePhase, vmInfo, Comparison.Bound.UPPER), constraintIndex, compilationOutput); } } diff --git a/test/hotspot/jtreg/compiler/lib/ir_framework/driver/irmatching/irrule/phase/CompilePhaseIRRuleBuilder.java b/test/hotspot/jtreg/compiler/lib/ir_framework/driver/irmatching/irrule/phase/CompilePhaseIRRuleBuilder.java index 7c89ac433a6b0..5d327135c22b2 100644 --- a/test/hotspot/jtreg/compiler/lib/ir_framework/driver/irmatching/irrule/phase/CompilePhaseIRRuleBuilder.java +++ b/test/hotspot/jtreg/compiler/lib/ir_framework/driver/irmatching/irrule/phase/CompilePhaseIRRuleBuilder.java @@ -34,6 +34,7 @@ import compiler.lib.ir_framework.driver.irmatching.irrule.checkattribute.parsing.RawFailOn; import compiler.lib.ir_framework.driver.irmatching.irrule.constraint.Constraint; import compiler.lib.ir_framework.driver.irmatching.irrule.constraint.raw.RawConstraint; +import compiler.lib.ir_framework.driver.irmatching.parser.VMInfo; import compiler.lib.ir_framework.shared.TestFormat; import java.util.*; @@ -60,24 +61,24 @@ public CompilePhaseIRRuleBuilder(IR irAnno, Compilation compilation) { this.rawCountsConstraints = new RawCounts(irAnno.counts()).createRawConstraints(); } - public SortedSet build() { + public SortedSet build(VMInfo vmInfo) { CompilePhase[] compilePhases = irAnno.phase(); TestFormat.checkNoReport(new HashSet<>(List.of(compilePhases)).size() == compilePhases.length, "Cannot specify a compile phase twice"); for (CompilePhase compilePhase : compilePhases) { if (compilePhase == CompilePhase.DEFAULT) { - createCompilePhaseIRRulesForDefault(); + createCompilePhaseIRRulesForDefault(vmInfo); } else { - createCompilePhaseIRRule(compilePhase); + createCompilePhaseIRRule(compilePhase, vmInfo); } } return compilePhaseIRRules; } - private void createCompilePhaseIRRulesForDefault() { + private void createCompilePhaseIRRulesForDefault(VMInfo vmInfo) { DefaultPhaseRawConstraintParser parser = new DefaultPhaseRawConstraintParser(compilation); Map> checkAttributesForCompilePhase = - parser.parse(rawFailOnConstraints, rawCountsConstraints); + parser.parse(rawFailOnConstraints, rawCountsConstraints, vmInfo); checkAttributesForCompilePhase.forEach((compilePhase, constraints) -> { if (compilation.hasOutput(compilePhase)) { compilePhaseIRRules.add(new CompilePhaseIRRule(compilePhase, constraints, @@ -88,9 +89,9 @@ private void createCompilePhaseIRRulesForDefault() { }); } - private void createCompilePhaseIRRule(CompilePhase compilePhase) { - List failOnConstraints = parseRawConstraints(rawFailOnConstraints, compilePhase); - List countsConstraints = parseRawConstraints(rawCountsConstraints, compilePhase); + private void createCompilePhaseIRRule(CompilePhase compilePhase, VMInfo vmInfo) { + List failOnConstraints = parseRawConstraints(rawFailOnConstraints, compilePhase, vmInfo); + List countsConstraints = parseRawConstraints(rawCountsConstraints, compilePhase, vmInfo); if (compilation.hasOutput(compilePhase)) { createValidCompilePhaseIRRule(compilePhase, failOnConstraints, countsConstraints); } else { @@ -113,10 +114,11 @@ private void createValidCompilePhaseIRRule(CompilePhase compilePhase, List parseRawConstraints(List rawConstraints, - CompilePhase compilePhase) { + CompilePhase compilePhase, + VMInfo vmInfo) { List constraintResultList = new ArrayList<>(); for (RawConstraint rawConstraint : rawConstraints) { - constraintResultList.add(rawConstraint.parse(compilePhase, compilation.output(compilePhase))); + constraintResultList.add(rawConstraint.parse(compilePhase, compilation.output(compilePhase), vmInfo)); } return constraintResultList; } diff --git a/test/hotspot/jtreg/compiler/lib/ir_framework/driver/irmatching/irrule/phase/DefaultPhaseRawConstraintParser.java b/test/hotspot/jtreg/compiler/lib/ir_framework/driver/irmatching/irrule/phase/DefaultPhaseRawConstraintParser.java index cf530fb19a236..1f83788397817 100644 --- a/test/hotspot/jtreg/compiler/lib/ir_framework/driver/irmatching/irrule/phase/DefaultPhaseRawConstraintParser.java +++ b/test/hotspot/jtreg/compiler/lib/ir_framework/driver/irmatching/irrule/phase/DefaultPhaseRawConstraintParser.java @@ -31,6 +31,7 @@ import compiler.lib.ir_framework.driver.irmatching.irrule.checkattribute.FailOn; import compiler.lib.ir_framework.driver.irmatching.irrule.constraint.Constraint; import compiler.lib.ir_framework.driver.irmatching.irrule.constraint.raw.RawConstraint; +import compiler.lib.ir_framework.driver.irmatching.parser.VMInfo; import compiler.lib.ir_framework.shared.TestFrameworkException; import java.util.ArrayList; @@ -52,22 +53,26 @@ public DefaultPhaseRawConstraintParser(Compilation compilation) { } public Map> parse(List rawFailOnConstraints, - List rawCountsConstraints) { + List rawCountsConstraints, + VMInfo vmInfo) { Map failOnForCompilePhase = parseRawConstraints(rawFailOnConstraints, - CheckAttributeType.FAIL_ON); + CheckAttributeType.FAIL_ON, + vmInfo); Map countsForCompilePhase = parseRawConstraints(rawCountsConstraints, - CheckAttributeType.COUNTS); + CheckAttributeType.COUNTS, + vmInfo); return mergeCheckAttributesForCompilePhase(failOnForCompilePhase, countsForCompilePhase); } private Map parseRawConstraints(List rawConstraints, - CheckAttributeType checkAttributeType) { + CheckAttributeType checkAttributeType, + VMInfo vmInfo) { Map> matchableForCompilePhase = new HashMap<>(); for (RawConstraint rawConstraint : rawConstraints) { CompilePhase compilePhase = rawConstraint.defaultCompilePhase(); List checkAttribute = matchableForCompilePhase.computeIfAbsent(compilePhase, k -> new ArrayList<>()); - checkAttribute.add(rawConstraint.parse(compilePhase, compilation.output(compilePhase))); + checkAttribute.add(rawConstraint.parse(compilePhase, compilation.output(compilePhase), vmInfo)); } return replaceConstraintsWithCheckAttribute(matchableForCompilePhase, checkAttributeType); } diff --git a/test/hotspot/jtreg/compiler/lib/ir_framework/driver/irmatching/parser/IRMethodBuilder.java b/test/hotspot/jtreg/compiler/lib/ir_framework/driver/irmatching/parser/IRMethodBuilder.java index fb7db3e3a3b50..beed44a01c5ca 100644 --- a/test/hotspot/jtreg/compiler/lib/ir_framework/driver/irmatching/parser/IRMethodBuilder.java +++ b/test/hotspot/jtreg/compiler/lib/ir_framework/driver/irmatching/parser/IRMethodBuilder.java @@ -51,18 +51,18 @@ public IRMethodBuilder(TestMethods testMethods, LoggedMethods loggedMethods) { * Create IR methods for all test methods identified by {@link IREncodingParser} by combining them with the parsed * compilation output from {@link HotSpotPidFileParser}. */ - public SortedSet build() { + public SortedSet build(VMInfo vmInfo) { SortedSet irMethods = new TreeSet<>(); testMethods.testMethods().forEach( - (methodName, testMethod) -> irMethods.add(createIRMethod(methodName, testMethod))); + (methodName, testMethod) -> irMethods.add(createIRMethod(methodName, testMethod, vmInfo))); return irMethods; } - private IRMethodMatchable createIRMethod(String methodName, TestMethod testMethod) { + private IRMethodMatchable createIRMethod(String methodName, TestMethod testMethod, VMInfo vmInfo) { LoggedMethod loggedMethod = loggedMethods.get(methodName); if (loggedMethod != null) { return new IRMethod(testMethod.method(), testMethod.irRuleIds(), testMethod.irAnnos(), - new Compilation(loggedMethod.compilationOutput())); + new Compilation(loggedMethod.compilationOutput()), vmInfo); } else { return new NotCompiledIRMethod(testMethod.method(), testMethod.irRuleIds().length); } diff --git a/test/hotspot/jtreg/compiler/lib/ir_framework/driver/irmatching/parser/TestClassParser.java b/test/hotspot/jtreg/compiler/lib/ir_framework/driver/irmatching/parser/TestClassParser.java index ea4b0acf0bb4a..776642d460c24 100644 --- a/test/hotspot/jtreg/compiler/lib/ir_framework/driver/irmatching/parser/TestClassParser.java +++ b/test/hotspot/jtreg/compiler/lib/ir_framework/driver/irmatching/parser/TestClassParser.java @@ -54,10 +54,11 @@ public TestClassParser(Class testClass) { public Matchable parse(String hotspotPidFileName, String irEncoding) { IREncodingParser irEncodingParser = new IREncodingParser(testClass); TestMethods testMethods = irEncodingParser.parse(irEncoding); + VMInfo vmInfo = VMInfoParser.parseVMInfo(irEncoding); if (testMethods.hasTestMethods()) { HotSpotPidFileParser hotSpotPidFileParser = new HotSpotPidFileParser(testClass.getName(), testMethods); LoggedMethods loggedMethods = hotSpotPidFileParser.parse(hotspotPidFileName); - return createTestClass(testMethods, loggedMethods); + return createTestClass(testMethods, loggedMethods, vmInfo); } return new NonIRTestClass(); } @@ -66,9 +67,9 @@ public Matchable parse(String hotspotPidFileName, String irEncoding) { * Create test class with IR methods for all test methods identified by {@link IREncodingParser} by combining them * with the parsed compilation output from {@link HotSpotPidFileParser}. */ - private Matchable createTestClass(TestMethods testMethods, LoggedMethods loggedMethods) { + private Matchable createTestClass(TestMethods testMethods, LoggedMethods loggedMethods, VMInfo vmInfo) { IRMethodBuilder irMethodBuilder = new IRMethodBuilder(testMethods, loggedMethods); - SortedSet irMethods = irMethodBuilder.build(); + SortedSet irMethods = irMethodBuilder.build(vmInfo); TestFormat.throwIfAnyFailures(); return new TestClass(irMethods); } diff --git a/test/hotspot/jtreg/compiler/lib/ir_framework/driver/irmatching/parser/VMInfo.java b/test/hotspot/jtreg/compiler/lib/ir_framework/driver/irmatching/parser/VMInfo.java new file mode 100644 index 0000000000000..d76dea902c2b7 --- /dev/null +++ b/test/hotspot/jtreg/compiler/lib/ir_framework/driver/irmatching/parser/VMInfo.java @@ -0,0 +1,107 @@ +/* + * Copyright (c) 2023, Oracle and/or its affiliates. All rights reserved. + * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. + * + * This code is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 only, as + * published by the Free Software Foundation. + * + * This code is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License + * version 2 for more details (a copy is included in the LICENSE file that + * accompanied this code). + * + * You should have received a copy of the GNU General Public License version + * 2 along with this work; if not, write to the Free Software Foundation, + * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA. + * + * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA + * or visit www.oracle.com if you need additional information or have any + * questions. + */ + +package compiler.lib.ir_framework.driver.irmatching.parser; + +import compiler.lib.ir_framework.TestFramework; +import compiler.lib.ir_framework.shared.TestFrameworkException; + +import java.util.Map; +import java.util.regex.Matcher; +import java.util.regex.Pattern; + +/** + * This class stores the key value mapping from the VMInfo. + * + * @see IREncodingParser + */ +public class VMInfo { + /** + * Stores the key-value mapping. + */ + private final Map keyValueMap; + + private static final Pattern CPU_SKYLAKE_PATTERN = + Pattern.compile("family 6 model 85 stepping (\\d) "); + + public VMInfo(Map map) { + this.keyValueMap = map; + + TestFramework.check(isKey("cpuFeatures"), "VMInfo does not contain cpuFeatures"); + TestFramework.check(isKey("MaxVectorSize"), "VMInfo does not contain MaxVectorSize"); + TestFramework.check(isKey("MaxVectorSizeIsDefault"), "VMInfo does not contain MaxVectorSizeIsDefault"); + TestFramework.check(isKey("LoopMaxUnroll"), "VMInfo does not contain LoopMaxUnroll"); + TestFramework.check(isKey("UseAVX"), "VMInfo does not contain UseAVX"); + TestFramework.check(isKey("UseAVXIsDefault"), "VMInfo does not contain UseAVXIsDefault"); + } + + public String getStringValue(String key) { + TestFramework.check(isKey(key), "VMInfo does not contain \"" + key + "\""); + return keyValueMap.get(key); + } + + public long getLongValue(String key) { + try { + return Long.parseLong(getStringValue(key)); + } catch (NumberFormatException e) { + throw new TestFrameworkException("VMInfo value for \"" + key + "\" is not a long, got \"" + getStringValue(key) + "\""); + } + } + + public boolean hasCPUFeature(String feature) { + String features = getStringValue("cpuFeatures") + ","; + return features.contains(" " + feature + ","); + } + + public boolean isCascadeLake() { + Matcher matcher = CPU_SKYLAKE_PATTERN.matcher(getStringValue("cpuFeatures")); + if (!matcher.find()) { + return false; // skylake pattern not found + } + String stepping = matcher.group(1).trim(); + return Long.parseLong(stepping) >= 5; // this makes it Cascade Lake + } + + public boolean isDefaultCascadeLake() { + // See VM_Version::is_default_intel_cascade_lake + return isCascadeLake() && + getLongValue("MaxVectorSizeIsDefault") == 1 && + getLongValue("UseAVXIsDefault") == 1 && + getLongValue("UseAVX") > 2; + } + + /** + * Some platforms do not behave as expected, and one cannot trust that the vectors + * make use of the full MaxVectorSize. For Cascade Lake, we only use 32 bytes for + * SuperWord by default even though MaxVectorSize is 64. But the VectorAPI still + * uses 64 bytes. Thus MaxVectorSize is not a reliable indicator for the expected + * maximal vector size on that platform. + */ + public boolean canTrustVectorSize() { + return !isDefaultCascadeLake(); + } + + public boolean isKey(String key) { + return keyValueMap.containsKey(key); + } +} diff --git a/test/hotspot/jtreg/compiler/lib/ir_framework/driver/irmatching/parser/VMInfoParser.java b/test/hotspot/jtreg/compiler/lib/ir_framework/driver/irmatching/parser/VMInfoParser.java new file mode 100644 index 0000000000000..a8e6782ab126c --- /dev/null +++ b/test/hotspot/jtreg/compiler/lib/ir_framework/driver/irmatching/parser/VMInfoParser.java @@ -0,0 +1,77 @@ +/* + * Copyright (c) 2023, Oracle and/or its affiliates. All rights reserved. + * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. + * + * This code is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 only, as + * published by the Free Software Foundation. + * + * This code is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License + * version 2 for more details (a copy is included in the LICENSE file that + * accompanied this code). + * + * You should have received a copy of the GNU General Public License version + * 2 along with this work; if not, write to the Free Software Foundation, + * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA. + * + * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA + * or visit www.oracle.com if you need additional information or have any + * questions. + */ + +package compiler.lib.ir_framework.driver.irmatching.parser; + +import compiler.lib.ir_framework.TestFramework; +import compiler.lib.ir_framework.shared.TestFrameworkException; +import compiler.lib.ir_framework.test.VMInfoPrinter; + +import java.util.HashMap; +import java.util.Map; +import java.util.regex.Matcher; +import java.util.regex.Pattern; + +/** + * Class to parse the VMInfo emitted by the test VM and creating {@link VMInfo} objects for each entry. + * + * @see VMInfo + */ +public class VMInfoParser { + + private static final Pattern VM_INFO_PATTERN = + Pattern.compile("(?<=" + VMInfoPrinter.START_VM_INFO + "\r?\n).*\\R([\\s\\S]*)(?=" + VMInfoPrinter.END_VM_INFO + ")"); + + /** + * Extract VMInfo from the irEncoding. + */ + public static VMInfo parseVMInfo(String irEncoding) { + Map map = new HashMap<>(); + String[] lines = getVMInfoLines(irEncoding); + for (String s : lines) { + String line = s.trim(); + String[] splitLine = line.split(":", 2); + if (splitLine.length != 2) { + throw new TestFrameworkException("Invalid VMInfo key:value encoding. Found: " + splitLine[0]); + } + String key = splitLine[0]; + String value = splitLine[1]; + map.put(key, value); + } + return new VMInfo(map); + } + + /** + * Extract the VMInfo from the irEncoding string, strip away the header and return the individual key-value lines. + */ + private static String[] getVMInfoLines(String irEncoding) { + Matcher matcher = VM_INFO_PATTERN.matcher(irEncoding); + TestFramework.check(matcher.find(), "Did not find VMInfo in:" + System.lineSeparator() + irEncoding); + String lines = matcher.group(1).trim(); + if (lines.isEmpty()) { + // Nothing to IR match. + return new String[0]; + } + return lines.split("\\R"); + } +} diff --git a/test/hotspot/jtreg/compiler/lib/ir_framework/shared/Comparison.java b/test/hotspot/jtreg/compiler/lib/ir_framework/shared/Comparison.java index d9e124a2efd44..fc553212e4d6f 100644 --- a/test/hotspot/jtreg/compiler/lib/ir_framework/shared/Comparison.java +++ b/test/hotspot/jtreg/compiler/lib/ir_framework/shared/Comparison.java @@ -38,6 +38,12 @@ public class Comparison> { private final BiPredicate comparisonPredicate; private final String comparator; + public enum Bound { + LOWER, + UPPER, + EQUAL, + } + public Comparison(T givenValue, String comparator, BiPredicate comparisonPredicate) { this.givenValue = givenValue; this.comparator = comparator; diff --git a/test/hotspot/jtreg/compiler/lib/ir_framework/test/TestVM.java b/test/hotspot/jtreg/compiler/lib/ir_framework/test/TestVM.java index 697f97ea1bcdc..be65bd6e2072d 100644 --- a/test/hotspot/jtreg/compiler/lib/ir_framework/test/TestVM.java +++ b/test/hotspot/jtreg/compiler/lib/ir_framework/test/TestVM.java @@ -266,6 +266,7 @@ private void setupTests() { addBaseTests(); if (PRINT_VALID_IR_RULES) { irMatchRulePrinter.emit(); + VMInfoPrinter.emit(); } TestFormat.throwIfAnyFailures(); declaredTests.clear(); diff --git a/test/hotspot/jtreg/compiler/lib/ir_framework/test/VMInfoPrinter.java b/test/hotspot/jtreg/compiler/lib/ir_framework/test/VMInfoPrinter.java new file mode 100644 index 0000000000000..14636da4cbe20 --- /dev/null +++ b/test/hotspot/jtreg/compiler/lib/ir_framework/test/VMInfoPrinter.java @@ -0,0 +1,70 @@ +/* + * Copyright (c) 2023, Oracle and/or its affiliates. All rights reserved. + * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. + * + * This code is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 only, as + * published by the Free Software Foundation. + * + * This code is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License + * version 2 for more details (a copy is included in the LICENSE file that + * accompanied this code). + * + * You should have received a copy of the GNU General Public License version + * 2 along with this work; if not, write to the Free Software Foundation, + * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA. + * + * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA + * or visit www.oracle.com if you need additional information or have any + * questions. + */ + +package compiler.lib.ir_framework.test; + +import compiler.lib.ir_framework.shared.TestFrameworkSocket; +import jdk.test.whitebox.WhiteBox; + +/** + * Prints some test VM info to the socket. + */ +public class VMInfoPrinter { + public static final String START_VM_INFO = "##### IRMatchingVMInfo - used by TestFramework #####"; + public static final String END_VM_INFO = "----- END VMInfo -----"; + + private static final WhiteBox WHITE_BOX = WhiteBox.getWhiteBox(); + + public static void emit() { + StringBuilder vmInfo = new StringBuilder(); + vmInfo.append(START_VM_INFO).append(System.lineSeparator()); + vmInfo.append(":").append(System.lineSeparator()); + + // CPU feature independent info + String cpuFeatures = WHITE_BOX.getCPUFeatures(); + vmInfo.append("cpuFeatures:").append(cpuFeatures).append(System.lineSeparator()); + long maxVectorSize = WHITE_BOX.getIntxVMFlag("MaxVectorSize"); + vmInfo.append("MaxVectorSize:").append(maxVectorSize).append(System.lineSeparator()); + boolean maxVectorSizeIsDefault = WHITE_BOX.isDefaultVMFlag("MaxVectorSize"); + vmInfo.append("MaxVectorSizeIsDefault:") + .append(maxVectorSizeIsDefault ? 1 : 0) + .append(System.lineSeparator()); + long loopMaxUnroll = WHITE_BOX.getIntxVMFlag("LoopMaxUnroll"); + vmInfo.append("LoopMaxUnroll:").append(loopMaxUnroll).append(System.lineSeparator()); + + // CPU feature dependent info + long useAVX = 0; + boolean useAVXIsDefault = true; + if (cpuFeatures.contains(" sse, ")) { + useAVX = WHITE_BOX.getIntVMFlag("UseAVX"); + useAVXIsDefault = WHITE_BOX.isDefaultVMFlag("UseAVX"); + } + vmInfo.append("UseAVX:").append(useAVX).append(System.lineSeparator()); + vmInfo.append("UseAVXIsDefault:") + .append(useAVXIsDefault ? 1 : 0) + .append(System.lineSeparator()); + + vmInfo.append(END_VM_INFO); + TestFrameworkSocket.write(vmInfo.toString(), "VMInfo"); + } +} diff --git a/test/hotspot/jtreg/compiler/loopopts/superword/SumRedAbsNeg_Double.java b/test/hotspot/jtreg/compiler/loopopts/superword/SumRedAbsNeg_Double.java index 32c1053e6dc49..0122f1c34cd61 100644 --- a/test/hotspot/jtreg/compiler/loopopts/superword/SumRedAbsNeg_Double.java +++ b/test/hotspot/jtreg/compiler/loopopts/superword/SumRedAbsNeg_Double.java @@ -92,7 +92,7 @@ public static void sumReductionInit( (with or without store) in SuperWord::profitable. */ @Test @IR(applyIf = {"SuperWordReductions", "false"}, - failOn = {IRNode.ADD_REDUCTION_VD, IRNode.ABS_V, IRNode.NEG_V}) + failOn = {IRNode.ADD_REDUCTION_VD, IRNode.ABS_VD, IRNode.NEG_VD}) public static double sumReductionImplement( double[] a, double[] b, diff --git a/test/hotspot/jtreg/compiler/loopopts/superword/SumRedAbsNeg_Float.java b/test/hotspot/jtreg/compiler/loopopts/superword/SumRedAbsNeg_Float.java index f3eb427e0ea37..f886daf903ff8 100644 --- a/test/hotspot/jtreg/compiler/loopopts/superword/SumRedAbsNeg_Float.java +++ b/test/hotspot/jtreg/compiler/loopopts/superword/SumRedAbsNeg_Float.java @@ -90,10 +90,12 @@ public static void sumReductionInit( @Test @IR(applyIf = {"SuperWordReductions", "false"}, - failOn = {IRNode.ADD_REDUCTION_VF, IRNode.ABS_V, IRNode.NEG_V}) + failOn = {IRNode.ADD_REDUCTION_VF, IRNode.ABS_VF, IRNode.NEG_VF}) @IR(applyIfCPUFeature = {"sse2", "true"}, applyIfAnd = {"SuperWordReductions", "true", "LoopMaxUnroll", ">= 8"}, - counts = {IRNode.ADD_REDUCTION_VF, ">= 1", IRNode.ABS_V, ">= 1", IRNode.NEG_V, ">= 1"}) + counts = {IRNode.ADD_REDUCTION_VF, ">= 1", + IRNode.ABS_VF, IRNode.VECTOR_SIZE + "min(LoopMaxUnroll, max_float)", ">= 1", + IRNode.NEG_VF, IRNode.VECTOR_SIZE + "min(LoopMaxUnroll, max_float)", ">= 1"}) public static float sumReductionImplement( float[] a, float[] b, diff --git a/test/hotspot/jtreg/compiler/loopopts/superword/SumRedSqrt_Double.java b/test/hotspot/jtreg/compiler/loopopts/superword/SumRedSqrt_Double.java index 76453b21e846a..d0fd27d25b4ad 100644 --- a/test/hotspot/jtreg/compiler/loopopts/superword/SumRedSqrt_Double.java +++ b/test/hotspot/jtreg/compiler/loopopts/superword/SumRedSqrt_Double.java @@ -87,10 +87,10 @@ public static void sumReductionInit( Require avx for SQRT_VD. */ @Test @IR(applyIf = {"SuperWordReductions", "false"}, - failOn = {IRNode.ADD_REDUCTION_VD, IRNode.SQRT_V}) + failOn = {IRNode.ADD_REDUCTION_VD, IRNode.SQRT_VD}) @IR(applyIfCPUFeature = {"avx", "true"}, applyIfAnd = {"SuperWordReductions", "true", "LoopMaxUnroll", ">= 8"}, - counts = {IRNode.ADD_REDUCTION_VD, ">= 1", IRNode.SQRT_V, ">= 1"}) + counts = {IRNode.ADD_REDUCTION_VD, ">= 1", IRNode.SQRT_VD, ">= 1"}) public static double sumReductionWithStoreImplement( double[] a, double[] b, diff --git a/test/hotspot/jtreg/compiler/loopopts/superword/TestCyclicDependency.java b/test/hotspot/jtreg/compiler/loopopts/superword/TestCyclicDependency.java index 803c7e9841d9d..94e47f3f7479a 100644 --- a/test/hotspot/jtreg/compiler/loopopts/superword/TestCyclicDependency.java +++ b/test/hotspot/jtreg/compiler/loopopts/superword/TestCyclicDependency.java @@ -240,7 +240,7 @@ public void runTest9() { } @Test - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.ADD_VI, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_I, "> 0", IRNode.ADD_VI, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIfCPUFeatureOr = {"sse4.1", "true", "asimd", "true"}) static void test0(int[] dataI, float[] dataF) { for (int i = 0; i < RANGE; i++) { @@ -346,7 +346,7 @@ static void test7(int[] dataI, float[] dataF) { } @Test - @IR(counts = {IRNode.ADD_VF, "> 0"}, + @IR(counts = {IRNode.ADD_VF, IRNode.VECTOR_SIZE + "min(max_int, max_float)", "> 0"}, applyIf = {"AlignVector", "false"}, applyIfCPUFeatureOr = {"sse4.1", "true", "asimd", "true"}) // Some aarch64 machines have AlignVector == true, like ThunderX2 diff --git a/test/hotspot/jtreg/compiler/loopopts/superword/TestDependencyOffsets.java b/test/hotspot/jtreg/compiler/loopopts/superword/TestDependencyOffsets.java index 14033f9712a98..132844801a125 100644 --- a/test/hotspot/jtreg/compiler/loopopts/superword/TestDependencyOffsets.java +++ b/test/hotspot/jtreg/compiler/loopopts/superword/TestDependencyOffsets.java @@ -27,7 +27,7 @@ * and various MaxVectorSize values, and +- AlignVector. * * Note: this test is auto-generated. Please modify / generate with script: - * https://bugs.openjdk.org/browse/JDK-8308606 + * https://bugs.openjdk.org/browse/JDK-8310308 * * Types: int, long, short, char, byte, float, double * Offsets: 0, -1, 1, -2, 2, -3, 3, -4, 4, -7, 7, -8, 8, -14, 14, -16, 16, -18, 18, -20, 20, -31, 31, -32, 32, -63, 63, -64, 64, -65, 65, -128, 128, -129, 129, -192, 192 @@ -1389,19 +1389,19 @@ public static void main(String args[]) { @Test // CPU: sse4.1 to avx -> vector_width: 16 -> elements in vector: 4 - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.MUL_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_I, "> 0", IRNode.MUL_VI, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIfAnd = {"AlignVector", "false", "MaxVectorSize", ">= 8"}, applyIfCPUFeatureAnd = {"sse4.1", "true", "avx2", "false"}) // CPU: avx2 -> vector_width: 32 -> elements in vector: 8 - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.MUL_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_I, "> 0", IRNode.MUL_VI, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIfAnd = {"AlignVector", "false", "MaxVectorSize", ">= 8"}, applyIfCPUFeatureAnd = {"avx2", "true", "avx512", "false"}) // CPU: avx512 -> vector_width: 64 -> elements in vector: 16 - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.MUL_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_I, "> 0", IRNode.MUL_VI, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIfAnd = {"AlignVector", "false", "MaxVectorSize", ">= 8"}, applyIfCPUFeature = {"avx512", "true"}) // CPU: asimd -> vector_width: 32 -> elements in vector: 8 - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.MUL_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_I, "> 0", IRNode.MUL_VI, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIfAnd = {"AlignVector", "false", "MaxVectorSize", ">= 8"}, applyIfCPUFeature = {"asimd", "true"}) public static void testIntP0(int[] data) { @@ -1421,35 +1421,35 @@ public static void runIntP0() { @Test // CPU: sse4.1 to avx -> vector_width: 16 -> elements in vector: 4 - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.MUL_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_I, "> 0", IRNode.MUL_VI, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIfAnd = {"AlignVector", "false", "MaxVectorSize", ">= 8"}, applyIfCPUFeatureAnd = {"sse4.1", "true", "avx2", "false"}) // Strict alignment not possible. - @IR(failOn = {IRNode.LOAD_VECTOR, IRNode.MUL_V, IRNode.STORE_VECTOR}, + @IR(failOn = {IRNode.LOAD_VECTOR_I, IRNode.MUL_VI, IRNode.STORE_VECTOR}, applyIf = {"AlignVector", "true"}, applyIfCPUFeatureAnd = {"sse4.1", "true", "avx2", "false"}) // CPU: avx2 -> vector_width: 32 -> elements in vector: 8 - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.MUL_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_I, "> 0", IRNode.MUL_VI, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIfAnd = {"AlignVector", "false", "MaxVectorSize", ">= 8"}, applyIfCPUFeatureAnd = {"avx2", "true", "avx512", "false"}) // Strict alignment not possible. - @IR(failOn = {IRNode.LOAD_VECTOR, IRNode.MUL_V, IRNode.STORE_VECTOR}, + @IR(failOn = {IRNode.LOAD_VECTOR_I, IRNode.MUL_VI, IRNode.STORE_VECTOR}, applyIf = {"AlignVector", "true"}, applyIfCPUFeatureAnd = {"avx2", "true", "avx512", "false"}) // CPU: avx512 -> vector_width: 64 -> elements in vector: 16 - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.MUL_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_I, "> 0", IRNode.MUL_VI, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIfAnd = {"AlignVector", "false", "MaxVectorSize", ">= 8"}, applyIfCPUFeature = {"avx512", "true"}) // Strict alignment not possible. - @IR(failOn = {IRNode.LOAD_VECTOR, IRNode.MUL_V, IRNode.STORE_VECTOR}, + @IR(failOn = {IRNode.LOAD_VECTOR_I, IRNode.MUL_VI, IRNode.STORE_VECTOR}, applyIf = {"AlignVector", "true"}, applyIfCPUFeature = {"avx512", "true"}) // CPU: asimd -> vector_width: 32 -> elements in vector: 8 - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.MUL_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_I, "> 0", IRNode.MUL_VI, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIfAnd = {"AlignVector", "false", "MaxVectorSize", ">= 8"}, applyIfCPUFeature = {"asimd", "true"}) // Strict alignment not possible. - @IR(failOn = {IRNode.LOAD_VECTOR, IRNode.MUL_V, IRNode.STORE_VECTOR}, + @IR(failOn = {IRNode.LOAD_VECTOR_I, IRNode.MUL_VI, IRNode.STORE_VECTOR}, applyIf = {"AlignVector", "true"}, applyIfCPUFeature = {"asimd", "true"}) public static void testIntM1(int[] data) { @@ -1497,19 +1497,19 @@ public static void runIntP1() { @Test // CPU: sse4.1 to avx -> vector_width: 16 -> elements in vector: 4 - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.MUL_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_I, "> 0", IRNode.MUL_VI, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIfAnd = {"AlignVector", "false", "MaxVectorSize", ">= 8"}, applyIfCPUFeatureAnd = {"sse4.1", "true", "avx2", "false"}) // CPU: avx2 -> vector_width: 32 -> elements in vector: 8 - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.MUL_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_I, "> 0", IRNode.MUL_VI, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIfAnd = {"AlignVector", "false", "MaxVectorSize", ">= 8"}, applyIfCPUFeatureAnd = {"avx2", "true", "avx512", "false"}) // CPU: avx512 -> vector_width: 64 -> elements in vector: 16 - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.MUL_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_I, "> 0", IRNode.MUL_VI, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIfAnd = {"AlignVector", "false", "MaxVectorSize", ">= 8"}, applyIfCPUFeature = {"avx512", "true"}) // CPU: asimd -> vector_width: 32 -> elements in vector: 8 - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.MUL_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_I, "> 0", IRNode.MUL_VI, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIfAnd = {"AlignVector", "false", "MaxVectorSize", ">= 8"}, applyIfCPUFeature = {"asimd", "true"}) public static void testIntM2(int[] data) { @@ -1530,22 +1530,22 @@ public static void runIntM2() { @Test // CPU: sse4.1 to avx -> vector_width: 16 -> elements in vector: 4 // positive byte_offset 8 can lead to cyclic dependency - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.MUL_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_I, "> 0", IRNode.MUL_VI, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIfAnd = {"AlignVector", "false", "MaxVectorSize", ">= 8", "MaxVectorSize", "<= 8"}, applyIfCPUFeatureAnd = {"sse4.1", "true", "avx2", "false"}) // CPU: avx2 -> vector_width: 32 -> elements in vector: 8 // positive byte_offset 8 can lead to cyclic dependency - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.MUL_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_I, "> 0", IRNode.MUL_VI, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIfAnd = {"AlignVector", "false", "MaxVectorSize", ">= 8", "MaxVectorSize", "<= 8"}, applyIfCPUFeatureAnd = {"avx2", "true", "avx512", "false"}) // CPU: avx512 -> vector_width: 64 -> elements in vector: 16 // positive byte_offset 8 can lead to cyclic dependency - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.MUL_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_I, "> 0", IRNode.MUL_VI, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIfAnd = {"AlignVector", "false", "MaxVectorSize", ">= 8", "MaxVectorSize", "<= 8"}, applyIfCPUFeature = {"avx512", "true"}) // CPU: asimd -> vector_width: 32 -> elements in vector: 8 // positive byte_offset 8 can lead to cyclic dependency - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.MUL_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_I, "> 0", IRNode.MUL_VI, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIfAnd = {"AlignVector", "false", "MaxVectorSize", ">= 8", "MaxVectorSize", "<= 8"}, applyIfCPUFeature = {"asimd", "true"}) public static void testIntP2(int[] data) { @@ -1565,35 +1565,35 @@ public static void runIntP2() { @Test // CPU: sse4.1 to avx -> vector_width: 16 -> elements in vector: 4 - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.MUL_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_I, "> 0", IRNode.MUL_VI, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIfAnd = {"AlignVector", "false", "MaxVectorSize", ">= 8"}, applyIfCPUFeatureAnd = {"sse4.1", "true", "avx2", "false"}) // Strict alignment not possible. - @IR(failOn = {IRNode.LOAD_VECTOR, IRNode.MUL_V, IRNode.STORE_VECTOR}, + @IR(failOn = {IRNode.LOAD_VECTOR_I, IRNode.MUL_VI, IRNode.STORE_VECTOR}, applyIf = {"AlignVector", "true"}, applyIfCPUFeatureAnd = {"sse4.1", "true", "avx2", "false"}) // CPU: avx2 -> vector_width: 32 -> elements in vector: 8 - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.MUL_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_I, "> 0", IRNode.MUL_VI, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIfAnd = {"AlignVector", "false", "MaxVectorSize", ">= 8"}, applyIfCPUFeatureAnd = {"avx2", "true", "avx512", "false"}) // Strict alignment not possible. - @IR(failOn = {IRNode.LOAD_VECTOR, IRNode.MUL_V, IRNode.STORE_VECTOR}, + @IR(failOn = {IRNode.LOAD_VECTOR_I, IRNode.MUL_VI, IRNode.STORE_VECTOR}, applyIf = {"AlignVector", "true"}, applyIfCPUFeatureAnd = {"avx2", "true", "avx512", "false"}) // CPU: avx512 -> vector_width: 64 -> elements in vector: 16 - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.MUL_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_I, "> 0", IRNode.MUL_VI, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIfAnd = {"AlignVector", "false", "MaxVectorSize", ">= 8"}, applyIfCPUFeature = {"avx512", "true"}) // Strict alignment not possible. - @IR(failOn = {IRNode.LOAD_VECTOR, IRNode.MUL_V, IRNode.STORE_VECTOR}, + @IR(failOn = {IRNode.LOAD_VECTOR_I, IRNode.MUL_VI, IRNode.STORE_VECTOR}, applyIf = {"AlignVector", "true"}, applyIfCPUFeature = {"avx512", "true"}) // CPU: asimd -> vector_width: 32 -> elements in vector: 8 - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.MUL_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_I, "> 0", IRNode.MUL_VI, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIfAnd = {"AlignVector", "false", "MaxVectorSize", ">= 8"}, applyIfCPUFeature = {"asimd", "true"}) // Strict alignment not possible. - @IR(failOn = {IRNode.LOAD_VECTOR, IRNode.MUL_V, IRNode.STORE_VECTOR}, + @IR(failOn = {IRNode.LOAD_VECTOR_I, IRNode.MUL_VI, IRNode.STORE_VECTOR}, applyIf = {"AlignVector", "true"}, applyIfCPUFeature = {"asimd", "true"}) public static void testIntM3(int[] data) { @@ -1614,22 +1614,22 @@ public static void runIntM3() { @Test // CPU: sse4.1 to avx -> vector_width: 16 -> elements in vector: 4 // positive byte_offset 12 can lead to cyclic dependency - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.MUL_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_I, "> 0", IRNode.MUL_VI, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIfAnd = {"AlignVector", "false", "MaxVectorSize", ">= 8", "MaxVectorSize", "<= 12"}, applyIfCPUFeatureAnd = {"sse4.1", "true", "avx2", "false"}) // CPU: avx2 -> vector_width: 32 -> elements in vector: 8 // positive byte_offset 12 can lead to cyclic dependency - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.MUL_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_I, "> 0", IRNode.MUL_VI, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIfAnd = {"AlignVector", "false", "MaxVectorSize", ">= 8", "MaxVectorSize", "<= 12"}, applyIfCPUFeatureAnd = {"avx2", "true", "avx512", "false"}) // CPU: avx512 -> vector_width: 64 -> elements in vector: 16 // positive byte_offset 12 can lead to cyclic dependency - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.MUL_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_I, "> 0", IRNode.MUL_VI, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIfAnd = {"AlignVector", "false", "MaxVectorSize", ">= 8", "MaxVectorSize", "<= 12"}, applyIfCPUFeature = {"avx512", "true"}) // CPU: asimd -> vector_width: 32 -> elements in vector: 8 // positive byte_offset 12 can lead to cyclic dependency - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.MUL_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_I, "> 0", IRNode.MUL_VI, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIfAnd = {"AlignVector", "false", "MaxVectorSize", ">= 8", "MaxVectorSize", "<= 12"}, applyIfCPUFeature = {"asimd", "true"}) public static void testIntP3(int[] data) { @@ -1649,19 +1649,19 @@ public static void runIntP3() { @Test // CPU: sse4.1 to avx -> vector_width: 16 -> elements in vector: 4 - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.MUL_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_I, "> 0", IRNode.MUL_VI, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIfAnd = {"AlignVector", "false", "MaxVectorSize", ">= 8"}, applyIfCPUFeatureAnd = {"sse4.1", "true", "avx2", "false"}) // CPU: avx2 -> vector_width: 32 -> elements in vector: 8 - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.MUL_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_I, "> 0", IRNode.MUL_VI, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIfAnd = {"AlignVector", "false", "MaxVectorSize", ">= 8"}, applyIfCPUFeatureAnd = {"avx2", "true", "avx512", "false"}) // CPU: avx512 -> vector_width: 64 -> elements in vector: 16 - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.MUL_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_I, "> 0", IRNode.MUL_VI, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIfAnd = {"AlignVector", "false", "MaxVectorSize", ">= 8"}, applyIfCPUFeature = {"avx512", "true"}) // CPU: asimd -> vector_width: 32 -> elements in vector: 8 - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.MUL_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_I, "> 0", IRNode.MUL_VI, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIfAnd = {"AlignVector", "false", "MaxVectorSize", ">= 8"}, applyIfCPUFeature = {"asimd", "true"}) public static void testIntM4(int[] data) { @@ -1681,26 +1681,26 @@ public static void runIntM4() { @Test // CPU: sse4.1 to avx -> vector_width: 16 -> elements in vector: 4 - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.MUL_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_I, "> 0", IRNode.MUL_VI, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIfAnd = {"AlignVector", "false", "MaxVectorSize", ">= 8"}, applyIfCPUFeatureAnd = {"sse4.1", "true", "avx2", "false"}) // Vectorize when strict alignment guaranteed. - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.MUL_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_I, "> 0", IRNode.MUL_VI, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIfAnd = {"AlignVector", "true", "MaxVectorSize", ">= 8"}, applyIfCPUFeatureAnd = {"sse4.1", "true", "avx2", "false"}) // CPU: avx2 -> vector_width: 32 -> elements in vector: 8 // positive byte_offset 16 can lead to cyclic dependency - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.MUL_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_I, "> 0", IRNode.MUL_VI, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIfAnd = {"AlignVector", "false", "MaxVectorSize", ">= 8", "MaxVectorSize", "<= 16"}, applyIfCPUFeatureAnd = {"avx2", "true", "avx512", "false"}) // CPU: avx512 -> vector_width: 64 -> elements in vector: 16 // positive byte_offset 16 can lead to cyclic dependency - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.MUL_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_I, "> 0", IRNode.MUL_VI, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIfAnd = {"AlignVector", "false", "MaxVectorSize", ">= 8", "MaxVectorSize", "<= 16"}, applyIfCPUFeature = {"avx512", "true"}) // CPU: asimd -> vector_width: 32 -> elements in vector: 8 // positive byte_offset 16 can lead to cyclic dependency - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.MUL_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_I, "> 0", IRNode.MUL_VI, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIfAnd = {"AlignVector", "false", "MaxVectorSize", ">= 8", "MaxVectorSize", "<= 16"}, applyIfCPUFeature = {"asimd", "true"}) public static void testIntP4(int[] data) { @@ -1720,35 +1720,35 @@ public static void runIntP4() { @Test // CPU: sse4.1 to avx -> vector_width: 16 -> elements in vector: 4 - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.MUL_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_I, "> 0", IRNode.MUL_VI, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIfAnd = {"AlignVector", "false", "MaxVectorSize", ">= 8"}, applyIfCPUFeatureAnd = {"sse4.1", "true", "avx2", "false"}) // Strict alignment not possible. - @IR(failOn = {IRNode.LOAD_VECTOR, IRNode.MUL_V, IRNode.STORE_VECTOR}, + @IR(failOn = {IRNode.LOAD_VECTOR_I, IRNode.MUL_VI, IRNode.STORE_VECTOR}, applyIf = {"AlignVector", "true"}, applyIfCPUFeatureAnd = {"sse4.1", "true", "avx2", "false"}) // CPU: avx2 -> vector_width: 32 -> elements in vector: 8 - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.MUL_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_I, "> 0", IRNode.MUL_VI, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIfAnd = {"AlignVector", "false", "MaxVectorSize", ">= 8"}, applyIfCPUFeatureAnd = {"avx2", "true", "avx512", "false"}) // Strict alignment not possible. - @IR(failOn = {IRNode.LOAD_VECTOR, IRNode.MUL_V, IRNode.STORE_VECTOR}, + @IR(failOn = {IRNode.LOAD_VECTOR_I, IRNode.MUL_VI, IRNode.STORE_VECTOR}, applyIf = {"AlignVector", "true"}, applyIfCPUFeatureAnd = {"avx2", "true", "avx512", "false"}) // CPU: avx512 -> vector_width: 64 -> elements in vector: 16 - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.MUL_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_I, "> 0", IRNode.MUL_VI, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIfAnd = {"AlignVector", "false", "MaxVectorSize", ">= 8"}, applyIfCPUFeature = {"avx512", "true"}) // Strict alignment not possible. - @IR(failOn = {IRNode.LOAD_VECTOR, IRNode.MUL_V, IRNode.STORE_VECTOR}, + @IR(failOn = {IRNode.LOAD_VECTOR_I, IRNode.MUL_VI, IRNode.STORE_VECTOR}, applyIf = {"AlignVector", "true"}, applyIfCPUFeature = {"avx512", "true"}) // CPU: asimd -> vector_width: 32 -> elements in vector: 8 - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.MUL_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_I, "> 0", IRNode.MUL_VI, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIfAnd = {"AlignVector", "false", "MaxVectorSize", ">= 8"}, applyIfCPUFeature = {"asimd", "true"}) // Strict alignment not possible. - @IR(failOn = {IRNode.LOAD_VECTOR, IRNode.MUL_V, IRNode.STORE_VECTOR}, + @IR(failOn = {IRNode.LOAD_VECTOR_I, IRNode.MUL_VI, IRNode.STORE_VECTOR}, applyIf = {"AlignVector", "true"}, applyIfCPUFeature = {"asimd", "true"}) public static void testIntM7(int[] data) { @@ -1768,22 +1768,22 @@ public static void runIntM7() { @Test // CPU: sse4.1 to avx -> vector_width: 16 -> elements in vector: 4 - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.MUL_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_I, "> 0", IRNode.MUL_VI, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIfAnd = {"AlignVector", "false", "MaxVectorSize", ">= 8"}, applyIfCPUFeatureAnd = {"sse4.1", "true", "avx2", "false"}) // CPU: avx2 -> vector_width: 32 -> elements in vector: 8 // positive byte_offset 28 can lead to cyclic dependency - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.MUL_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_I, "> 0", IRNode.MUL_VI, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIfAnd = {"AlignVector", "false", "MaxVectorSize", ">= 8", "MaxVectorSize", "<= 28"}, applyIfCPUFeatureAnd = {"avx2", "true", "avx512", "false"}) // CPU: avx512 -> vector_width: 64 -> elements in vector: 16 // positive byte_offset 28 can lead to cyclic dependency - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.MUL_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_I, "> 0", IRNode.MUL_VI, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIfAnd = {"AlignVector", "false", "MaxVectorSize", ">= 8", "MaxVectorSize", "<= 28"}, applyIfCPUFeature = {"avx512", "true"}) // CPU: asimd -> vector_width: 32 -> elements in vector: 8 // positive byte_offset 28 can lead to cyclic dependency - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.MUL_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_I, "> 0", IRNode.MUL_VI, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIfAnd = {"AlignVector", "false", "MaxVectorSize", ">= 8", "MaxVectorSize", "<= 28"}, applyIfCPUFeature = {"asimd", "true"}) public static void testIntP7(int[] data) { @@ -1803,19 +1803,19 @@ public static void runIntP7() { @Test // CPU: sse4.1 to avx -> vector_width: 16 -> elements in vector: 4 - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.MUL_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_I, "> 0", IRNode.MUL_VI, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIfAnd = {"AlignVector", "false", "MaxVectorSize", ">= 8"}, applyIfCPUFeatureAnd = {"sse4.1", "true", "avx2", "false"}) // CPU: avx2 -> vector_width: 32 -> elements in vector: 8 - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.MUL_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_I, "> 0", IRNode.MUL_VI, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIfAnd = {"AlignVector", "false", "MaxVectorSize", ">= 8"}, applyIfCPUFeatureAnd = {"avx2", "true", "avx512", "false"}) // CPU: avx512 -> vector_width: 64 -> elements in vector: 16 - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.MUL_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_I, "> 0", IRNode.MUL_VI, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIfAnd = {"AlignVector", "false", "MaxVectorSize", ">= 8"}, applyIfCPUFeature = {"avx512", "true"}) // CPU: asimd -> vector_width: 32 -> elements in vector: 8 - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.MUL_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_I, "> 0", IRNode.MUL_VI, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIfAnd = {"AlignVector", "false", "MaxVectorSize", ">= 8"}, applyIfCPUFeature = {"asimd", "true"}) public static void testIntM8(int[] data) { @@ -1835,32 +1835,32 @@ public static void runIntM8() { @Test // CPU: sse4.1 to avx -> vector_width: 16 -> elements in vector: 4 - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.MUL_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_I, "> 0", IRNode.MUL_VI, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIfAnd = {"AlignVector", "false", "MaxVectorSize", ">= 8"}, applyIfCPUFeatureAnd = {"sse4.1", "true", "avx2", "false"}) // Vectorize when strict alignment guaranteed. - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.MUL_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_I, "> 0", IRNode.MUL_VI, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIfAnd = {"AlignVector", "true", "MaxVectorSize", ">= 8"}, applyIfCPUFeatureAnd = {"sse4.1", "true", "avx2", "false"}) // CPU: avx2 -> vector_width: 32 -> elements in vector: 8 - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.MUL_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_I, "> 0", IRNode.MUL_VI, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIfAnd = {"AlignVector", "false", "MaxVectorSize", ">= 8"}, applyIfCPUFeatureAnd = {"avx2", "true", "avx512", "false"}) // Vectorize when strict alignment guaranteed. - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.MUL_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_I, "> 0", IRNode.MUL_VI, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIfAnd = {"AlignVector", "true", "MaxVectorSize", ">= 8"}, applyIfCPUFeatureAnd = {"avx2", "true", "avx512", "false"}) // CPU: avx512 -> vector_width: 64 -> elements in vector: 16 // positive byte_offset 32 can lead to cyclic dependency - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.MUL_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_I, "> 0", IRNode.MUL_VI, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIfAnd = {"AlignVector", "false", "MaxVectorSize", ">= 8", "MaxVectorSize", "<= 32"}, applyIfCPUFeature = {"avx512", "true"}) // CPU: asimd -> vector_width: 32 -> elements in vector: 8 - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.MUL_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_I, "> 0", IRNode.MUL_VI, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIfAnd = {"AlignVector", "false", "MaxVectorSize", ">= 8"}, applyIfCPUFeature = {"asimd", "true"}) // Vectorize when strict alignment guaranteed. - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.MUL_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_I, "> 0", IRNode.MUL_VI, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIfAnd = {"AlignVector", "true", "MaxVectorSize", ">= 8"}, applyIfCPUFeature = {"asimd", "true"}) public static void testIntP8(int[] data) { @@ -1880,19 +1880,19 @@ public static void runIntP8() { @Test // CPU: sse4.1 to avx -> vector_width: 16 -> elements in vector: 4 - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.MUL_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_I, "> 0", IRNode.MUL_VI, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIfAnd = {"AlignVector", "false", "MaxVectorSize", ">= 8"}, applyIfCPUFeatureAnd = {"sse4.1", "true", "avx2", "false"}) // CPU: avx2 -> vector_width: 32 -> elements in vector: 8 - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.MUL_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_I, "> 0", IRNode.MUL_VI, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIfAnd = {"AlignVector", "false", "MaxVectorSize", ">= 8"}, applyIfCPUFeatureAnd = {"avx2", "true", "avx512", "false"}) // CPU: avx512 -> vector_width: 64 -> elements in vector: 16 - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.MUL_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_I, "> 0", IRNode.MUL_VI, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIfAnd = {"AlignVector", "false", "MaxVectorSize", ">= 8"}, applyIfCPUFeature = {"avx512", "true"}) // CPU: asimd -> vector_width: 32 -> elements in vector: 8 - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.MUL_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_I, "> 0", IRNode.MUL_VI, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIfAnd = {"AlignVector", "false", "MaxVectorSize", ">= 8"}, applyIfCPUFeature = {"asimd", "true"}) public static void testIntM14(int[] data) { @@ -1912,20 +1912,20 @@ public static void runIntM14() { @Test // CPU: sse4.1 to avx -> vector_width: 16 -> elements in vector: 4 - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.MUL_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_I, "> 0", IRNode.MUL_VI, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIfAnd = {"AlignVector", "false", "MaxVectorSize", ">= 8"}, applyIfCPUFeatureAnd = {"sse4.1", "true", "avx2", "false"}) // CPU: avx2 -> vector_width: 32 -> elements in vector: 8 - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.MUL_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_I, "> 0", IRNode.MUL_VI, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIfAnd = {"AlignVector", "false", "MaxVectorSize", ">= 8"}, applyIfCPUFeatureAnd = {"avx2", "true", "avx512", "false"}) // CPU: avx512 -> vector_width: 64 -> elements in vector: 16 // positive byte_offset 56 can lead to cyclic dependency - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.MUL_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_I, "> 0", IRNode.MUL_VI, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIfAnd = {"AlignVector", "false", "MaxVectorSize", ">= 8", "MaxVectorSize", "<= 56"}, applyIfCPUFeature = {"avx512", "true"}) // CPU: asimd -> vector_width: 32 -> elements in vector: 8 - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.MUL_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_I, "> 0", IRNode.MUL_VI, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIfAnd = {"AlignVector", "false", "MaxVectorSize", ">= 8"}, applyIfCPUFeature = {"asimd", "true"}) public static void testIntP14(int[] data) { @@ -1945,19 +1945,19 @@ public static void runIntP14() { @Test // CPU: sse4.1 to avx -> vector_width: 16 -> elements in vector: 4 - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.MUL_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_I, "> 0", IRNode.MUL_VI, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIfAnd = {"AlignVector", "false", "MaxVectorSize", ">= 8"}, applyIfCPUFeatureAnd = {"sse4.1", "true", "avx2", "false"}) // CPU: avx2 -> vector_width: 32 -> elements in vector: 8 - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.MUL_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_I, "> 0", IRNode.MUL_VI, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIfAnd = {"AlignVector", "false", "MaxVectorSize", ">= 8"}, applyIfCPUFeatureAnd = {"avx2", "true", "avx512", "false"}) // CPU: avx512 -> vector_width: 64 -> elements in vector: 16 - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.MUL_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_I, "> 0", IRNode.MUL_VI, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIfAnd = {"AlignVector", "false", "MaxVectorSize", ">= 8"}, applyIfCPUFeature = {"avx512", "true"}) // CPU: asimd -> vector_width: 32 -> elements in vector: 8 - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.MUL_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_I, "> 0", IRNode.MUL_VI, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIfAnd = {"AlignVector", "false", "MaxVectorSize", ">= 8"}, applyIfCPUFeature = {"asimd", "true"}) public static void testIntM16(int[] data) { @@ -1977,35 +1977,35 @@ public static void runIntM16() { @Test // CPU: sse4.1 to avx -> vector_width: 16 -> elements in vector: 4 - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.MUL_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_I, "> 0", IRNode.MUL_VI, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIfAnd = {"AlignVector", "false", "MaxVectorSize", ">= 8"}, applyIfCPUFeatureAnd = {"sse4.1", "true", "avx2", "false"}) // Vectorize when strict alignment guaranteed. - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.MUL_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_I, "> 0", IRNode.MUL_VI, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIfAnd = {"AlignVector", "true", "MaxVectorSize", ">= 8"}, applyIfCPUFeatureAnd = {"sse4.1", "true", "avx2", "false"}) // CPU: avx2 -> vector_width: 32 -> elements in vector: 8 - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.MUL_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_I, "> 0", IRNode.MUL_VI, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIfAnd = {"AlignVector", "false", "MaxVectorSize", ">= 8"}, applyIfCPUFeatureAnd = {"avx2", "true", "avx512", "false"}) // Vectorize when strict alignment guaranteed. - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.MUL_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_I, "> 0", IRNode.MUL_VI, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIfAnd = {"AlignVector", "true", "MaxVectorSize", ">= 8"}, applyIfCPUFeatureAnd = {"avx2", "true", "avx512", "false"}) // CPU: avx512 -> vector_width: 64 -> elements in vector: 16 - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.MUL_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_I, "> 0", IRNode.MUL_VI, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIfAnd = {"AlignVector", "false", "MaxVectorSize", ">= 8"}, applyIfCPUFeature = {"avx512", "true"}) // Vectorize when strict alignment guaranteed. - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.MUL_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_I, "> 0", IRNode.MUL_VI, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIfAnd = {"AlignVector", "true", "MaxVectorSize", ">= 8"}, applyIfCPUFeature = {"avx512", "true"}) // CPU: asimd -> vector_width: 32 -> elements in vector: 8 - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.MUL_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_I, "> 0", IRNode.MUL_VI, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIfAnd = {"AlignVector", "false", "MaxVectorSize", ">= 8"}, applyIfCPUFeature = {"asimd", "true"}) // Vectorize when strict alignment guaranteed. - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.MUL_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_I, "> 0", IRNode.MUL_VI, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIfAnd = {"AlignVector", "true", "MaxVectorSize", ">= 8"}, applyIfCPUFeature = {"asimd", "true"}) public static void testIntP16(int[] data) { @@ -2025,19 +2025,19 @@ public static void runIntP16() { @Test // CPU: sse4.1 to avx -> vector_width: 16 -> elements in vector: 4 - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.MUL_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_I, "> 0", IRNode.MUL_VI, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIfAnd = {"AlignVector", "false", "MaxVectorSize", ">= 8"}, applyIfCPUFeatureAnd = {"sse4.1", "true", "avx2", "false"}) // CPU: avx2 -> vector_width: 32 -> elements in vector: 8 - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.MUL_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_I, "> 0", IRNode.MUL_VI, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIfAnd = {"AlignVector", "false", "MaxVectorSize", ">= 8"}, applyIfCPUFeatureAnd = {"avx2", "true", "avx512", "false"}) // CPU: avx512 -> vector_width: 64 -> elements in vector: 16 - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.MUL_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_I, "> 0", IRNode.MUL_VI, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIfAnd = {"AlignVector", "false", "MaxVectorSize", ">= 8"}, applyIfCPUFeature = {"avx512", "true"}) // CPU: asimd -> vector_width: 32 -> elements in vector: 8 - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.MUL_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_I, "> 0", IRNode.MUL_VI, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIfAnd = {"AlignVector", "false", "MaxVectorSize", ">= 8"}, applyIfCPUFeature = {"asimd", "true"}) public static void testIntM18(int[] data) { @@ -2057,19 +2057,19 @@ public static void runIntM18() { @Test // CPU: sse4.1 to avx -> vector_width: 16 -> elements in vector: 4 - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.MUL_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_I, "> 0", IRNode.MUL_VI, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIfAnd = {"AlignVector", "false", "MaxVectorSize", ">= 8"}, applyIfCPUFeatureAnd = {"sse4.1", "true", "avx2", "false"}) // CPU: avx2 -> vector_width: 32 -> elements in vector: 8 - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.MUL_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_I, "> 0", IRNode.MUL_VI, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIfAnd = {"AlignVector", "false", "MaxVectorSize", ">= 8"}, applyIfCPUFeatureAnd = {"avx2", "true", "avx512", "false"}) // CPU: avx512 -> vector_width: 64 -> elements in vector: 16 - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.MUL_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_I, "> 0", IRNode.MUL_VI, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIfAnd = {"AlignVector", "false", "MaxVectorSize", ">= 8"}, applyIfCPUFeature = {"avx512", "true"}) // CPU: asimd -> vector_width: 32 -> elements in vector: 8 - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.MUL_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_I, "> 0", IRNode.MUL_VI, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIfAnd = {"AlignVector", "false", "MaxVectorSize", ">= 8"}, applyIfCPUFeature = {"asimd", "true"}) public static void testIntP18(int[] data) { @@ -2089,19 +2089,19 @@ public static void runIntP18() { @Test // CPU: sse4.1 to avx -> vector_width: 16 -> elements in vector: 4 - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.MUL_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_I, "> 0", IRNode.MUL_VI, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIfAnd = {"AlignVector", "false", "MaxVectorSize", ">= 8"}, applyIfCPUFeatureAnd = {"sse4.1", "true", "avx2", "false"}) // CPU: avx2 -> vector_width: 32 -> elements in vector: 8 - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.MUL_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_I, "> 0", IRNode.MUL_VI, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIfAnd = {"AlignVector", "false", "MaxVectorSize", ">= 8"}, applyIfCPUFeatureAnd = {"avx2", "true", "avx512", "false"}) // CPU: avx512 -> vector_width: 64 -> elements in vector: 16 - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.MUL_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_I, "> 0", IRNode.MUL_VI, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIfAnd = {"AlignVector", "false", "MaxVectorSize", ">= 8"}, applyIfCPUFeature = {"avx512", "true"}) // CPU: asimd -> vector_width: 32 -> elements in vector: 8 - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.MUL_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_I, "> 0", IRNode.MUL_VI, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIfAnd = {"AlignVector", "false", "MaxVectorSize", ">= 8"}, applyIfCPUFeature = {"asimd", "true"}) public static void testIntM20(int[] data) { @@ -2121,23 +2121,23 @@ public static void runIntM20() { @Test // CPU: sse4.1 to avx -> vector_width: 16 -> elements in vector: 4 - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.MUL_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_I, "> 0", IRNode.MUL_VI, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIfAnd = {"AlignVector", "false", "MaxVectorSize", ">= 8"}, applyIfCPUFeatureAnd = {"sse4.1", "true", "avx2", "false"}) // Vectorize when strict alignment guaranteed. - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.MUL_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_I, "> 0", IRNode.MUL_VI, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIfAnd = {"AlignVector", "true", "MaxVectorSize", ">= 8"}, applyIfCPUFeatureAnd = {"sse4.1", "true", "avx2", "false"}) // CPU: avx2 -> vector_width: 32 -> elements in vector: 8 - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.MUL_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_I, "> 0", IRNode.MUL_VI, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIfAnd = {"AlignVector", "false", "MaxVectorSize", ">= 8"}, applyIfCPUFeatureAnd = {"avx2", "true", "avx512", "false"}) // CPU: avx512 -> vector_width: 64 -> elements in vector: 16 - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.MUL_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_I, "> 0", IRNode.MUL_VI, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIfAnd = {"AlignVector", "false", "MaxVectorSize", ">= 8"}, applyIfCPUFeature = {"avx512", "true"}) // CPU: asimd -> vector_width: 32 -> elements in vector: 8 - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.MUL_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_I, "> 0", IRNode.MUL_VI, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIfAnd = {"AlignVector", "false", "MaxVectorSize", ">= 8"}, applyIfCPUFeature = {"asimd", "true"}) public static void testIntP20(int[] data) { @@ -2157,35 +2157,35 @@ public static void runIntP20() { @Test // CPU: sse4.1 to avx -> vector_width: 16 -> elements in vector: 4 - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.MUL_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_I, "> 0", IRNode.MUL_VI, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIfAnd = {"AlignVector", "false", "MaxVectorSize", ">= 8"}, applyIfCPUFeatureAnd = {"sse4.1", "true", "avx2", "false"}) // Strict alignment not possible. - @IR(failOn = {IRNode.LOAD_VECTOR, IRNode.MUL_V, IRNode.STORE_VECTOR}, + @IR(failOn = {IRNode.LOAD_VECTOR_I, IRNode.MUL_VI, IRNode.STORE_VECTOR}, applyIf = {"AlignVector", "true"}, applyIfCPUFeatureAnd = {"sse4.1", "true", "avx2", "false"}) // CPU: avx2 -> vector_width: 32 -> elements in vector: 8 - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.MUL_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_I, "> 0", IRNode.MUL_VI, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIfAnd = {"AlignVector", "false", "MaxVectorSize", ">= 8"}, applyIfCPUFeatureAnd = {"avx2", "true", "avx512", "false"}) // Strict alignment not possible. - @IR(failOn = {IRNode.LOAD_VECTOR, IRNode.MUL_V, IRNode.STORE_VECTOR}, + @IR(failOn = {IRNode.LOAD_VECTOR_I, IRNode.MUL_VI, IRNode.STORE_VECTOR}, applyIf = {"AlignVector", "true"}, applyIfCPUFeatureAnd = {"avx2", "true", "avx512", "false"}) // CPU: avx512 -> vector_width: 64 -> elements in vector: 16 - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.MUL_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_I, "> 0", IRNode.MUL_VI, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIfAnd = {"AlignVector", "false", "MaxVectorSize", ">= 8"}, applyIfCPUFeature = {"avx512", "true"}) // Strict alignment not possible. - @IR(failOn = {IRNode.LOAD_VECTOR, IRNode.MUL_V, IRNode.STORE_VECTOR}, + @IR(failOn = {IRNode.LOAD_VECTOR_I, IRNode.MUL_VI, IRNode.STORE_VECTOR}, applyIf = {"AlignVector", "true"}, applyIfCPUFeature = {"avx512", "true"}) // CPU: asimd -> vector_width: 32 -> elements in vector: 8 - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.MUL_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_I, "> 0", IRNode.MUL_VI, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIfAnd = {"AlignVector", "false", "MaxVectorSize", ">= 8"}, applyIfCPUFeature = {"asimd", "true"}) // Strict alignment not possible. - @IR(failOn = {IRNode.LOAD_VECTOR, IRNode.MUL_V, IRNode.STORE_VECTOR}, + @IR(failOn = {IRNode.LOAD_VECTOR_I, IRNode.MUL_VI, IRNode.STORE_VECTOR}, applyIf = {"AlignVector", "true"}, applyIfCPUFeature = {"asimd", "true"}) public static void testIntM31(int[] data) { @@ -2205,19 +2205,19 @@ public static void runIntM31() { @Test // CPU: sse4.1 to avx -> vector_width: 16 -> elements in vector: 4 - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.MUL_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_I, "> 0", IRNode.MUL_VI, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIfAnd = {"AlignVector", "false", "MaxVectorSize", ">= 8"}, applyIfCPUFeatureAnd = {"sse4.1", "true", "avx2", "false"}) // CPU: avx2 -> vector_width: 32 -> elements in vector: 8 - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.MUL_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_I, "> 0", IRNode.MUL_VI, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIfAnd = {"AlignVector", "false", "MaxVectorSize", ">= 8"}, applyIfCPUFeatureAnd = {"avx2", "true", "avx512", "false"}) // CPU: avx512 -> vector_width: 64 -> elements in vector: 16 - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.MUL_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_I, "> 0", IRNode.MUL_VI, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIfAnd = {"AlignVector", "false", "MaxVectorSize", ">= 8"}, applyIfCPUFeature = {"avx512", "true"}) // CPU: asimd -> vector_width: 32 -> elements in vector: 8 - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.MUL_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_I, "> 0", IRNode.MUL_VI, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIfAnd = {"AlignVector", "false", "MaxVectorSize", ">= 8"}, applyIfCPUFeature = {"asimd", "true"}) public static void testIntP31(int[] data) { @@ -2237,19 +2237,19 @@ public static void runIntP31() { @Test // CPU: sse4.1 to avx -> vector_width: 16 -> elements in vector: 4 - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.MUL_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_I, "> 0", IRNode.MUL_VI, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIfAnd = {"AlignVector", "false", "MaxVectorSize", ">= 8"}, applyIfCPUFeatureAnd = {"sse4.1", "true", "avx2", "false"}) // CPU: avx2 -> vector_width: 32 -> elements in vector: 8 - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.MUL_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_I, "> 0", IRNode.MUL_VI, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIfAnd = {"AlignVector", "false", "MaxVectorSize", ">= 8"}, applyIfCPUFeatureAnd = {"avx2", "true", "avx512", "false"}) // CPU: avx512 -> vector_width: 64 -> elements in vector: 16 - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.MUL_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_I, "> 0", IRNode.MUL_VI, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIfAnd = {"AlignVector", "false", "MaxVectorSize", ">= 8"}, applyIfCPUFeature = {"avx512", "true"}) // CPU: asimd -> vector_width: 32 -> elements in vector: 8 - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.MUL_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_I, "> 0", IRNode.MUL_VI, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIfAnd = {"AlignVector", "false", "MaxVectorSize", ">= 8"}, applyIfCPUFeature = {"asimd", "true"}) public static void testIntM32(int[] data) { @@ -2269,35 +2269,35 @@ public static void runIntM32() { @Test // CPU: sse4.1 to avx -> vector_width: 16 -> elements in vector: 4 - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.MUL_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_I, "> 0", IRNode.MUL_VI, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIfAnd = {"AlignVector", "false", "MaxVectorSize", ">= 8"}, applyIfCPUFeatureAnd = {"sse4.1", "true", "avx2", "false"}) // Vectorize when strict alignment guaranteed. - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.MUL_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_I, "> 0", IRNode.MUL_VI, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIfAnd = {"AlignVector", "true", "MaxVectorSize", ">= 8"}, applyIfCPUFeatureAnd = {"sse4.1", "true", "avx2", "false"}) // CPU: avx2 -> vector_width: 32 -> elements in vector: 8 - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.MUL_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_I, "> 0", IRNode.MUL_VI, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIfAnd = {"AlignVector", "false", "MaxVectorSize", ">= 8"}, applyIfCPUFeatureAnd = {"avx2", "true", "avx512", "false"}) // Vectorize when strict alignment guaranteed. - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.MUL_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_I, "> 0", IRNode.MUL_VI, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIfAnd = {"AlignVector", "true", "MaxVectorSize", ">= 8"}, applyIfCPUFeatureAnd = {"avx2", "true", "avx512", "false"}) // CPU: avx512 -> vector_width: 64 -> elements in vector: 16 - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.MUL_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_I, "> 0", IRNode.MUL_VI, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIfAnd = {"AlignVector", "false", "MaxVectorSize", ">= 8"}, applyIfCPUFeature = {"avx512", "true"}) // Vectorize when strict alignment guaranteed. - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.MUL_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_I, "> 0", IRNode.MUL_VI, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIfAnd = {"AlignVector", "true", "MaxVectorSize", ">= 8"}, applyIfCPUFeature = {"avx512", "true"}) // CPU: asimd -> vector_width: 32 -> elements in vector: 8 - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.MUL_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_I, "> 0", IRNode.MUL_VI, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIfAnd = {"AlignVector", "false", "MaxVectorSize", ">= 8"}, applyIfCPUFeature = {"asimd", "true"}) // Vectorize when strict alignment guaranteed. - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.MUL_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_I, "> 0", IRNode.MUL_VI, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIfAnd = {"AlignVector", "true", "MaxVectorSize", ">= 8"}, applyIfCPUFeature = {"asimd", "true"}) public static void testIntP32(int[] data) { @@ -2317,35 +2317,35 @@ public static void runIntP32() { @Test // CPU: sse4.1 to avx -> vector_width: 16 -> elements in vector: 4 - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.MUL_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_I, "> 0", IRNode.MUL_VI, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIfAnd = {"AlignVector", "false", "MaxVectorSize", ">= 8"}, applyIfCPUFeatureAnd = {"sse4.1", "true", "avx2", "false"}) // Strict alignment not possible. - @IR(failOn = {IRNode.LOAD_VECTOR, IRNode.MUL_V, IRNode.STORE_VECTOR}, + @IR(failOn = {IRNode.LOAD_VECTOR_I, IRNode.MUL_VI, IRNode.STORE_VECTOR}, applyIf = {"AlignVector", "true"}, applyIfCPUFeatureAnd = {"sse4.1", "true", "avx2", "false"}) // CPU: avx2 -> vector_width: 32 -> elements in vector: 8 - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.MUL_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_I, "> 0", IRNode.MUL_VI, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIfAnd = {"AlignVector", "false", "MaxVectorSize", ">= 8"}, applyIfCPUFeatureAnd = {"avx2", "true", "avx512", "false"}) // Strict alignment not possible. - @IR(failOn = {IRNode.LOAD_VECTOR, IRNode.MUL_V, IRNode.STORE_VECTOR}, + @IR(failOn = {IRNode.LOAD_VECTOR_I, IRNode.MUL_VI, IRNode.STORE_VECTOR}, applyIf = {"AlignVector", "true"}, applyIfCPUFeatureAnd = {"avx2", "true", "avx512", "false"}) // CPU: avx512 -> vector_width: 64 -> elements in vector: 16 - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.MUL_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_I, "> 0", IRNode.MUL_VI, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIfAnd = {"AlignVector", "false", "MaxVectorSize", ">= 8"}, applyIfCPUFeature = {"avx512", "true"}) // Strict alignment not possible. - @IR(failOn = {IRNode.LOAD_VECTOR, IRNode.MUL_V, IRNode.STORE_VECTOR}, + @IR(failOn = {IRNode.LOAD_VECTOR_I, IRNode.MUL_VI, IRNode.STORE_VECTOR}, applyIf = {"AlignVector", "true"}, applyIfCPUFeature = {"avx512", "true"}) // CPU: asimd -> vector_width: 32 -> elements in vector: 8 - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.MUL_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_I, "> 0", IRNode.MUL_VI, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIfAnd = {"AlignVector", "false", "MaxVectorSize", ">= 8"}, applyIfCPUFeature = {"asimd", "true"}) // Strict alignment not possible. - @IR(failOn = {IRNode.LOAD_VECTOR, IRNode.MUL_V, IRNode.STORE_VECTOR}, + @IR(failOn = {IRNode.LOAD_VECTOR_I, IRNode.MUL_VI, IRNode.STORE_VECTOR}, applyIf = {"AlignVector", "true"}, applyIfCPUFeature = {"asimd", "true"}) public static void testIntM63(int[] data) { @@ -2365,19 +2365,19 @@ public static void runIntM63() { @Test // CPU: sse4.1 to avx -> vector_width: 16 -> elements in vector: 4 - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.MUL_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_I, "> 0", IRNode.MUL_VI, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIfAnd = {"AlignVector", "false", "MaxVectorSize", ">= 8"}, applyIfCPUFeatureAnd = {"sse4.1", "true", "avx2", "false"}) // CPU: avx2 -> vector_width: 32 -> elements in vector: 8 - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.MUL_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_I, "> 0", IRNode.MUL_VI, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIfAnd = {"AlignVector", "false", "MaxVectorSize", ">= 8"}, applyIfCPUFeatureAnd = {"avx2", "true", "avx512", "false"}) // CPU: avx512 -> vector_width: 64 -> elements in vector: 16 - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.MUL_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_I, "> 0", IRNode.MUL_VI, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIfAnd = {"AlignVector", "false", "MaxVectorSize", ">= 8"}, applyIfCPUFeature = {"avx512", "true"}) // CPU: asimd -> vector_width: 32 -> elements in vector: 8 - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.MUL_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_I, "> 0", IRNode.MUL_VI, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIfAnd = {"AlignVector", "false", "MaxVectorSize", ">= 8"}, applyIfCPUFeature = {"asimd", "true"}) public static void testIntP63(int[] data) { @@ -2397,19 +2397,19 @@ public static void runIntP63() { @Test // CPU: sse4.1 to avx -> vector_width: 16 -> elements in vector: 4 - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.MUL_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_I, "> 0", IRNode.MUL_VI, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIfAnd = {"AlignVector", "false", "MaxVectorSize", ">= 8"}, applyIfCPUFeatureAnd = {"sse4.1", "true", "avx2", "false"}) // CPU: avx2 -> vector_width: 32 -> elements in vector: 8 - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.MUL_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_I, "> 0", IRNode.MUL_VI, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIfAnd = {"AlignVector", "false", "MaxVectorSize", ">= 8"}, applyIfCPUFeatureAnd = {"avx2", "true", "avx512", "false"}) // CPU: avx512 -> vector_width: 64 -> elements in vector: 16 - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.MUL_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_I, "> 0", IRNode.MUL_VI, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIfAnd = {"AlignVector", "false", "MaxVectorSize", ">= 8"}, applyIfCPUFeature = {"avx512", "true"}) // CPU: asimd -> vector_width: 32 -> elements in vector: 8 - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.MUL_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_I, "> 0", IRNode.MUL_VI, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIfAnd = {"AlignVector", "false", "MaxVectorSize", ">= 8"}, applyIfCPUFeature = {"asimd", "true"}) public static void testIntM64(int[] data) { @@ -2429,35 +2429,35 @@ public static void runIntM64() { @Test // CPU: sse4.1 to avx -> vector_width: 16 -> elements in vector: 4 - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.MUL_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_I, "> 0", IRNode.MUL_VI, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIfAnd = {"AlignVector", "false", "MaxVectorSize", ">= 8"}, applyIfCPUFeatureAnd = {"sse4.1", "true", "avx2", "false"}) // Vectorize when strict alignment guaranteed. - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.MUL_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_I, "> 0", IRNode.MUL_VI, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIfAnd = {"AlignVector", "true", "MaxVectorSize", ">= 8"}, applyIfCPUFeatureAnd = {"sse4.1", "true", "avx2", "false"}) // CPU: avx2 -> vector_width: 32 -> elements in vector: 8 - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.MUL_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_I, "> 0", IRNode.MUL_VI, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIfAnd = {"AlignVector", "false", "MaxVectorSize", ">= 8"}, applyIfCPUFeatureAnd = {"avx2", "true", "avx512", "false"}) // Vectorize when strict alignment guaranteed. - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.MUL_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_I, "> 0", IRNode.MUL_VI, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIfAnd = {"AlignVector", "true", "MaxVectorSize", ">= 8"}, applyIfCPUFeatureAnd = {"avx2", "true", "avx512", "false"}) // CPU: avx512 -> vector_width: 64 -> elements in vector: 16 - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.MUL_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_I, "> 0", IRNode.MUL_VI, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIfAnd = {"AlignVector", "false", "MaxVectorSize", ">= 8"}, applyIfCPUFeature = {"avx512", "true"}) // Vectorize when strict alignment guaranteed. - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.MUL_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_I, "> 0", IRNode.MUL_VI, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIfAnd = {"AlignVector", "true", "MaxVectorSize", ">= 8"}, applyIfCPUFeature = {"avx512", "true"}) // CPU: asimd -> vector_width: 32 -> elements in vector: 8 - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.MUL_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_I, "> 0", IRNode.MUL_VI, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIfAnd = {"AlignVector", "false", "MaxVectorSize", ">= 8"}, applyIfCPUFeature = {"asimd", "true"}) // Vectorize when strict alignment guaranteed. - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.MUL_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_I, "> 0", IRNode.MUL_VI, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIfAnd = {"AlignVector", "true", "MaxVectorSize", ">= 8"}, applyIfCPUFeature = {"asimd", "true"}) public static void testIntP64(int[] data) { @@ -2477,35 +2477,35 @@ public static void runIntP64() { @Test // CPU: sse4.1 to avx -> vector_width: 16 -> elements in vector: 4 - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.MUL_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_I, "> 0", IRNode.MUL_VI, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIfAnd = {"AlignVector", "false", "MaxVectorSize", ">= 8"}, applyIfCPUFeatureAnd = {"sse4.1", "true", "avx2", "false"}) // Strict alignment not possible. - @IR(failOn = {IRNode.LOAD_VECTOR, IRNode.MUL_V, IRNode.STORE_VECTOR}, + @IR(failOn = {IRNode.LOAD_VECTOR_I, IRNode.MUL_VI, IRNode.STORE_VECTOR}, applyIf = {"AlignVector", "true"}, applyIfCPUFeatureAnd = {"sse4.1", "true", "avx2", "false"}) // CPU: avx2 -> vector_width: 32 -> elements in vector: 8 - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.MUL_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_I, "> 0", IRNode.MUL_VI, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIfAnd = {"AlignVector", "false", "MaxVectorSize", ">= 8"}, applyIfCPUFeatureAnd = {"avx2", "true", "avx512", "false"}) // Strict alignment not possible. - @IR(failOn = {IRNode.LOAD_VECTOR, IRNode.MUL_V, IRNode.STORE_VECTOR}, + @IR(failOn = {IRNode.LOAD_VECTOR_I, IRNode.MUL_VI, IRNode.STORE_VECTOR}, applyIf = {"AlignVector", "true"}, applyIfCPUFeatureAnd = {"avx2", "true", "avx512", "false"}) // CPU: avx512 -> vector_width: 64 -> elements in vector: 16 - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.MUL_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_I, "> 0", IRNode.MUL_VI, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIfAnd = {"AlignVector", "false", "MaxVectorSize", ">= 8"}, applyIfCPUFeature = {"avx512", "true"}) // Strict alignment not possible. - @IR(failOn = {IRNode.LOAD_VECTOR, IRNode.MUL_V, IRNode.STORE_VECTOR}, + @IR(failOn = {IRNode.LOAD_VECTOR_I, IRNode.MUL_VI, IRNode.STORE_VECTOR}, applyIf = {"AlignVector", "true"}, applyIfCPUFeature = {"avx512", "true"}) // CPU: asimd -> vector_width: 32 -> elements in vector: 8 - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.MUL_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_I, "> 0", IRNode.MUL_VI, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIfAnd = {"AlignVector", "false", "MaxVectorSize", ">= 8"}, applyIfCPUFeature = {"asimd", "true"}) // Strict alignment not possible. - @IR(failOn = {IRNode.LOAD_VECTOR, IRNode.MUL_V, IRNode.STORE_VECTOR}, + @IR(failOn = {IRNode.LOAD_VECTOR_I, IRNode.MUL_VI, IRNode.STORE_VECTOR}, applyIf = {"AlignVector", "true"}, applyIfCPUFeature = {"asimd", "true"}) public static void testIntM65(int[] data) { @@ -2525,19 +2525,19 @@ public static void runIntM65() { @Test // CPU: sse4.1 to avx -> vector_width: 16 -> elements in vector: 4 - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.MUL_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_I, "> 0", IRNode.MUL_VI, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIfAnd = {"AlignVector", "false", "MaxVectorSize", ">= 8"}, applyIfCPUFeatureAnd = {"sse4.1", "true", "avx2", "false"}) // CPU: avx2 -> vector_width: 32 -> elements in vector: 8 - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.MUL_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_I, "> 0", IRNode.MUL_VI, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIfAnd = {"AlignVector", "false", "MaxVectorSize", ">= 8"}, applyIfCPUFeatureAnd = {"avx2", "true", "avx512", "false"}) // CPU: avx512 -> vector_width: 64 -> elements in vector: 16 - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.MUL_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_I, "> 0", IRNode.MUL_VI, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIfAnd = {"AlignVector", "false", "MaxVectorSize", ">= 8"}, applyIfCPUFeature = {"avx512", "true"}) // CPU: asimd -> vector_width: 32 -> elements in vector: 8 - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.MUL_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_I, "> 0", IRNode.MUL_VI, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIfAnd = {"AlignVector", "false", "MaxVectorSize", ">= 8"}, applyIfCPUFeature = {"asimd", "true"}) public static void testIntP65(int[] data) { @@ -2557,19 +2557,19 @@ public static void runIntP65() { @Test // CPU: sse4.1 to avx -> vector_width: 16 -> elements in vector: 4 - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.MUL_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_I, "> 0", IRNode.MUL_VI, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIfAnd = {"AlignVector", "false", "MaxVectorSize", ">= 8"}, applyIfCPUFeatureAnd = {"sse4.1", "true", "avx2", "false"}) // CPU: avx2 -> vector_width: 32 -> elements in vector: 8 - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.MUL_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_I, "> 0", IRNode.MUL_VI, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIfAnd = {"AlignVector", "false", "MaxVectorSize", ">= 8"}, applyIfCPUFeatureAnd = {"avx2", "true", "avx512", "false"}) // CPU: avx512 -> vector_width: 64 -> elements in vector: 16 - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.MUL_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_I, "> 0", IRNode.MUL_VI, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIfAnd = {"AlignVector", "false", "MaxVectorSize", ">= 8"}, applyIfCPUFeature = {"avx512", "true"}) // CPU: asimd -> vector_width: 32 -> elements in vector: 8 - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.MUL_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_I, "> 0", IRNode.MUL_VI, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIfAnd = {"AlignVector", "false", "MaxVectorSize", ">= 8"}, applyIfCPUFeature = {"asimd", "true"}) public static void testIntM128(int[] data) { @@ -2589,35 +2589,35 @@ public static void runIntM128() { @Test // CPU: sse4.1 to avx -> vector_width: 16 -> elements in vector: 4 - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.MUL_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_I, "> 0", IRNode.MUL_VI, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIfAnd = {"AlignVector", "false", "MaxVectorSize", ">= 8"}, applyIfCPUFeatureAnd = {"sse4.1", "true", "avx2", "false"}) // Vectorize when strict alignment guaranteed. - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.MUL_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_I, "> 0", IRNode.MUL_VI, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIfAnd = {"AlignVector", "true", "MaxVectorSize", ">= 8"}, applyIfCPUFeatureAnd = {"sse4.1", "true", "avx2", "false"}) // CPU: avx2 -> vector_width: 32 -> elements in vector: 8 - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.MUL_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_I, "> 0", IRNode.MUL_VI, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIfAnd = {"AlignVector", "false", "MaxVectorSize", ">= 8"}, applyIfCPUFeatureAnd = {"avx2", "true", "avx512", "false"}) // Vectorize when strict alignment guaranteed. - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.MUL_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_I, "> 0", IRNode.MUL_VI, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIfAnd = {"AlignVector", "true", "MaxVectorSize", ">= 8"}, applyIfCPUFeatureAnd = {"avx2", "true", "avx512", "false"}) // CPU: avx512 -> vector_width: 64 -> elements in vector: 16 - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.MUL_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_I, "> 0", IRNode.MUL_VI, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIfAnd = {"AlignVector", "false", "MaxVectorSize", ">= 8"}, applyIfCPUFeature = {"avx512", "true"}) // Vectorize when strict alignment guaranteed. - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.MUL_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_I, "> 0", IRNode.MUL_VI, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIfAnd = {"AlignVector", "true", "MaxVectorSize", ">= 8"}, applyIfCPUFeature = {"avx512", "true"}) // CPU: asimd -> vector_width: 32 -> elements in vector: 8 - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.MUL_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_I, "> 0", IRNode.MUL_VI, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIfAnd = {"AlignVector", "false", "MaxVectorSize", ">= 8"}, applyIfCPUFeature = {"asimd", "true"}) // Vectorize when strict alignment guaranteed. - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.MUL_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_I, "> 0", IRNode.MUL_VI, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIfAnd = {"AlignVector", "true", "MaxVectorSize", ">= 8"}, applyIfCPUFeature = {"asimd", "true"}) public static void testIntP128(int[] data) { @@ -2637,35 +2637,35 @@ public static void runIntP128() { @Test // CPU: sse4.1 to avx -> vector_width: 16 -> elements in vector: 4 - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.MUL_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_I, "> 0", IRNode.MUL_VI, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIfAnd = {"AlignVector", "false", "MaxVectorSize", ">= 8"}, applyIfCPUFeatureAnd = {"sse4.1", "true", "avx2", "false"}) // Strict alignment not possible. - @IR(failOn = {IRNode.LOAD_VECTOR, IRNode.MUL_V, IRNode.STORE_VECTOR}, + @IR(failOn = {IRNode.LOAD_VECTOR_I, IRNode.MUL_VI, IRNode.STORE_VECTOR}, applyIf = {"AlignVector", "true"}, applyIfCPUFeatureAnd = {"sse4.1", "true", "avx2", "false"}) // CPU: avx2 -> vector_width: 32 -> elements in vector: 8 - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.MUL_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_I, "> 0", IRNode.MUL_VI, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIfAnd = {"AlignVector", "false", "MaxVectorSize", ">= 8"}, applyIfCPUFeatureAnd = {"avx2", "true", "avx512", "false"}) // Strict alignment not possible. - @IR(failOn = {IRNode.LOAD_VECTOR, IRNode.MUL_V, IRNode.STORE_VECTOR}, + @IR(failOn = {IRNode.LOAD_VECTOR_I, IRNode.MUL_VI, IRNode.STORE_VECTOR}, applyIf = {"AlignVector", "true"}, applyIfCPUFeatureAnd = {"avx2", "true", "avx512", "false"}) // CPU: avx512 -> vector_width: 64 -> elements in vector: 16 - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.MUL_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_I, "> 0", IRNode.MUL_VI, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIfAnd = {"AlignVector", "false", "MaxVectorSize", ">= 8"}, applyIfCPUFeature = {"avx512", "true"}) // Strict alignment not possible. - @IR(failOn = {IRNode.LOAD_VECTOR, IRNode.MUL_V, IRNode.STORE_VECTOR}, + @IR(failOn = {IRNode.LOAD_VECTOR_I, IRNode.MUL_VI, IRNode.STORE_VECTOR}, applyIf = {"AlignVector", "true"}, applyIfCPUFeature = {"avx512", "true"}) // CPU: asimd -> vector_width: 32 -> elements in vector: 8 - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.MUL_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_I, "> 0", IRNode.MUL_VI, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIfAnd = {"AlignVector", "false", "MaxVectorSize", ">= 8"}, applyIfCPUFeature = {"asimd", "true"}) // Strict alignment not possible. - @IR(failOn = {IRNode.LOAD_VECTOR, IRNode.MUL_V, IRNode.STORE_VECTOR}, + @IR(failOn = {IRNode.LOAD_VECTOR_I, IRNode.MUL_VI, IRNode.STORE_VECTOR}, applyIf = {"AlignVector", "true"}, applyIfCPUFeature = {"asimd", "true"}) public static void testIntM129(int[] data) { @@ -2685,19 +2685,19 @@ public static void runIntM129() { @Test // CPU: sse4.1 to avx -> vector_width: 16 -> elements in vector: 4 - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.MUL_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_I, "> 0", IRNode.MUL_VI, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIfAnd = {"AlignVector", "false", "MaxVectorSize", ">= 8"}, applyIfCPUFeatureAnd = {"sse4.1", "true", "avx2", "false"}) // CPU: avx2 -> vector_width: 32 -> elements in vector: 8 - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.MUL_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_I, "> 0", IRNode.MUL_VI, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIfAnd = {"AlignVector", "false", "MaxVectorSize", ">= 8"}, applyIfCPUFeatureAnd = {"avx2", "true", "avx512", "false"}) // CPU: avx512 -> vector_width: 64 -> elements in vector: 16 - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.MUL_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_I, "> 0", IRNode.MUL_VI, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIfAnd = {"AlignVector", "false", "MaxVectorSize", ">= 8"}, applyIfCPUFeature = {"avx512", "true"}) // CPU: asimd -> vector_width: 32 -> elements in vector: 8 - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.MUL_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_I, "> 0", IRNode.MUL_VI, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIfAnd = {"AlignVector", "false", "MaxVectorSize", ">= 8"}, applyIfCPUFeature = {"asimd", "true"}) public static void testIntP129(int[] data) { @@ -2717,19 +2717,19 @@ public static void runIntP129() { @Test // CPU: sse4.1 to avx -> vector_width: 16 -> elements in vector: 4 - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.MUL_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_I, "> 0", IRNode.MUL_VI, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIfAnd = {"AlignVector", "false", "MaxVectorSize", ">= 8"}, applyIfCPUFeatureAnd = {"sse4.1", "true", "avx2", "false"}) // CPU: avx2 -> vector_width: 32 -> elements in vector: 8 - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.MUL_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_I, "> 0", IRNode.MUL_VI, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIfAnd = {"AlignVector", "false", "MaxVectorSize", ">= 8"}, applyIfCPUFeatureAnd = {"avx2", "true", "avx512", "false"}) // CPU: avx512 -> vector_width: 64 -> elements in vector: 16 - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.MUL_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_I, "> 0", IRNode.MUL_VI, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIfAnd = {"AlignVector", "false", "MaxVectorSize", ">= 8"}, applyIfCPUFeature = {"avx512", "true"}) // CPU: asimd -> vector_width: 32 -> elements in vector: 8 - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.MUL_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_I, "> 0", IRNode.MUL_VI, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIfAnd = {"AlignVector", "false", "MaxVectorSize", ">= 8"}, applyIfCPUFeature = {"asimd", "true"}) public static void testIntM192(int[] data) { @@ -2749,35 +2749,35 @@ public static void runIntM192() { @Test // CPU: sse4.1 to avx -> vector_width: 16 -> elements in vector: 4 - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.MUL_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_I, "> 0", IRNode.MUL_VI, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIfAnd = {"AlignVector", "false", "MaxVectorSize", ">= 8"}, applyIfCPUFeatureAnd = {"sse4.1", "true", "avx2", "false"}) // Vectorize when strict alignment guaranteed. - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.MUL_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_I, "> 0", IRNode.MUL_VI, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIfAnd = {"AlignVector", "true", "MaxVectorSize", ">= 8"}, applyIfCPUFeatureAnd = {"sse4.1", "true", "avx2", "false"}) // CPU: avx2 -> vector_width: 32 -> elements in vector: 8 - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.MUL_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_I, "> 0", IRNode.MUL_VI, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIfAnd = {"AlignVector", "false", "MaxVectorSize", ">= 8"}, applyIfCPUFeatureAnd = {"avx2", "true", "avx512", "false"}) // Vectorize when strict alignment guaranteed. - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.MUL_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_I, "> 0", IRNode.MUL_VI, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIfAnd = {"AlignVector", "true", "MaxVectorSize", ">= 8"}, applyIfCPUFeatureAnd = {"avx2", "true", "avx512", "false"}) // CPU: avx512 -> vector_width: 64 -> elements in vector: 16 - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.MUL_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_I, "> 0", IRNode.MUL_VI, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIfAnd = {"AlignVector", "false", "MaxVectorSize", ">= 8"}, applyIfCPUFeature = {"avx512", "true"}) // Vectorize when strict alignment guaranteed. - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.MUL_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_I, "> 0", IRNode.MUL_VI, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIfAnd = {"AlignVector", "true", "MaxVectorSize", ">= 8"}, applyIfCPUFeature = {"avx512", "true"}) // CPU: asimd -> vector_width: 32 -> elements in vector: 8 - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.MUL_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_I, "> 0", IRNode.MUL_VI, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIfAnd = {"AlignVector", "false", "MaxVectorSize", ">= 8"}, applyIfCPUFeature = {"asimd", "true"}) // Vectorize when strict alignment guaranteed. - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.MUL_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_I, "> 0", IRNode.MUL_VI, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIfAnd = {"AlignVector", "true", "MaxVectorSize", ">= 8"}, applyIfCPUFeature = {"asimd", "true"}) public static void testIntP192(int[] data) { @@ -2797,19 +2797,19 @@ public static void runIntP192() { @Test // CPU: sse4.1 to avx -> vector_width: 16 -> elements in vector: 2 - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.ADD_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_L, "> 0", IRNode.ADD_VL, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIfAnd = {"AlignVector", "false", "MaxVectorSize", ">= 16"}, applyIfCPUFeatureAnd = {"sse4.1", "true", "avx2", "false"}) // CPU: avx2 -> vector_width: 32 -> elements in vector: 4 - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.ADD_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_L, "> 0", IRNode.ADD_VL, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIfAnd = {"AlignVector", "false", "MaxVectorSize", ">= 16"}, applyIfCPUFeatureAnd = {"avx2", "true", "avx512", "false"}) // CPU: avx512 -> vector_width: 64 -> elements in vector: 8 - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.ADD_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_L, "> 0", IRNode.ADD_VL, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIfAnd = {"AlignVector", "false", "MaxVectorSize", ">= 16"}, applyIfCPUFeature = {"avx512", "true"}) // CPU: asimd -> vector_width: 32 -> elements in vector: 4 - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.ADD_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_L, "> 0", IRNode.ADD_VL, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIfAnd = {"AlignVector", "false", "MaxVectorSize", ">= 16"}, applyIfCPUFeature = {"asimd", "true"}) public static void testLongP0(long[] data) { @@ -2829,35 +2829,35 @@ public static void runLongP0() { @Test // CPU: sse4.1 to avx -> vector_width: 16 -> elements in vector: 2 - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.ADD_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_L, "> 0", IRNode.ADD_VL, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIfAnd = {"AlignVector", "false", "MaxVectorSize", ">= 16"}, applyIfCPUFeatureAnd = {"sse4.1", "true", "avx2", "false"}) // Strict alignment not possible. - @IR(failOn = {IRNode.LOAD_VECTOR, IRNode.ADD_V, IRNode.STORE_VECTOR}, + @IR(failOn = {IRNode.LOAD_VECTOR_L, IRNode.ADD_VL, IRNode.STORE_VECTOR}, applyIf = {"AlignVector", "true"}, applyIfCPUFeatureAnd = {"sse4.1", "true", "avx2", "false"}) // CPU: avx2 -> vector_width: 32 -> elements in vector: 4 - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.ADD_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_L, "> 0", IRNode.ADD_VL, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIfAnd = {"AlignVector", "false", "MaxVectorSize", ">= 16"}, applyIfCPUFeatureAnd = {"avx2", "true", "avx512", "false"}) // Strict alignment not possible. - @IR(failOn = {IRNode.LOAD_VECTOR, IRNode.ADD_V, IRNode.STORE_VECTOR}, + @IR(failOn = {IRNode.LOAD_VECTOR_L, IRNode.ADD_VL, IRNode.STORE_VECTOR}, applyIf = {"AlignVector", "true"}, applyIfCPUFeatureAnd = {"avx2", "true", "avx512", "false"}) // CPU: avx512 -> vector_width: 64 -> elements in vector: 8 - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.ADD_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_L, "> 0", IRNode.ADD_VL, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIfAnd = {"AlignVector", "false", "MaxVectorSize", ">= 16"}, applyIfCPUFeature = {"avx512", "true"}) // Strict alignment not possible. - @IR(failOn = {IRNode.LOAD_VECTOR, IRNode.ADD_V, IRNode.STORE_VECTOR}, + @IR(failOn = {IRNode.LOAD_VECTOR_L, IRNode.ADD_VL, IRNode.STORE_VECTOR}, applyIf = {"AlignVector", "true"}, applyIfCPUFeature = {"avx512", "true"}) // CPU: asimd -> vector_width: 32 -> elements in vector: 4 - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.ADD_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_L, "> 0", IRNode.ADD_VL, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIfAnd = {"AlignVector", "false", "MaxVectorSize", ">= 16"}, applyIfCPUFeature = {"asimd", "true"}) // Strict alignment not possible. - @IR(failOn = {IRNode.LOAD_VECTOR, IRNode.ADD_V, IRNode.STORE_VECTOR}, + @IR(failOn = {IRNode.LOAD_VECTOR_L, IRNode.ADD_VL, IRNode.STORE_VECTOR}, applyIf = {"AlignVector", "true"}, applyIfCPUFeature = {"asimd", "true"}) public static void testLongM1(long[] data) { @@ -2905,19 +2905,19 @@ public static void runLongP1() { @Test // CPU: sse4.1 to avx -> vector_width: 16 -> elements in vector: 2 - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.ADD_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_L, "> 0", IRNode.ADD_VL, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIfAnd = {"AlignVector", "false", "MaxVectorSize", ">= 16"}, applyIfCPUFeatureAnd = {"sse4.1", "true", "avx2", "false"}) // CPU: avx2 -> vector_width: 32 -> elements in vector: 4 - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.ADD_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_L, "> 0", IRNode.ADD_VL, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIfAnd = {"AlignVector", "false", "MaxVectorSize", ">= 16"}, applyIfCPUFeatureAnd = {"avx2", "true", "avx512", "false"}) // CPU: avx512 -> vector_width: 64 -> elements in vector: 8 - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.ADD_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_L, "> 0", IRNode.ADD_VL, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIfAnd = {"AlignVector", "false", "MaxVectorSize", ">= 16"}, applyIfCPUFeature = {"avx512", "true"}) // CPU: asimd -> vector_width: 32 -> elements in vector: 4 - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.ADD_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_L, "> 0", IRNode.ADD_VL, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIfAnd = {"AlignVector", "false", "MaxVectorSize", ">= 16"}, applyIfCPUFeature = {"asimd", "true"}) public static void testLongM2(long[] data) { @@ -2937,26 +2937,26 @@ public static void runLongM2() { @Test // CPU: sse4.1 to avx -> vector_width: 16 -> elements in vector: 2 - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.ADD_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_L, "> 0", IRNode.ADD_VL, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIfAnd = {"AlignVector", "false", "MaxVectorSize", ">= 16"}, applyIfCPUFeatureAnd = {"sse4.1", "true", "avx2", "false"}) // Vectorize when strict alignment guaranteed. - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.ADD_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_L, "> 0", IRNode.ADD_VL, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIfAnd = {"AlignVector", "true", "MaxVectorSize", ">= 16"}, applyIfCPUFeatureAnd = {"sse4.1", "true", "avx2", "false"}) // CPU: avx2 -> vector_width: 32 -> elements in vector: 4 // positive byte_offset 16 can lead to cyclic dependency - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.ADD_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_L, "> 0", IRNode.ADD_VL, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIfAnd = {"AlignVector", "false", "MaxVectorSize", ">= 16", "MaxVectorSize", "<= 16"}, applyIfCPUFeatureAnd = {"avx2", "true", "avx512", "false"}) // CPU: avx512 -> vector_width: 64 -> elements in vector: 8 // positive byte_offset 16 can lead to cyclic dependency - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.ADD_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_L, "> 0", IRNode.ADD_VL, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIfAnd = {"AlignVector", "false", "MaxVectorSize", ">= 16", "MaxVectorSize", "<= 16"}, applyIfCPUFeature = {"avx512", "true"}) // CPU: asimd -> vector_width: 32 -> elements in vector: 4 // positive byte_offset 16 can lead to cyclic dependency - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.ADD_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_L, "> 0", IRNode.ADD_VL, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIfAnd = {"AlignVector", "false", "MaxVectorSize", ">= 16", "MaxVectorSize", "<= 16"}, applyIfCPUFeature = {"asimd", "true"}) public static void testLongP2(long[] data) { @@ -2976,35 +2976,35 @@ public static void runLongP2() { @Test // CPU: sse4.1 to avx -> vector_width: 16 -> elements in vector: 2 - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.ADD_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_L, "> 0", IRNode.ADD_VL, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIfAnd = {"AlignVector", "false", "MaxVectorSize", ">= 16"}, applyIfCPUFeatureAnd = {"sse4.1", "true", "avx2", "false"}) // Strict alignment not possible. - @IR(failOn = {IRNode.LOAD_VECTOR, IRNode.ADD_V, IRNode.STORE_VECTOR}, + @IR(failOn = {IRNode.LOAD_VECTOR_L, IRNode.ADD_VL, IRNode.STORE_VECTOR}, applyIf = {"AlignVector", "true"}, applyIfCPUFeatureAnd = {"sse4.1", "true", "avx2", "false"}) // CPU: avx2 -> vector_width: 32 -> elements in vector: 4 - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.ADD_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_L, "> 0", IRNode.ADD_VL, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIfAnd = {"AlignVector", "false", "MaxVectorSize", ">= 16"}, applyIfCPUFeatureAnd = {"avx2", "true", "avx512", "false"}) // Strict alignment not possible. - @IR(failOn = {IRNode.LOAD_VECTOR, IRNode.ADD_V, IRNode.STORE_VECTOR}, + @IR(failOn = {IRNode.LOAD_VECTOR_L, IRNode.ADD_VL, IRNode.STORE_VECTOR}, applyIf = {"AlignVector", "true"}, applyIfCPUFeatureAnd = {"avx2", "true", "avx512", "false"}) // CPU: avx512 -> vector_width: 64 -> elements in vector: 8 - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.ADD_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_L, "> 0", IRNode.ADD_VL, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIfAnd = {"AlignVector", "false", "MaxVectorSize", ">= 16"}, applyIfCPUFeature = {"avx512", "true"}) // Strict alignment not possible. - @IR(failOn = {IRNode.LOAD_VECTOR, IRNode.ADD_V, IRNode.STORE_VECTOR}, + @IR(failOn = {IRNode.LOAD_VECTOR_L, IRNode.ADD_VL, IRNode.STORE_VECTOR}, applyIf = {"AlignVector", "true"}, applyIfCPUFeature = {"avx512", "true"}) // CPU: asimd -> vector_width: 32 -> elements in vector: 4 - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.ADD_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_L, "> 0", IRNode.ADD_VL, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIfAnd = {"AlignVector", "false", "MaxVectorSize", ">= 16"}, applyIfCPUFeature = {"asimd", "true"}) // Strict alignment not possible. - @IR(failOn = {IRNode.LOAD_VECTOR, IRNode.ADD_V, IRNode.STORE_VECTOR}, + @IR(failOn = {IRNode.LOAD_VECTOR_L, IRNode.ADD_VL, IRNode.STORE_VECTOR}, applyIf = {"AlignVector", "true"}, applyIfCPUFeature = {"asimd", "true"}) public static void testLongM3(long[] data) { @@ -3024,22 +3024,22 @@ public static void runLongM3() { @Test // CPU: sse4.1 to avx -> vector_width: 16 -> elements in vector: 2 - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.ADD_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_L, "> 0", IRNode.ADD_VL, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIfAnd = {"AlignVector", "false", "MaxVectorSize", ">= 16"}, applyIfCPUFeatureAnd = {"sse4.1", "true", "avx2", "false"}) // CPU: avx2 -> vector_width: 32 -> elements in vector: 4 // positive byte_offset 24 can lead to cyclic dependency - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.ADD_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_L, "> 0", IRNode.ADD_VL, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIfAnd = {"AlignVector", "false", "MaxVectorSize", ">= 16", "MaxVectorSize", "<= 24"}, applyIfCPUFeatureAnd = {"avx2", "true", "avx512", "false"}) // CPU: avx512 -> vector_width: 64 -> elements in vector: 8 // positive byte_offset 24 can lead to cyclic dependency - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.ADD_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_L, "> 0", IRNode.ADD_VL, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIfAnd = {"AlignVector", "false", "MaxVectorSize", ">= 16", "MaxVectorSize", "<= 24"}, applyIfCPUFeature = {"avx512", "true"}) // CPU: asimd -> vector_width: 32 -> elements in vector: 4 // positive byte_offset 24 can lead to cyclic dependency - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.ADD_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_L, "> 0", IRNode.ADD_VL, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIfAnd = {"AlignVector", "false", "MaxVectorSize", ">= 16", "MaxVectorSize", "<= 24"}, applyIfCPUFeature = {"asimd", "true"}) public static void testLongP3(long[] data) { @@ -3059,19 +3059,19 @@ public static void runLongP3() { @Test // CPU: sse4.1 to avx -> vector_width: 16 -> elements in vector: 2 - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.ADD_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_L, "> 0", IRNode.ADD_VL, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIfAnd = {"AlignVector", "false", "MaxVectorSize", ">= 16"}, applyIfCPUFeatureAnd = {"sse4.1", "true", "avx2", "false"}) // CPU: avx2 -> vector_width: 32 -> elements in vector: 4 - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.ADD_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_L, "> 0", IRNode.ADD_VL, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIfAnd = {"AlignVector", "false", "MaxVectorSize", ">= 16"}, applyIfCPUFeatureAnd = {"avx2", "true", "avx512", "false"}) // CPU: avx512 -> vector_width: 64 -> elements in vector: 8 - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.ADD_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_L, "> 0", IRNode.ADD_VL, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIfAnd = {"AlignVector", "false", "MaxVectorSize", ">= 16"}, applyIfCPUFeature = {"avx512", "true"}) // CPU: asimd -> vector_width: 32 -> elements in vector: 4 - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.ADD_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_L, "> 0", IRNode.ADD_VL, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIfAnd = {"AlignVector", "false", "MaxVectorSize", ">= 16"}, applyIfCPUFeature = {"asimd", "true"}) public static void testLongM4(long[] data) { @@ -3091,32 +3091,32 @@ public static void runLongM4() { @Test // CPU: sse4.1 to avx -> vector_width: 16 -> elements in vector: 2 - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.ADD_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_L, "> 0", IRNode.ADD_VL, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIfAnd = {"AlignVector", "false", "MaxVectorSize", ">= 16"}, applyIfCPUFeatureAnd = {"sse4.1", "true", "avx2", "false"}) // Vectorize when strict alignment guaranteed. - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.ADD_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_L, "> 0", IRNode.ADD_VL, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIfAnd = {"AlignVector", "true", "MaxVectorSize", ">= 16"}, applyIfCPUFeatureAnd = {"sse4.1", "true", "avx2", "false"}) // CPU: avx2 -> vector_width: 32 -> elements in vector: 4 - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.ADD_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_L, "> 0", IRNode.ADD_VL, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIfAnd = {"AlignVector", "false", "MaxVectorSize", ">= 16"}, applyIfCPUFeatureAnd = {"avx2", "true", "avx512", "false"}) // Vectorize when strict alignment guaranteed. - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.ADD_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_L, "> 0", IRNode.ADD_VL, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIfAnd = {"AlignVector", "true", "MaxVectorSize", ">= 16"}, applyIfCPUFeatureAnd = {"avx2", "true", "avx512", "false"}) // CPU: avx512 -> vector_width: 64 -> elements in vector: 8 // positive byte_offset 32 can lead to cyclic dependency - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.ADD_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_L, "> 0", IRNode.ADD_VL, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIfAnd = {"AlignVector", "false", "MaxVectorSize", ">= 16", "MaxVectorSize", "<= 32"}, applyIfCPUFeature = {"avx512", "true"}) // CPU: asimd -> vector_width: 32 -> elements in vector: 4 - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.ADD_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_L, "> 0", IRNode.ADD_VL, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIfAnd = {"AlignVector", "false", "MaxVectorSize", ">= 16"}, applyIfCPUFeature = {"asimd", "true"}) // Vectorize when strict alignment guaranteed. - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.ADD_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_L, "> 0", IRNode.ADD_VL, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIfAnd = {"AlignVector", "true", "MaxVectorSize", ">= 16"}, applyIfCPUFeature = {"asimd", "true"}) public static void testLongP4(long[] data) { @@ -3136,35 +3136,35 @@ public static void runLongP4() { @Test // CPU: sse4.1 to avx -> vector_width: 16 -> elements in vector: 2 - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.ADD_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_L, "> 0", IRNode.ADD_VL, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIfAnd = {"AlignVector", "false", "MaxVectorSize", ">= 16"}, applyIfCPUFeatureAnd = {"sse4.1", "true", "avx2", "false"}) // Strict alignment not possible. - @IR(failOn = {IRNode.LOAD_VECTOR, IRNode.ADD_V, IRNode.STORE_VECTOR}, + @IR(failOn = {IRNode.LOAD_VECTOR_L, IRNode.ADD_VL, IRNode.STORE_VECTOR}, applyIf = {"AlignVector", "true"}, applyIfCPUFeatureAnd = {"sse4.1", "true", "avx2", "false"}) // CPU: avx2 -> vector_width: 32 -> elements in vector: 4 - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.ADD_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_L, "> 0", IRNode.ADD_VL, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIfAnd = {"AlignVector", "false", "MaxVectorSize", ">= 16"}, applyIfCPUFeatureAnd = {"avx2", "true", "avx512", "false"}) // Strict alignment not possible. - @IR(failOn = {IRNode.LOAD_VECTOR, IRNode.ADD_V, IRNode.STORE_VECTOR}, + @IR(failOn = {IRNode.LOAD_VECTOR_L, IRNode.ADD_VL, IRNode.STORE_VECTOR}, applyIf = {"AlignVector", "true"}, applyIfCPUFeatureAnd = {"avx2", "true", "avx512", "false"}) // CPU: avx512 -> vector_width: 64 -> elements in vector: 8 - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.ADD_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_L, "> 0", IRNode.ADD_VL, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIfAnd = {"AlignVector", "false", "MaxVectorSize", ">= 16"}, applyIfCPUFeature = {"avx512", "true"}) // Strict alignment not possible. - @IR(failOn = {IRNode.LOAD_VECTOR, IRNode.ADD_V, IRNode.STORE_VECTOR}, + @IR(failOn = {IRNode.LOAD_VECTOR_L, IRNode.ADD_VL, IRNode.STORE_VECTOR}, applyIf = {"AlignVector", "true"}, applyIfCPUFeature = {"avx512", "true"}) // CPU: asimd -> vector_width: 32 -> elements in vector: 4 - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.ADD_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_L, "> 0", IRNode.ADD_VL, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIfAnd = {"AlignVector", "false", "MaxVectorSize", ">= 16"}, applyIfCPUFeature = {"asimd", "true"}) // Strict alignment not possible. - @IR(failOn = {IRNode.LOAD_VECTOR, IRNode.ADD_V, IRNode.STORE_VECTOR}, + @IR(failOn = {IRNode.LOAD_VECTOR_L, IRNode.ADD_VL, IRNode.STORE_VECTOR}, applyIf = {"AlignVector", "true"}, applyIfCPUFeature = {"asimd", "true"}) public static void testLongM7(long[] data) { @@ -3184,20 +3184,20 @@ public static void runLongM7() { @Test // CPU: sse4.1 to avx -> vector_width: 16 -> elements in vector: 2 - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.ADD_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_L, "> 0", IRNode.ADD_VL, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIfAnd = {"AlignVector", "false", "MaxVectorSize", ">= 16"}, applyIfCPUFeatureAnd = {"sse4.1", "true", "avx2", "false"}) // CPU: avx2 -> vector_width: 32 -> elements in vector: 4 - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.ADD_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_L, "> 0", IRNode.ADD_VL, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIfAnd = {"AlignVector", "false", "MaxVectorSize", ">= 16"}, applyIfCPUFeatureAnd = {"avx2", "true", "avx512", "false"}) // CPU: avx512 -> vector_width: 64 -> elements in vector: 8 // positive byte_offset 56 can lead to cyclic dependency - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.ADD_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_L, "> 0", IRNode.ADD_VL, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIfAnd = {"AlignVector", "false", "MaxVectorSize", ">= 16", "MaxVectorSize", "<= 56"}, applyIfCPUFeature = {"avx512", "true"}) // CPU: asimd -> vector_width: 32 -> elements in vector: 4 - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.ADD_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_L, "> 0", IRNode.ADD_VL, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIfAnd = {"AlignVector", "false", "MaxVectorSize", ">= 16"}, applyIfCPUFeature = {"asimd", "true"}) public static void testLongP7(long[] data) { @@ -3217,19 +3217,19 @@ public static void runLongP7() { @Test // CPU: sse4.1 to avx -> vector_width: 16 -> elements in vector: 2 - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.ADD_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_L, "> 0", IRNode.ADD_VL, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIfAnd = {"AlignVector", "false", "MaxVectorSize", ">= 16"}, applyIfCPUFeatureAnd = {"sse4.1", "true", "avx2", "false"}) // CPU: avx2 -> vector_width: 32 -> elements in vector: 4 - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.ADD_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_L, "> 0", IRNode.ADD_VL, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIfAnd = {"AlignVector", "false", "MaxVectorSize", ">= 16"}, applyIfCPUFeatureAnd = {"avx2", "true", "avx512", "false"}) // CPU: avx512 -> vector_width: 64 -> elements in vector: 8 - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.ADD_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_L, "> 0", IRNode.ADD_VL, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIfAnd = {"AlignVector", "false", "MaxVectorSize", ">= 16"}, applyIfCPUFeature = {"avx512", "true"}) // CPU: asimd -> vector_width: 32 -> elements in vector: 4 - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.ADD_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_L, "> 0", IRNode.ADD_VL, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIfAnd = {"AlignVector", "false", "MaxVectorSize", ">= 16"}, applyIfCPUFeature = {"asimd", "true"}) public static void testLongM8(long[] data) { @@ -3249,35 +3249,35 @@ public static void runLongM8() { @Test // CPU: sse4.1 to avx -> vector_width: 16 -> elements in vector: 2 - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.ADD_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_L, "> 0", IRNode.ADD_VL, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIfAnd = {"AlignVector", "false", "MaxVectorSize", ">= 16"}, applyIfCPUFeatureAnd = {"sse4.1", "true", "avx2", "false"}) // Vectorize when strict alignment guaranteed. - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.ADD_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_L, "> 0", IRNode.ADD_VL, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIfAnd = {"AlignVector", "true", "MaxVectorSize", ">= 16"}, applyIfCPUFeatureAnd = {"sse4.1", "true", "avx2", "false"}) // CPU: avx2 -> vector_width: 32 -> elements in vector: 4 - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.ADD_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_L, "> 0", IRNode.ADD_VL, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIfAnd = {"AlignVector", "false", "MaxVectorSize", ">= 16"}, applyIfCPUFeatureAnd = {"avx2", "true", "avx512", "false"}) // Vectorize when strict alignment guaranteed. - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.ADD_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_L, "> 0", IRNode.ADD_VL, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIfAnd = {"AlignVector", "true", "MaxVectorSize", ">= 16"}, applyIfCPUFeatureAnd = {"avx2", "true", "avx512", "false"}) // CPU: avx512 -> vector_width: 64 -> elements in vector: 8 - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.ADD_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_L, "> 0", IRNode.ADD_VL, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIfAnd = {"AlignVector", "false", "MaxVectorSize", ">= 16"}, applyIfCPUFeature = {"avx512", "true"}) // Vectorize when strict alignment guaranteed. - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.ADD_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_L, "> 0", IRNode.ADD_VL, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIfAnd = {"AlignVector", "true", "MaxVectorSize", ">= 16"}, applyIfCPUFeature = {"avx512", "true"}) // CPU: asimd -> vector_width: 32 -> elements in vector: 4 - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.ADD_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_L, "> 0", IRNode.ADD_VL, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIfAnd = {"AlignVector", "false", "MaxVectorSize", ">= 16"}, applyIfCPUFeature = {"asimd", "true"}) // Vectorize when strict alignment guaranteed. - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.ADD_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_L, "> 0", IRNode.ADD_VL, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIfAnd = {"AlignVector", "true", "MaxVectorSize", ">= 16"}, applyIfCPUFeature = {"asimd", "true"}) public static void testLongP8(long[] data) { @@ -3297,19 +3297,19 @@ public static void runLongP8() { @Test // CPU: sse4.1 to avx -> vector_width: 16 -> elements in vector: 2 - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.ADD_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_L, "> 0", IRNode.ADD_VL, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIfAnd = {"AlignVector", "false", "MaxVectorSize", ">= 16"}, applyIfCPUFeatureAnd = {"sse4.1", "true", "avx2", "false"}) // CPU: avx2 -> vector_width: 32 -> elements in vector: 4 - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.ADD_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_L, "> 0", IRNode.ADD_VL, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIfAnd = {"AlignVector", "false", "MaxVectorSize", ">= 16"}, applyIfCPUFeatureAnd = {"avx2", "true", "avx512", "false"}) // CPU: avx512 -> vector_width: 64 -> elements in vector: 8 - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.ADD_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_L, "> 0", IRNode.ADD_VL, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIfAnd = {"AlignVector", "false", "MaxVectorSize", ">= 16"}, applyIfCPUFeature = {"avx512", "true"}) // CPU: asimd -> vector_width: 32 -> elements in vector: 4 - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.ADD_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_L, "> 0", IRNode.ADD_VL, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIfAnd = {"AlignVector", "false", "MaxVectorSize", ">= 16"}, applyIfCPUFeature = {"asimd", "true"}) public static void testLongM14(long[] data) { @@ -3329,23 +3329,23 @@ public static void runLongM14() { @Test // CPU: sse4.1 to avx -> vector_width: 16 -> elements in vector: 2 - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.ADD_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_L, "> 0", IRNode.ADD_VL, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIfAnd = {"AlignVector", "false", "MaxVectorSize", ">= 16"}, applyIfCPUFeatureAnd = {"sse4.1", "true", "avx2", "false"}) // Vectorize when strict alignment guaranteed. - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.ADD_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_L, "> 0", IRNode.ADD_VL, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIfAnd = {"AlignVector", "true", "MaxVectorSize", ">= 16"}, applyIfCPUFeatureAnd = {"sse4.1", "true", "avx2", "false"}) // CPU: avx2 -> vector_width: 32 -> elements in vector: 4 - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.ADD_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_L, "> 0", IRNode.ADD_VL, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIfAnd = {"AlignVector", "false", "MaxVectorSize", ">= 16"}, applyIfCPUFeatureAnd = {"avx2", "true", "avx512", "false"}) // CPU: avx512 -> vector_width: 64 -> elements in vector: 8 - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.ADD_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_L, "> 0", IRNode.ADD_VL, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIfAnd = {"AlignVector", "false", "MaxVectorSize", ">= 16"}, applyIfCPUFeature = {"avx512", "true"}) // CPU: asimd -> vector_width: 32 -> elements in vector: 4 - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.ADD_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_L, "> 0", IRNode.ADD_VL, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIfAnd = {"AlignVector", "false", "MaxVectorSize", ">= 16"}, applyIfCPUFeature = {"asimd", "true"}) public static void testLongP14(long[] data) { @@ -3365,19 +3365,19 @@ public static void runLongP14() { @Test // CPU: sse4.1 to avx -> vector_width: 16 -> elements in vector: 2 - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.ADD_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_L, "> 0", IRNode.ADD_VL, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIfAnd = {"AlignVector", "false", "MaxVectorSize", ">= 16"}, applyIfCPUFeatureAnd = {"sse4.1", "true", "avx2", "false"}) // CPU: avx2 -> vector_width: 32 -> elements in vector: 4 - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.ADD_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_L, "> 0", IRNode.ADD_VL, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIfAnd = {"AlignVector", "false", "MaxVectorSize", ">= 16"}, applyIfCPUFeatureAnd = {"avx2", "true", "avx512", "false"}) // CPU: avx512 -> vector_width: 64 -> elements in vector: 8 - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.ADD_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_L, "> 0", IRNode.ADD_VL, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIfAnd = {"AlignVector", "false", "MaxVectorSize", ">= 16"}, applyIfCPUFeature = {"avx512", "true"}) // CPU: asimd -> vector_width: 32 -> elements in vector: 4 - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.ADD_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_L, "> 0", IRNode.ADD_VL, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIfAnd = {"AlignVector", "false", "MaxVectorSize", ">= 16"}, applyIfCPUFeature = {"asimd", "true"}) public static void testLongM16(long[] data) { @@ -3397,35 +3397,35 @@ public static void runLongM16() { @Test // CPU: sse4.1 to avx -> vector_width: 16 -> elements in vector: 2 - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.ADD_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_L, "> 0", IRNode.ADD_VL, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIfAnd = {"AlignVector", "false", "MaxVectorSize", ">= 16"}, applyIfCPUFeatureAnd = {"sse4.1", "true", "avx2", "false"}) // Vectorize when strict alignment guaranteed. - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.ADD_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_L, "> 0", IRNode.ADD_VL, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIfAnd = {"AlignVector", "true", "MaxVectorSize", ">= 16"}, applyIfCPUFeatureAnd = {"sse4.1", "true", "avx2", "false"}) // CPU: avx2 -> vector_width: 32 -> elements in vector: 4 - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.ADD_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_L, "> 0", IRNode.ADD_VL, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIfAnd = {"AlignVector", "false", "MaxVectorSize", ">= 16"}, applyIfCPUFeatureAnd = {"avx2", "true", "avx512", "false"}) // Vectorize when strict alignment guaranteed. - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.ADD_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_L, "> 0", IRNode.ADD_VL, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIfAnd = {"AlignVector", "true", "MaxVectorSize", ">= 16"}, applyIfCPUFeatureAnd = {"avx2", "true", "avx512", "false"}) // CPU: avx512 -> vector_width: 64 -> elements in vector: 8 - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.ADD_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_L, "> 0", IRNode.ADD_VL, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIfAnd = {"AlignVector", "false", "MaxVectorSize", ">= 16"}, applyIfCPUFeature = {"avx512", "true"}) // Vectorize when strict alignment guaranteed. - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.ADD_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_L, "> 0", IRNode.ADD_VL, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIfAnd = {"AlignVector", "true", "MaxVectorSize", ">= 16"}, applyIfCPUFeature = {"avx512", "true"}) // CPU: asimd -> vector_width: 32 -> elements in vector: 4 - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.ADD_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_L, "> 0", IRNode.ADD_VL, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIfAnd = {"AlignVector", "false", "MaxVectorSize", ">= 16"}, applyIfCPUFeature = {"asimd", "true"}) // Vectorize when strict alignment guaranteed. - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.ADD_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_L, "> 0", IRNode.ADD_VL, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIfAnd = {"AlignVector", "true", "MaxVectorSize", ">= 16"}, applyIfCPUFeature = {"asimd", "true"}) public static void testLongP16(long[] data) { @@ -3445,19 +3445,19 @@ public static void runLongP16() { @Test // CPU: sse4.1 to avx -> vector_width: 16 -> elements in vector: 2 - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.ADD_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_L, "> 0", IRNode.ADD_VL, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIfAnd = {"AlignVector", "false", "MaxVectorSize", ">= 16"}, applyIfCPUFeatureAnd = {"sse4.1", "true", "avx2", "false"}) // CPU: avx2 -> vector_width: 32 -> elements in vector: 4 - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.ADD_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_L, "> 0", IRNode.ADD_VL, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIfAnd = {"AlignVector", "false", "MaxVectorSize", ">= 16"}, applyIfCPUFeatureAnd = {"avx2", "true", "avx512", "false"}) // CPU: avx512 -> vector_width: 64 -> elements in vector: 8 - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.ADD_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_L, "> 0", IRNode.ADD_VL, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIfAnd = {"AlignVector", "false", "MaxVectorSize", ">= 16"}, applyIfCPUFeature = {"avx512", "true"}) // CPU: asimd -> vector_width: 32 -> elements in vector: 4 - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.ADD_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_L, "> 0", IRNode.ADD_VL, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIfAnd = {"AlignVector", "false", "MaxVectorSize", ">= 16"}, applyIfCPUFeature = {"asimd", "true"}) public static void testLongM18(long[] data) { @@ -3477,23 +3477,23 @@ public static void runLongM18() { @Test // CPU: sse4.1 to avx -> vector_width: 16 -> elements in vector: 2 - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.ADD_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_L, "> 0", IRNode.ADD_VL, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIfAnd = {"AlignVector", "false", "MaxVectorSize", ">= 16"}, applyIfCPUFeatureAnd = {"sse4.1", "true", "avx2", "false"}) // Vectorize when strict alignment guaranteed. - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.ADD_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_L, "> 0", IRNode.ADD_VL, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIfAnd = {"AlignVector", "true", "MaxVectorSize", ">= 16"}, applyIfCPUFeatureAnd = {"sse4.1", "true", "avx2", "false"}) // CPU: avx2 -> vector_width: 32 -> elements in vector: 4 - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.ADD_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_L, "> 0", IRNode.ADD_VL, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIfAnd = {"AlignVector", "false", "MaxVectorSize", ">= 16"}, applyIfCPUFeatureAnd = {"avx2", "true", "avx512", "false"}) // CPU: avx512 -> vector_width: 64 -> elements in vector: 8 - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.ADD_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_L, "> 0", IRNode.ADD_VL, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIfAnd = {"AlignVector", "false", "MaxVectorSize", ">= 16"}, applyIfCPUFeature = {"avx512", "true"}) // CPU: asimd -> vector_width: 32 -> elements in vector: 4 - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.ADD_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_L, "> 0", IRNode.ADD_VL, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIfAnd = {"AlignVector", "false", "MaxVectorSize", ">= 16"}, applyIfCPUFeature = {"asimd", "true"}) public static void testLongP18(long[] data) { @@ -3513,19 +3513,19 @@ public static void runLongP18() { @Test // CPU: sse4.1 to avx -> vector_width: 16 -> elements in vector: 2 - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.ADD_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_L, "> 0", IRNode.ADD_VL, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIfAnd = {"AlignVector", "false", "MaxVectorSize", ">= 16"}, applyIfCPUFeatureAnd = {"sse4.1", "true", "avx2", "false"}) // CPU: avx2 -> vector_width: 32 -> elements in vector: 4 - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.ADD_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_L, "> 0", IRNode.ADD_VL, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIfAnd = {"AlignVector", "false", "MaxVectorSize", ">= 16"}, applyIfCPUFeatureAnd = {"avx2", "true", "avx512", "false"}) // CPU: avx512 -> vector_width: 64 -> elements in vector: 8 - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.ADD_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_L, "> 0", IRNode.ADD_VL, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIfAnd = {"AlignVector", "false", "MaxVectorSize", ">= 16"}, applyIfCPUFeature = {"avx512", "true"}) // CPU: asimd -> vector_width: 32 -> elements in vector: 4 - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.ADD_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_L, "> 0", IRNode.ADD_VL, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIfAnd = {"AlignVector", "false", "MaxVectorSize", ">= 16"}, applyIfCPUFeature = {"asimd", "true"}) public static void testLongM20(long[] data) { @@ -3545,31 +3545,31 @@ public static void runLongM20() { @Test // CPU: sse4.1 to avx -> vector_width: 16 -> elements in vector: 2 - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.ADD_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_L, "> 0", IRNode.ADD_VL, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIfAnd = {"AlignVector", "false", "MaxVectorSize", ">= 16"}, applyIfCPUFeatureAnd = {"sse4.1", "true", "avx2", "false"}) // Vectorize when strict alignment guaranteed. - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.ADD_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_L, "> 0", IRNode.ADD_VL, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIfAnd = {"AlignVector", "true", "MaxVectorSize", ">= 16"}, applyIfCPUFeatureAnd = {"sse4.1", "true", "avx2", "false"}) // CPU: avx2 -> vector_width: 32 -> elements in vector: 4 - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.ADD_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_L, "> 0", IRNode.ADD_VL, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIfAnd = {"AlignVector", "false", "MaxVectorSize", ">= 16"}, applyIfCPUFeatureAnd = {"avx2", "true", "avx512", "false"}) // Vectorize when strict alignment guaranteed. - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.ADD_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_L, "> 0", IRNode.ADD_VL, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIfAnd = {"AlignVector", "true", "MaxVectorSize", ">= 16"}, applyIfCPUFeatureAnd = {"avx2", "true", "avx512", "false"}) // CPU: avx512 -> vector_width: 64 -> elements in vector: 8 - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.ADD_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_L, "> 0", IRNode.ADD_VL, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIfAnd = {"AlignVector", "false", "MaxVectorSize", ">= 16"}, applyIfCPUFeature = {"avx512", "true"}) // CPU: asimd -> vector_width: 32 -> elements in vector: 4 - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.ADD_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_L, "> 0", IRNode.ADD_VL, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIfAnd = {"AlignVector", "false", "MaxVectorSize", ">= 16"}, applyIfCPUFeature = {"asimd", "true"}) // Vectorize when strict alignment guaranteed. - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.ADD_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_L, "> 0", IRNode.ADD_VL, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIfAnd = {"AlignVector", "true", "MaxVectorSize", ">= 16"}, applyIfCPUFeature = {"asimd", "true"}) public static void testLongP20(long[] data) { @@ -3589,35 +3589,35 @@ public static void runLongP20() { @Test // CPU: sse4.1 to avx -> vector_width: 16 -> elements in vector: 2 - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.ADD_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_L, "> 0", IRNode.ADD_VL, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIfAnd = {"AlignVector", "false", "MaxVectorSize", ">= 16"}, applyIfCPUFeatureAnd = {"sse4.1", "true", "avx2", "false"}) // Strict alignment not possible. - @IR(failOn = {IRNode.LOAD_VECTOR, IRNode.ADD_V, IRNode.STORE_VECTOR}, + @IR(failOn = {IRNode.LOAD_VECTOR_L, IRNode.ADD_VL, IRNode.STORE_VECTOR}, applyIf = {"AlignVector", "true"}, applyIfCPUFeatureAnd = {"sse4.1", "true", "avx2", "false"}) // CPU: avx2 -> vector_width: 32 -> elements in vector: 4 - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.ADD_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_L, "> 0", IRNode.ADD_VL, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIfAnd = {"AlignVector", "false", "MaxVectorSize", ">= 16"}, applyIfCPUFeatureAnd = {"avx2", "true", "avx512", "false"}) // Strict alignment not possible. - @IR(failOn = {IRNode.LOAD_VECTOR, IRNode.ADD_V, IRNode.STORE_VECTOR}, + @IR(failOn = {IRNode.LOAD_VECTOR_L, IRNode.ADD_VL, IRNode.STORE_VECTOR}, applyIf = {"AlignVector", "true"}, applyIfCPUFeatureAnd = {"avx2", "true", "avx512", "false"}) // CPU: avx512 -> vector_width: 64 -> elements in vector: 8 - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.ADD_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_L, "> 0", IRNode.ADD_VL, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIfAnd = {"AlignVector", "false", "MaxVectorSize", ">= 16"}, applyIfCPUFeature = {"avx512", "true"}) // Strict alignment not possible. - @IR(failOn = {IRNode.LOAD_VECTOR, IRNode.ADD_V, IRNode.STORE_VECTOR}, + @IR(failOn = {IRNode.LOAD_VECTOR_L, IRNode.ADD_VL, IRNode.STORE_VECTOR}, applyIf = {"AlignVector", "true"}, applyIfCPUFeature = {"avx512", "true"}) // CPU: asimd -> vector_width: 32 -> elements in vector: 4 - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.ADD_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_L, "> 0", IRNode.ADD_VL, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIfAnd = {"AlignVector", "false", "MaxVectorSize", ">= 16"}, applyIfCPUFeature = {"asimd", "true"}) // Strict alignment not possible. - @IR(failOn = {IRNode.LOAD_VECTOR, IRNode.ADD_V, IRNode.STORE_VECTOR}, + @IR(failOn = {IRNode.LOAD_VECTOR_L, IRNode.ADD_VL, IRNode.STORE_VECTOR}, applyIf = {"AlignVector", "true"}, applyIfCPUFeature = {"asimd", "true"}) public static void testLongM31(long[] data) { @@ -3637,19 +3637,19 @@ public static void runLongM31() { @Test // CPU: sse4.1 to avx -> vector_width: 16 -> elements in vector: 2 - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.ADD_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_L, "> 0", IRNode.ADD_VL, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIfAnd = {"AlignVector", "false", "MaxVectorSize", ">= 16"}, applyIfCPUFeatureAnd = {"sse4.1", "true", "avx2", "false"}) // CPU: avx2 -> vector_width: 32 -> elements in vector: 4 - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.ADD_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_L, "> 0", IRNode.ADD_VL, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIfAnd = {"AlignVector", "false", "MaxVectorSize", ">= 16"}, applyIfCPUFeatureAnd = {"avx2", "true", "avx512", "false"}) // CPU: avx512 -> vector_width: 64 -> elements in vector: 8 - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.ADD_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_L, "> 0", IRNode.ADD_VL, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIfAnd = {"AlignVector", "false", "MaxVectorSize", ">= 16"}, applyIfCPUFeature = {"avx512", "true"}) // CPU: asimd -> vector_width: 32 -> elements in vector: 4 - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.ADD_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_L, "> 0", IRNode.ADD_VL, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIfAnd = {"AlignVector", "false", "MaxVectorSize", ">= 16"}, applyIfCPUFeature = {"asimd", "true"}) public static void testLongP31(long[] data) { @@ -3669,19 +3669,19 @@ public static void runLongP31() { @Test // CPU: sse4.1 to avx -> vector_width: 16 -> elements in vector: 2 - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.ADD_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_L, "> 0", IRNode.ADD_VL, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIfAnd = {"AlignVector", "false", "MaxVectorSize", ">= 16"}, applyIfCPUFeatureAnd = {"sse4.1", "true", "avx2", "false"}) // CPU: avx2 -> vector_width: 32 -> elements in vector: 4 - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.ADD_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_L, "> 0", IRNode.ADD_VL, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIfAnd = {"AlignVector", "false", "MaxVectorSize", ">= 16"}, applyIfCPUFeatureAnd = {"avx2", "true", "avx512", "false"}) // CPU: avx512 -> vector_width: 64 -> elements in vector: 8 - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.ADD_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_L, "> 0", IRNode.ADD_VL, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIfAnd = {"AlignVector", "false", "MaxVectorSize", ">= 16"}, applyIfCPUFeature = {"avx512", "true"}) // CPU: asimd -> vector_width: 32 -> elements in vector: 4 - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.ADD_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_L, "> 0", IRNode.ADD_VL, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIfAnd = {"AlignVector", "false", "MaxVectorSize", ">= 16"}, applyIfCPUFeature = {"asimd", "true"}) public static void testLongM32(long[] data) { @@ -3701,35 +3701,35 @@ public static void runLongM32() { @Test // CPU: sse4.1 to avx -> vector_width: 16 -> elements in vector: 2 - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.ADD_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_L, "> 0", IRNode.ADD_VL, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIfAnd = {"AlignVector", "false", "MaxVectorSize", ">= 16"}, applyIfCPUFeatureAnd = {"sse4.1", "true", "avx2", "false"}) // Vectorize when strict alignment guaranteed. - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.ADD_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_L, "> 0", IRNode.ADD_VL, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIfAnd = {"AlignVector", "true", "MaxVectorSize", ">= 16"}, applyIfCPUFeatureAnd = {"sse4.1", "true", "avx2", "false"}) // CPU: avx2 -> vector_width: 32 -> elements in vector: 4 - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.ADD_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_L, "> 0", IRNode.ADD_VL, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIfAnd = {"AlignVector", "false", "MaxVectorSize", ">= 16"}, applyIfCPUFeatureAnd = {"avx2", "true", "avx512", "false"}) // Vectorize when strict alignment guaranteed. - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.ADD_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_L, "> 0", IRNode.ADD_VL, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIfAnd = {"AlignVector", "true", "MaxVectorSize", ">= 16"}, applyIfCPUFeatureAnd = {"avx2", "true", "avx512", "false"}) // CPU: avx512 -> vector_width: 64 -> elements in vector: 8 - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.ADD_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_L, "> 0", IRNode.ADD_VL, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIfAnd = {"AlignVector", "false", "MaxVectorSize", ">= 16"}, applyIfCPUFeature = {"avx512", "true"}) // Vectorize when strict alignment guaranteed. - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.ADD_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_L, "> 0", IRNode.ADD_VL, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIfAnd = {"AlignVector", "true", "MaxVectorSize", ">= 16"}, applyIfCPUFeature = {"avx512", "true"}) // CPU: asimd -> vector_width: 32 -> elements in vector: 4 - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.ADD_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_L, "> 0", IRNode.ADD_VL, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIfAnd = {"AlignVector", "false", "MaxVectorSize", ">= 16"}, applyIfCPUFeature = {"asimd", "true"}) // Vectorize when strict alignment guaranteed. - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.ADD_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_L, "> 0", IRNode.ADD_VL, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIfAnd = {"AlignVector", "true", "MaxVectorSize", ">= 16"}, applyIfCPUFeature = {"asimd", "true"}) public static void testLongP32(long[] data) { @@ -3749,35 +3749,35 @@ public static void runLongP32() { @Test // CPU: sse4.1 to avx -> vector_width: 16 -> elements in vector: 2 - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.ADD_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_L, "> 0", IRNode.ADD_VL, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIfAnd = {"AlignVector", "false", "MaxVectorSize", ">= 16"}, applyIfCPUFeatureAnd = {"sse4.1", "true", "avx2", "false"}) // Strict alignment not possible. - @IR(failOn = {IRNode.LOAD_VECTOR, IRNode.ADD_V, IRNode.STORE_VECTOR}, + @IR(failOn = {IRNode.LOAD_VECTOR_L, IRNode.ADD_VL, IRNode.STORE_VECTOR}, applyIf = {"AlignVector", "true"}, applyIfCPUFeatureAnd = {"sse4.1", "true", "avx2", "false"}) // CPU: avx2 -> vector_width: 32 -> elements in vector: 4 - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.ADD_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_L, "> 0", IRNode.ADD_VL, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIfAnd = {"AlignVector", "false", "MaxVectorSize", ">= 16"}, applyIfCPUFeatureAnd = {"avx2", "true", "avx512", "false"}) // Strict alignment not possible. - @IR(failOn = {IRNode.LOAD_VECTOR, IRNode.ADD_V, IRNode.STORE_VECTOR}, + @IR(failOn = {IRNode.LOAD_VECTOR_L, IRNode.ADD_VL, IRNode.STORE_VECTOR}, applyIf = {"AlignVector", "true"}, applyIfCPUFeatureAnd = {"avx2", "true", "avx512", "false"}) // CPU: avx512 -> vector_width: 64 -> elements in vector: 8 - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.ADD_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_L, "> 0", IRNode.ADD_VL, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIfAnd = {"AlignVector", "false", "MaxVectorSize", ">= 16"}, applyIfCPUFeature = {"avx512", "true"}) // Strict alignment not possible. - @IR(failOn = {IRNode.LOAD_VECTOR, IRNode.ADD_V, IRNode.STORE_VECTOR}, + @IR(failOn = {IRNode.LOAD_VECTOR_L, IRNode.ADD_VL, IRNode.STORE_VECTOR}, applyIf = {"AlignVector", "true"}, applyIfCPUFeature = {"avx512", "true"}) // CPU: asimd -> vector_width: 32 -> elements in vector: 4 - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.ADD_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_L, "> 0", IRNode.ADD_VL, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIfAnd = {"AlignVector", "false", "MaxVectorSize", ">= 16"}, applyIfCPUFeature = {"asimd", "true"}) // Strict alignment not possible. - @IR(failOn = {IRNode.LOAD_VECTOR, IRNode.ADD_V, IRNode.STORE_VECTOR}, + @IR(failOn = {IRNode.LOAD_VECTOR_L, IRNode.ADD_VL, IRNode.STORE_VECTOR}, applyIf = {"AlignVector", "true"}, applyIfCPUFeature = {"asimd", "true"}) public static void testLongM63(long[] data) { @@ -3797,19 +3797,19 @@ public static void runLongM63() { @Test // CPU: sse4.1 to avx -> vector_width: 16 -> elements in vector: 2 - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.ADD_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_L, "> 0", IRNode.ADD_VL, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIfAnd = {"AlignVector", "false", "MaxVectorSize", ">= 16"}, applyIfCPUFeatureAnd = {"sse4.1", "true", "avx2", "false"}) // CPU: avx2 -> vector_width: 32 -> elements in vector: 4 - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.ADD_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_L, "> 0", IRNode.ADD_VL, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIfAnd = {"AlignVector", "false", "MaxVectorSize", ">= 16"}, applyIfCPUFeatureAnd = {"avx2", "true", "avx512", "false"}) // CPU: avx512 -> vector_width: 64 -> elements in vector: 8 - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.ADD_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_L, "> 0", IRNode.ADD_VL, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIfAnd = {"AlignVector", "false", "MaxVectorSize", ">= 16"}, applyIfCPUFeature = {"avx512", "true"}) // CPU: asimd -> vector_width: 32 -> elements in vector: 4 - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.ADD_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_L, "> 0", IRNode.ADD_VL, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIfAnd = {"AlignVector", "false", "MaxVectorSize", ">= 16"}, applyIfCPUFeature = {"asimd", "true"}) public static void testLongP63(long[] data) { @@ -3829,19 +3829,19 @@ public static void runLongP63() { @Test // CPU: sse4.1 to avx -> vector_width: 16 -> elements in vector: 2 - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.ADD_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_L, "> 0", IRNode.ADD_VL, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIfAnd = {"AlignVector", "false", "MaxVectorSize", ">= 16"}, applyIfCPUFeatureAnd = {"sse4.1", "true", "avx2", "false"}) // CPU: avx2 -> vector_width: 32 -> elements in vector: 4 - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.ADD_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_L, "> 0", IRNode.ADD_VL, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIfAnd = {"AlignVector", "false", "MaxVectorSize", ">= 16"}, applyIfCPUFeatureAnd = {"avx2", "true", "avx512", "false"}) // CPU: avx512 -> vector_width: 64 -> elements in vector: 8 - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.ADD_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_L, "> 0", IRNode.ADD_VL, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIfAnd = {"AlignVector", "false", "MaxVectorSize", ">= 16"}, applyIfCPUFeature = {"avx512", "true"}) // CPU: asimd -> vector_width: 32 -> elements in vector: 4 - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.ADD_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_L, "> 0", IRNode.ADD_VL, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIfAnd = {"AlignVector", "false", "MaxVectorSize", ">= 16"}, applyIfCPUFeature = {"asimd", "true"}) public static void testLongM64(long[] data) { @@ -3861,35 +3861,35 @@ public static void runLongM64() { @Test // CPU: sse4.1 to avx -> vector_width: 16 -> elements in vector: 2 - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.ADD_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_L, "> 0", IRNode.ADD_VL, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIfAnd = {"AlignVector", "false", "MaxVectorSize", ">= 16"}, applyIfCPUFeatureAnd = {"sse4.1", "true", "avx2", "false"}) // Vectorize when strict alignment guaranteed. - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.ADD_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_L, "> 0", IRNode.ADD_VL, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIfAnd = {"AlignVector", "true", "MaxVectorSize", ">= 16"}, applyIfCPUFeatureAnd = {"sse4.1", "true", "avx2", "false"}) // CPU: avx2 -> vector_width: 32 -> elements in vector: 4 - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.ADD_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_L, "> 0", IRNode.ADD_VL, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIfAnd = {"AlignVector", "false", "MaxVectorSize", ">= 16"}, applyIfCPUFeatureAnd = {"avx2", "true", "avx512", "false"}) // Vectorize when strict alignment guaranteed. - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.ADD_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_L, "> 0", IRNode.ADD_VL, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIfAnd = {"AlignVector", "true", "MaxVectorSize", ">= 16"}, applyIfCPUFeatureAnd = {"avx2", "true", "avx512", "false"}) // CPU: avx512 -> vector_width: 64 -> elements in vector: 8 - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.ADD_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_L, "> 0", IRNode.ADD_VL, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIfAnd = {"AlignVector", "false", "MaxVectorSize", ">= 16"}, applyIfCPUFeature = {"avx512", "true"}) // Vectorize when strict alignment guaranteed. - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.ADD_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_L, "> 0", IRNode.ADD_VL, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIfAnd = {"AlignVector", "true", "MaxVectorSize", ">= 16"}, applyIfCPUFeature = {"avx512", "true"}) // CPU: asimd -> vector_width: 32 -> elements in vector: 4 - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.ADD_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_L, "> 0", IRNode.ADD_VL, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIfAnd = {"AlignVector", "false", "MaxVectorSize", ">= 16"}, applyIfCPUFeature = {"asimd", "true"}) // Vectorize when strict alignment guaranteed. - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.ADD_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_L, "> 0", IRNode.ADD_VL, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIfAnd = {"AlignVector", "true", "MaxVectorSize", ">= 16"}, applyIfCPUFeature = {"asimd", "true"}) public static void testLongP64(long[] data) { @@ -3909,35 +3909,35 @@ public static void runLongP64() { @Test // CPU: sse4.1 to avx -> vector_width: 16 -> elements in vector: 2 - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.ADD_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_L, "> 0", IRNode.ADD_VL, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIfAnd = {"AlignVector", "false", "MaxVectorSize", ">= 16"}, applyIfCPUFeatureAnd = {"sse4.1", "true", "avx2", "false"}) // Strict alignment not possible. - @IR(failOn = {IRNode.LOAD_VECTOR, IRNode.ADD_V, IRNode.STORE_VECTOR}, + @IR(failOn = {IRNode.LOAD_VECTOR_L, IRNode.ADD_VL, IRNode.STORE_VECTOR}, applyIf = {"AlignVector", "true"}, applyIfCPUFeatureAnd = {"sse4.1", "true", "avx2", "false"}) // CPU: avx2 -> vector_width: 32 -> elements in vector: 4 - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.ADD_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_L, "> 0", IRNode.ADD_VL, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIfAnd = {"AlignVector", "false", "MaxVectorSize", ">= 16"}, applyIfCPUFeatureAnd = {"avx2", "true", "avx512", "false"}) // Strict alignment not possible. - @IR(failOn = {IRNode.LOAD_VECTOR, IRNode.ADD_V, IRNode.STORE_VECTOR}, + @IR(failOn = {IRNode.LOAD_VECTOR_L, IRNode.ADD_VL, IRNode.STORE_VECTOR}, applyIf = {"AlignVector", "true"}, applyIfCPUFeatureAnd = {"avx2", "true", "avx512", "false"}) // CPU: avx512 -> vector_width: 64 -> elements in vector: 8 - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.ADD_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_L, "> 0", IRNode.ADD_VL, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIfAnd = {"AlignVector", "false", "MaxVectorSize", ">= 16"}, applyIfCPUFeature = {"avx512", "true"}) // Strict alignment not possible. - @IR(failOn = {IRNode.LOAD_VECTOR, IRNode.ADD_V, IRNode.STORE_VECTOR}, + @IR(failOn = {IRNode.LOAD_VECTOR_L, IRNode.ADD_VL, IRNode.STORE_VECTOR}, applyIf = {"AlignVector", "true"}, applyIfCPUFeature = {"avx512", "true"}) // CPU: asimd -> vector_width: 32 -> elements in vector: 4 - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.ADD_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_L, "> 0", IRNode.ADD_VL, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIfAnd = {"AlignVector", "false", "MaxVectorSize", ">= 16"}, applyIfCPUFeature = {"asimd", "true"}) // Strict alignment not possible. - @IR(failOn = {IRNode.LOAD_VECTOR, IRNode.ADD_V, IRNode.STORE_VECTOR}, + @IR(failOn = {IRNode.LOAD_VECTOR_L, IRNode.ADD_VL, IRNode.STORE_VECTOR}, applyIf = {"AlignVector", "true"}, applyIfCPUFeature = {"asimd", "true"}) public static void testLongM65(long[] data) { @@ -3957,19 +3957,19 @@ public static void runLongM65() { @Test // CPU: sse4.1 to avx -> vector_width: 16 -> elements in vector: 2 - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.ADD_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_L, "> 0", IRNode.ADD_VL, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIfAnd = {"AlignVector", "false", "MaxVectorSize", ">= 16"}, applyIfCPUFeatureAnd = {"sse4.1", "true", "avx2", "false"}) // CPU: avx2 -> vector_width: 32 -> elements in vector: 4 - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.ADD_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_L, "> 0", IRNode.ADD_VL, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIfAnd = {"AlignVector", "false", "MaxVectorSize", ">= 16"}, applyIfCPUFeatureAnd = {"avx2", "true", "avx512", "false"}) // CPU: avx512 -> vector_width: 64 -> elements in vector: 8 - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.ADD_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_L, "> 0", IRNode.ADD_VL, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIfAnd = {"AlignVector", "false", "MaxVectorSize", ">= 16"}, applyIfCPUFeature = {"avx512", "true"}) // CPU: asimd -> vector_width: 32 -> elements in vector: 4 - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.ADD_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_L, "> 0", IRNode.ADD_VL, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIfAnd = {"AlignVector", "false", "MaxVectorSize", ">= 16"}, applyIfCPUFeature = {"asimd", "true"}) public static void testLongP65(long[] data) { @@ -3989,19 +3989,19 @@ public static void runLongP65() { @Test // CPU: sse4.1 to avx -> vector_width: 16 -> elements in vector: 2 - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.ADD_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_L, "> 0", IRNode.ADD_VL, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIfAnd = {"AlignVector", "false", "MaxVectorSize", ">= 16"}, applyIfCPUFeatureAnd = {"sse4.1", "true", "avx2", "false"}) // CPU: avx2 -> vector_width: 32 -> elements in vector: 4 - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.ADD_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_L, "> 0", IRNode.ADD_VL, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIfAnd = {"AlignVector", "false", "MaxVectorSize", ">= 16"}, applyIfCPUFeatureAnd = {"avx2", "true", "avx512", "false"}) // CPU: avx512 -> vector_width: 64 -> elements in vector: 8 - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.ADD_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_L, "> 0", IRNode.ADD_VL, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIfAnd = {"AlignVector", "false", "MaxVectorSize", ">= 16"}, applyIfCPUFeature = {"avx512", "true"}) // CPU: asimd -> vector_width: 32 -> elements in vector: 4 - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.ADD_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_L, "> 0", IRNode.ADD_VL, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIfAnd = {"AlignVector", "false", "MaxVectorSize", ">= 16"}, applyIfCPUFeature = {"asimd", "true"}) public static void testLongM128(long[] data) { @@ -4021,35 +4021,35 @@ public static void runLongM128() { @Test // CPU: sse4.1 to avx -> vector_width: 16 -> elements in vector: 2 - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.ADD_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_L, "> 0", IRNode.ADD_VL, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIfAnd = {"AlignVector", "false", "MaxVectorSize", ">= 16"}, applyIfCPUFeatureAnd = {"sse4.1", "true", "avx2", "false"}) // Vectorize when strict alignment guaranteed. - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.ADD_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_L, "> 0", IRNode.ADD_VL, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIfAnd = {"AlignVector", "true", "MaxVectorSize", ">= 16"}, applyIfCPUFeatureAnd = {"sse4.1", "true", "avx2", "false"}) // CPU: avx2 -> vector_width: 32 -> elements in vector: 4 - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.ADD_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_L, "> 0", IRNode.ADD_VL, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIfAnd = {"AlignVector", "false", "MaxVectorSize", ">= 16"}, applyIfCPUFeatureAnd = {"avx2", "true", "avx512", "false"}) // Vectorize when strict alignment guaranteed. - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.ADD_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_L, "> 0", IRNode.ADD_VL, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIfAnd = {"AlignVector", "true", "MaxVectorSize", ">= 16"}, applyIfCPUFeatureAnd = {"avx2", "true", "avx512", "false"}) // CPU: avx512 -> vector_width: 64 -> elements in vector: 8 - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.ADD_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_L, "> 0", IRNode.ADD_VL, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIfAnd = {"AlignVector", "false", "MaxVectorSize", ">= 16"}, applyIfCPUFeature = {"avx512", "true"}) // Vectorize when strict alignment guaranteed. - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.ADD_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_L, "> 0", IRNode.ADD_VL, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIfAnd = {"AlignVector", "true", "MaxVectorSize", ">= 16"}, applyIfCPUFeature = {"avx512", "true"}) // CPU: asimd -> vector_width: 32 -> elements in vector: 4 - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.ADD_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_L, "> 0", IRNode.ADD_VL, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIfAnd = {"AlignVector", "false", "MaxVectorSize", ">= 16"}, applyIfCPUFeature = {"asimd", "true"}) // Vectorize when strict alignment guaranteed. - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.ADD_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_L, "> 0", IRNode.ADD_VL, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIfAnd = {"AlignVector", "true", "MaxVectorSize", ">= 16"}, applyIfCPUFeature = {"asimd", "true"}) public static void testLongP128(long[] data) { @@ -4069,35 +4069,35 @@ public static void runLongP128() { @Test // CPU: sse4.1 to avx -> vector_width: 16 -> elements in vector: 2 - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.ADD_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_L, "> 0", IRNode.ADD_VL, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIfAnd = {"AlignVector", "false", "MaxVectorSize", ">= 16"}, applyIfCPUFeatureAnd = {"sse4.1", "true", "avx2", "false"}) // Strict alignment not possible. - @IR(failOn = {IRNode.LOAD_VECTOR, IRNode.ADD_V, IRNode.STORE_VECTOR}, + @IR(failOn = {IRNode.LOAD_VECTOR_L, IRNode.ADD_VL, IRNode.STORE_VECTOR}, applyIf = {"AlignVector", "true"}, applyIfCPUFeatureAnd = {"sse4.1", "true", "avx2", "false"}) // CPU: avx2 -> vector_width: 32 -> elements in vector: 4 - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.ADD_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_L, "> 0", IRNode.ADD_VL, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIfAnd = {"AlignVector", "false", "MaxVectorSize", ">= 16"}, applyIfCPUFeatureAnd = {"avx2", "true", "avx512", "false"}) // Strict alignment not possible. - @IR(failOn = {IRNode.LOAD_VECTOR, IRNode.ADD_V, IRNode.STORE_VECTOR}, + @IR(failOn = {IRNode.LOAD_VECTOR_L, IRNode.ADD_VL, IRNode.STORE_VECTOR}, applyIf = {"AlignVector", "true"}, applyIfCPUFeatureAnd = {"avx2", "true", "avx512", "false"}) // CPU: avx512 -> vector_width: 64 -> elements in vector: 8 - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.ADD_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_L, "> 0", IRNode.ADD_VL, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIfAnd = {"AlignVector", "false", "MaxVectorSize", ">= 16"}, applyIfCPUFeature = {"avx512", "true"}) // Strict alignment not possible. - @IR(failOn = {IRNode.LOAD_VECTOR, IRNode.ADD_V, IRNode.STORE_VECTOR}, + @IR(failOn = {IRNode.LOAD_VECTOR_L, IRNode.ADD_VL, IRNode.STORE_VECTOR}, applyIf = {"AlignVector", "true"}, applyIfCPUFeature = {"avx512", "true"}) // CPU: asimd -> vector_width: 32 -> elements in vector: 4 - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.ADD_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_L, "> 0", IRNode.ADD_VL, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIfAnd = {"AlignVector", "false", "MaxVectorSize", ">= 16"}, applyIfCPUFeature = {"asimd", "true"}) // Strict alignment not possible. - @IR(failOn = {IRNode.LOAD_VECTOR, IRNode.ADD_V, IRNode.STORE_VECTOR}, + @IR(failOn = {IRNode.LOAD_VECTOR_L, IRNode.ADD_VL, IRNode.STORE_VECTOR}, applyIf = {"AlignVector", "true"}, applyIfCPUFeature = {"asimd", "true"}) public static void testLongM129(long[] data) { @@ -4117,19 +4117,19 @@ public static void runLongM129() { @Test // CPU: sse4.1 to avx -> vector_width: 16 -> elements in vector: 2 - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.ADD_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_L, "> 0", IRNode.ADD_VL, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIfAnd = {"AlignVector", "false", "MaxVectorSize", ">= 16"}, applyIfCPUFeatureAnd = {"sse4.1", "true", "avx2", "false"}) // CPU: avx2 -> vector_width: 32 -> elements in vector: 4 - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.ADD_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_L, "> 0", IRNode.ADD_VL, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIfAnd = {"AlignVector", "false", "MaxVectorSize", ">= 16"}, applyIfCPUFeatureAnd = {"avx2", "true", "avx512", "false"}) // CPU: avx512 -> vector_width: 64 -> elements in vector: 8 - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.ADD_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_L, "> 0", IRNode.ADD_VL, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIfAnd = {"AlignVector", "false", "MaxVectorSize", ">= 16"}, applyIfCPUFeature = {"avx512", "true"}) // CPU: asimd -> vector_width: 32 -> elements in vector: 4 - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.ADD_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_L, "> 0", IRNode.ADD_VL, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIfAnd = {"AlignVector", "false", "MaxVectorSize", ">= 16"}, applyIfCPUFeature = {"asimd", "true"}) public static void testLongP129(long[] data) { @@ -4149,19 +4149,19 @@ public static void runLongP129() { @Test // CPU: sse4.1 to avx -> vector_width: 16 -> elements in vector: 2 - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.ADD_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_L, "> 0", IRNode.ADD_VL, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIfAnd = {"AlignVector", "false", "MaxVectorSize", ">= 16"}, applyIfCPUFeatureAnd = {"sse4.1", "true", "avx2", "false"}) // CPU: avx2 -> vector_width: 32 -> elements in vector: 4 - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.ADD_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_L, "> 0", IRNode.ADD_VL, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIfAnd = {"AlignVector", "false", "MaxVectorSize", ">= 16"}, applyIfCPUFeatureAnd = {"avx2", "true", "avx512", "false"}) // CPU: avx512 -> vector_width: 64 -> elements in vector: 8 - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.ADD_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_L, "> 0", IRNode.ADD_VL, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIfAnd = {"AlignVector", "false", "MaxVectorSize", ">= 16"}, applyIfCPUFeature = {"avx512", "true"}) // CPU: asimd -> vector_width: 32 -> elements in vector: 4 - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.ADD_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_L, "> 0", IRNode.ADD_VL, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIfAnd = {"AlignVector", "false", "MaxVectorSize", ">= 16"}, applyIfCPUFeature = {"asimd", "true"}) public static void testLongM192(long[] data) { @@ -4181,35 +4181,35 @@ public static void runLongM192() { @Test // CPU: sse4.1 to avx -> vector_width: 16 -> elements in vector: 2 - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.ADD_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_L, "> 0", IRNode.ADD_VL, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIfAnd = {"AlignVector", "false", "MaxVectorSize", ">= 16"}, applyIfCPUFeatureAnd = {"sse4.1", "true", "avx2", "false"}) // Vectorize when strict alignment guaranteed. - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.ADD_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_L, "> 0", IRNode.ADD_VL, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIfAnd = {"AlignVector", "true", "MaxVectorSize", ">= 16"}, applyIfCPUFeatureAnd = {"sse4.1", "true", "avx2", "false"}) // CPU: avx2 -> vector_width: 32 -> elements in vector: 4 - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.ADD_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_L, "> 0", IRNode.ADD_VL, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIfAnd = {"AlignVector", "false", "MaxVectorSize", ">= 16"}, applyIfCPUFeatureAnd = {"avx2", "true", "avx512", "false"}) // Vectorize when strict alignment guaranteed. - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.ADD_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_L, "> 0", IRNode.ADD_VL, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIfAnd = {"AlignVector", "true", "MaxVectorSize", ">= 16"}, applyIfCPUFeatureAnd = {"avx2", "true", "avx512", "false"}) // CPU: avx512 -> vector_width: 64 -> elements in vector: 8 - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.ADD_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_L, "> 0", IRNode.ADD_VL, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIfAnd = {"AlignVector", "false", "MaxVectorSize", ">= 16"}, applyIfCPUFeature = {"avx512", "true"}) // Vectorize when strict alignment guaranteed. - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.ADD_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_L, "> 0", IRNode.ADD_VL, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIfAnd = {"AlignVector", "true", "MaxVectorSize", ">= 16"}, applyIfCPUFeature = {"avx512", "true"}) // CPU: asimd -> vector_width: 32 -> elements in vector: 4 - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.ADD_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_L, "> 0", IRNode.ADD_VL, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIfAnd = {"AlignVector", "false", "MaxVectorSize", ">= 16"}, applyIfCPUFeature = {"asimd", "true"}) // Vectorize when strict alignment guaranteed. - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.ADD_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_L, "> 0", IRNode.ADD_VL, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIfAnd = {"AlignVector", "true", "MaxVectorSize", ">= 16"}, applyIfCPUFeature = {"asimd", "true"}) public static void testLongP192(long[] data) { @@ -4229,19 +4229,19 @@ public static void runLongP192() { @Test // CPU: sse4.1 to avx -> vector_width: 16 -> elements in vector: 8 - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.MUL_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_S, "> 0", IRNode.MUL_VS, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIfAnd = {"AlignVector", "false", "MaxVectorSize", ">= 4"}, applyIfCPUFeatureAnd = {"sse4.1", "true", "avx2", "false"}) // CPU: avx2 to avx512 without avx512bw -> vector_width: 32 -> elements in vector: 16 - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.MUL_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_S, "> 0", IRNode.MUL_VS, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIfAnd = {"AlignVector", "false", "MaxVectorSize", ">= 4"}, applyIfCPUFeatureAnd = {"avx2", "true", "avx512bw", "false"}) // CPU: avx512bw -> vector_width: 64 -> elements in vector: 32 - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.MUL_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_S, "> 0", IRNode.MUL_VS, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIfAnd = {"AlignVector", "false", "MaxVectorSize", ">= 4"}, applyIfCPUFeature = {"avx512bw", "true"}) // CPU: asimd -> vector_width: 32 -> elements in vector: 16 - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.MUL_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_S, "> 0", IRNode.MUL_VS, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIfAnd = {"AlignVector", "false", "MaxVectorSize", ">= 4"}, applyIfCPUFeature = {"asimd", "true"}) public static void testShortP0(short[] data) { @@ -4261,35 +4261,35 @@ public static void runShortP0() { @Test // CPU: sse4.1 to avx -> vector_width: 16 -> elements in vector: 8 - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.MUL_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_S, "> 0", IRNode.MUL_VS, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIfAnd = {"AlignVector", "false", "MaxVectorSize", ">= 4"}, applyIfCPUFeatureAnd = {"sse4.1", "true", "avx2", "false"}) // Strict alignment not possible. - @IR(failOn = {IRNode.LOAD_VECTOR, IRNode.MUL_V, IRNode.STORE_VECTOR}, + @IR(failOn = {IRNode.LOAD_VECTOR_S, IRNode.MUL_VS, IRNode.STORE_VECTOR}, applyIf = {"AlignVector", "true"}, applyIfCPUFeatureAnd = {"sse4.1", "true", "avx2", "false"}) // CPU: avx2 to avx512 without avx512bw -> vector_width: 32 -> elements in vector: 16 - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.MUL_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_S, "> 0", IRNode.MUL_VS, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIfAnd = {"AlignVector", "false", "MaxVectorSize", ">= 4"}, applyIfCPUFeatureAnd = {"avx2", "true", "avx512bw", "false"}) // Strict alignment not possible. - @IR(failOn = {IRNode.LOAD_VECTOR, IRNode.MUL_V, IRNode.STORE_VECTOR}, + @IR(failOn = {IRNode.LOAD_VECTOR_S, IRNode.MUL_VS, IRNode.STORE_VECTOR}, applyIf = {"AlignVector", "true"}, applyIfCPUFeatureAnd = {"avx2", "true", "avx512bw", "false"}) // CPU: avx512bw -> vector_width: 64 -> elements in vector: 32 - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.MUL_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_S, "> 0", IRNode.MUL_VS, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIfAnd = {"AlignVector", "false", "MaxVectorSize", ">= 4"}, applyIfCPUFeature = {"avx512bw", "true"}) // Strict alignment not possible. - @IR(failOn = {IRNode.LOAD_VECTOR, IRNode.MUL_V, IRNode.STORE_VECTOR}, + @IR(failOn = {IRNode.LOAD_VECTOR_S, IRNode.MUL_VS, IRNode.STORE_VECTOR}, applyIf = {"AlignVector", "true"}, applyIfCPUFeature = {"avx512bw", "true"}) // CPU: asimd -> vector_width: 32 -> elements in vector: 16 - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.MUL_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_S, "> 0", IRNode.MUL_VS, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIfAnd = {"AlignVector", "false", "MaxVectorSize", ">= 4"}, applyIfCPUFeature = {"asimd", "true"}) // Strict alignment not possible. - @IR(failOn = {IRNode.LOAD_VECTOR, IRNode.MUL_V, IRNode.STORE_VECTOR}, + @IR(failOn = {IRNode.LOAD_VECTOR_S, IRNode.MUL_VS, IRNode.STORE_VECTOR}, applyIf = {"AlignVector", "true"}, applyIfCPUFeature = {"asimd", "true"}) public static void testShortM1(short[] data) { @@ -4337,19 +4337,19 @@ public static void runShortP1() { @Test // CPU: sse4.1 to avx -> vector_width: 16 -> elements in vector: 8 - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.MUL_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_S, "> 0", IRNode.MUL_VS, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIfAnd = {"AlignVector", "false", "MaxVectorSize", ">= 4"}, applyIfCPUFeatureAnd = {"sse4.1", "true", "avx2", "false"}) // CPU: avx2 to avx512 without avx512bw -> vector_width: 32 -> elements in vector: 16 - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.MUL_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_S, "> 0", IRNode.MUL_VS, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIfAnd = {"AlignVector", "false", "MaxVectorSize", ">= 4"}, applyIfCPUFeatureAnd = {"avx2", "true", "avx512bw", "false"}) // CPU: avx512bw -> vector_width: 64 -> elements in vector: 32 - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.MUL_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_S, "> 0", IRNode.MUL_VS, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIfAnd = {"AlignVector", "false", "MaxVectorSize", ">= 4"}, applyIfCPUFeature = {"avx512bw", "true"}) // CPU: asimd -> vector_width: 32 -> elements in vector: 16 - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.MUL_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_S, "> 0", IRNode.MUL_VS, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIfAnd = {"AlignVector", "false", "MaxVectorSize", ">= 4"}, applyIfCPUFeature = {"asimd", "true"}) public static void testShortM2(short[] data) { @@ -4370,22 +4370,22 @@ public static void runShortM2() { @Test // CPU: sse4.1 to avx -> vector_width: 16 -> elements in vector: 8 // positive byte_offset 4 can lead to cyclic dependency - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.MUL_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_S, "> 0", IRNode.MUL_VS, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIfAnd = {"AlignVector", "false", "MaxVectorSize", ">= 4", "MaxVectorSize", "<= 4"}, applyIfCPUFeatureAnd = {"sse4.1", "true", "avx2", "false"}) // CPU: avx2 to avx512 without avx512bw -> vector_width: 32 -> elements in vector: 16 // positive byte_offset 4 can lead to cyclic dependency - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.MUL_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_S, "> 0", IRNode.MUL_VS, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIfAnd = {"AlignVector", "false", "MaxVectorSize", ">= 4", "MaxVectorSize", "<= 4"}, applyIfCPUFeatureAnd = {"avx2", "true", "avx512bw", "false"}) // CPU: avx512bw -> vector_width: 64 -> elements in vector: 32 // positive byte_offset 4 can lead to cyclic dependency - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.MUL_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_S, "> 0", IRNode.MUL_VS, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIfAnd = {"AlignVector", "false", "MaxVectorSize", ">= 4", "MaxVectorSize", "<= 4"}, applyIfCPUFeature = {"avx512bw", "true"}) // CPU: asimd -> vector_width: 32 -> elements in vector: 16 // positive byte_offset 4 can lead to cyclic dependency - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.MUL_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_S, "> 0", IRNode.MUL_VS, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIfAnd = {"AlignVector", "false", "MaxVectorSize", ">= 4", "MaxVectorSize", "<= 4"}, applyIfCPUFeature = {"asimd", "true"}) public static void testShortP2(short[] data) { @@ -4405,35 +4405,35 @@ public static void runShortP2() { @Test // CPU: sse4.1 to avx -> vector_width: 16 -> elements in vector: 8 - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.MUL_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_S, "> 0", IRNode.MUL_VS, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIfAnd = {"AlignVector", "false", "MaxVectorSize", ">= 4"}, applyIfCPUFeatureAnd = {"sse4.1", "true", "avx2", "false"}) // Strict alignment not possible. - @IR(failOn = {IRNode.LOAD_VECTOR, IRNode.MUL_V, IRNode.STORE_VECTOR}, + @IR(failOn = {IRNode.LOAD_VECTOR_S, IRNode.MUL_VS, IRNode.STORE_VECTOR}, applyIf = {"AlignVector", "true"}, applyIfCPUFeatureAnd = {"sse4.1", "true", "avx2", "false"}) // CPU: avx2 to avx512 without avx512bw -> vector_width: 32 -> elements in vector: 16 - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.MUL_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_S, "> 0", IRNode.MUL_VS, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIfAnd = {"AlignVector", "false", "MaxVectorSize", ">= 4"}, applyIfCPUFeatureAnd = {"avx2", "true", "avx512bw", "false"}) // Strict alignment not possible. - @IR(failOn = {IRNode.LOAD_VECTOR, IRNode.MUL_V, IRNode.STORE_VECTOR}, + @IR(failOn = {IRNode.LOAD_VECTOR_S, IRNode.MUL_VS, IRNode.STORE_VECTOR}, applyIf = {"AlignVector", "true"}, applyIfCPUFeatureAnd = {"avx2", "true", "avx512bw", "false"}) // CPU: avx512bw -> vector_width: 64 -> elements in vector: 32 - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.MUL_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_S, "> 0", IRNode.MUL_VS, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIfAnd = {"AlignVector", "false", "MaxVectorSize", ">= 4"}, applyIfCPUFeature = {"avx512bw", "true"}) // Strict alignment not possible. - @IR(failOn = {IRNode.LOAD_VECTOR, IRNode.MUL_V, IRNode.STORE_VECTOR}, + @IR(failOn = {IRNode.LOAD_VECTOR_S, IRNode.MUL_VS, IRNode.STORE_VECTOR}, applyIf = {"AlignVector", "true"}, applyIfCPUFeature = {"avx512bw", "true"}) // CPU: asimd -> vector_width: 32 -> elements in vector: 16 - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.MUL_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_S, "> 0", IRNode.MUL_VS, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIfAnd = {"AlignVector", "false", "MaxVectorSize", ">= 4"}, applyIfCPUFeature = {"asimd", "true"}) // Strict alignment not possible. - @IR(failOn = {IRNode.LOAD_VECTOR, IRNode.MUL_V, IRNode.STORE_VECTOR}, + @IR(failOn = {IRNode.LOAD_VECTOR_S, IRNode.MUL_VS, IRNode.STORE_VECTOR}, applyIf = {"AlignVector", "true"}, applyIfCPUFeature = {"asimd", "true"}) public static void testShortM3(short[] data) { @@ -4454,22 +4454,22 @@ public static void runShortM3() { @Test // CPU: sse4.1 to avx -> vector_width: 16 -> elements in vector: 8 // positive byte_offset 6 can lead to cyclic dependency - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.MUL_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_S, "> 0", IRNode.MUL_VS, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIfAnd = {"AlignVector", "false", "MaxVectorSize", ">= 4", "MaxVectorSize", "<= 6"}, applyIfCPUFeatureAnd = {"sse4.1", "true", "avx2", "false"}) // CPU: avx2 to avx512 without avx512bw -> vector_width: 32 -> elements in vector: 16 // positive byte_offset 6 can lead to cyclic dependency - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.MUL_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_S, "> 0", IRNode.MUL_VS, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIfAnd = {"AlignVector", "false", "MaxVectorSize", ">= 4", "MaxVectorSize", "<= 6"}, applyIfCPUFeatureAnd = {"avx2", "true", "avx512bw", "false"}) // CPU: avx512bw -> vector_width: 64 -> elements in vector: 32 // positive byte_offset 6 can lead to cyclic dependency - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.MUL_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_S, "> 0", IRNode.MUL_VS, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIfAnd = {"AlignVector", "false", "MaxVectorSize", ">= 4", "MaxVectorSize", "<= 6"}, applyIfCPUFeature = {"avx512bw", "true"}) // CPU: asimd -> vector_width: 32 -> elements in vector: 16 // positive byte_offset 6 can lead to cyclic dependency - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.MUL_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_S, "> 0", IRNode.MUL_VS, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIfAnd = {"AlignVector", "false", "MaxVectorSize", ">= 4", "MaxVectorSize", "<= 6"}, applyIfCPUFeature = {"asimd", "true"}) public static void testShortP3(short[] data) { @@ -4489,19 +4489,19 @@ public static void runShortP3() { @Test // CPU: sse4.1 to avx -> vector_width: 16 -> elements in vector: 8 - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.MUL_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_S, "> 0", IRNode.MUL_VS, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIfAnd = {"AlignVector", "false", "MaxVectorSize", ">= 4"}, applyIfCPUFeatureAnd = {"sse4.1", "true", "avx2", "false"}) // CPU: avx2 to avx512 without avx512bw -> vector_width: 32 -> elements in vector: 16 - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.MUL_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_S, "> 0", IRNode.MUL_VS, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIfAnd = {"AlignVector", "false", "MaxVectorSize", ">= 4"}, applyIfCPUFeatureAnd = {"avx2", "true", "avx512bw", "false"}) // CPU: avx512bw -> vector_width: 64 -> elements in vector: 32 - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.MUL_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_S, "> 0", IRNode.MUL_VS, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIfAnd = {"AlignVector", "false", "MaxVectorSize", ">= 4"}, applyIfCPUFeature = {"avx512bw", "true"}) // CPU: asimd -> vector_width: 32 -> elements in vector: 16 - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.MUL_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_S, "> 0", IRNode.MUL_VS, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIfAnd = {"AlignVector", "false", "MaxVectorSize", ">= 4"}, applyIfCPUFeature = {"asimd", "true"}) public static void testShortM4(short[] data) { @@ -4522,22 +4522,22 @@ public static void runShortM4() { @Test // CPU: sse4.1 to avx -> vector_width: 16 -> elements in vector: 8 // positive byte_offset 8 can lead to cyclic dependency - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.MUL_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_S, "> 0", IRNode.MUL_VS, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIfAnd = {"AlignVector", "false", "MaxVectorSize", ">= 4", "MaxVectorSize", "<= 8"}, applyIfCPUFeatureAnd = {"sse4.1", "true", "avx2", "false"}) // CPU: avx2 to avx512 without avx512bw -> vector_width: 32 -> elements in vector: 16 // positive byte_offset 8 can lead to cyclic dependency - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.MUL_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_S, "> 0", IRNode.MUL_VS, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIfAnd = {"AlignVector", "false", "MaxVectorSize", ">= 4", "MaxVectorSize", "<= 8"}, applyIfCPUFeatureAnd = {"avx2", "true", "avx512bw", "false"}) // CPU: avx512bw -> vector_width: 64 -> elements in vector: 32 // positive byte_offset 8 can lead to cyclic dependency - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.MUL_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_S, "> 0", IRNode.MUL_VS, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIfAnd = {"AlignVector", "false", "MaxVectorSize", ">= 4", "MaxVectorSize", "<= 8"}, applyIfCPUFeature = {"avx512bw", "true"}) // CPU: asimd -> vector_width: 32 -> elements in vector: 16 // positive byte_offset 8 can lead to cyclic dependency - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.MUL_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_S, "> 0", IRNode.MUL_VS, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIfAnd = {"AlignVector", "false", "MaxVectorSize", ">= 4", "MaxVectorSize", "<= 8"}, applyIfCPUFeature = {"asimd", "true"}) public static void testShortP4(short[] data) { @@ -4557,35 +4557,35 @@ public static void runShortP4() { @Test // CPU: sse4.1 to avx -> vector_width: 16 -> elements in vector: 8 - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.MUL_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_S, "> 0", IRNode.MUL_VS, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIfAnd = {"AlignVector", "false", "MaxVectorSize", ">= 4"}, applyIfCPUFeatureAnd = {"sse4.1", "true", "avx2", "false"}) // Strict alignment not possible. - @IR(failOn = {IRNode.LOAD_VECTOR, IRNode.MUL_V, IRNode.STORE_VECTOR}, + @IR(failOn = {IRNode.LOAD_VECTOR_S, IRNode.MUL_VS, IRNode.STORE_VECTOR}, applyIf = {"AlignVector", "true"}, applyIfCPUFeatureAnd = {"sse4.1", "true", "avx2", "false"}) // CPU: avx2 to avx512 without avx512bw -> vector_width: 32 -> elements in vector: 16 - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.MUL_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_S, "> 0", IRNode.MUL_VS, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIfAnd = {"AlignVector", "false", "MaxVectorSize", ">= 4"}, applyIfCPUFeatureAnd = {"avx2", "true", "avx512bw", "false"}) // Strict alignment not possible. - @IR(failOn = {IRNode.LOAD_VECTOR, IRNode.MUL_V, IRNode.STORE_VECTOR}, + @IR(failOn = {IRNode.LOAD_VECTOR_S, IRNode.MUL_VS, IRNode.STORE_VECTOR}, applyIf = {"AlignVector", "true"}, applyIfCPUFeatureAnd = {"avx2", "true", "avx512bw", "false"}) // CPU: avx512bw -> vector_width: 64 -> elements in vector: 32 - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.MUL_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_S, "> 0", IRNode.MUL_VS, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIfAnd = {"AlignVector", "false", "MaxVectorSize", ">= 4"}, applyIfCPUFeature = {"avx512bw", "true"}) // Strict alignment not possible. - @IR(failOn = {IRNode.LOAD_VECTOR, IRNode.MUL_V, IRNode.STORE_VECTOR}, + @IR(failOn = {IRNode.LOAD_VECTOR_S, IRNode.MUL_VS, IRNode.STORE_VECTOR}, applyIf = {"AlignVector", "true"}, applyIfCPUFeature = {"avx512bw", "true"}) // CPU: asimd -> vector_width: 32 -> elements in vector: 16 - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.MUL_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_S, "> 0", IRNode.MUL_VS, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIfAnd = {"AlignVector", "false", "MaxVectorSize", ">= 4"}, applyIfCPUFeature = {"asimd", "true"}) // Strict alignment not possible. - @IR(failOn = {IRNode.LOAD_VECTOR, IRNode.MUL_V, IRNode.STORE_VECTOR}, + @IR(failOn = {IRNode.LOAD_VECTOR_S, IRNode.MUL_VS, IRNode.STORE_VECTOR}, applyIf = {"AlignVector", "true"}, applyIfCPUFeature = {"asimd", "true"}) public static void testShortM7(short[] data) { @@ -4606,22 +4606,22 @@ public static void runShortM7() { @Test // CPU: sse4.1 to avx -> vector_width: 16 -> elements in vector: 8 // positive byte_offset 14 can lead to cyclic dependency - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.MUL_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_S, "> 0", IRNode.MUL_VS, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIfAnd = {"AlignVector", "false", "MaxVectorSize", ">= 4", "MaxVectorSize", "<= 14"}, applyIfCPUFeatureAnd = {"sse4.1", "true", "avx2", "false"}) // CPU: avx2 to avx512 without avx512bw -> vector_width: 32 -> elements in vector: 16 // positive byte_offset 14 can lead to cyclic dependency - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.MUL_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_S, "> 0", IRNode.MUL_VS, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIfAnd = {"AlignVector", "false", "MaxVectorSize", ">= 4", "MaxVectorSize", "<= 14"}, applyIfCPUFeatureAnd = {"avx2", "true", "avx512bw", "false"}) // CPU: avx512bw -> vector_width: 64 -> elements in vector: 32 // positive byte_offset 14 can lead to cyclic dependency - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.MUL_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_S, "> 0", IRNode.MUL_VS, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIfAnd = {"AlignVector", "false", "MaxVectorSize", ">= 4", "MaxVectorSize", "<= 14"}, applyIfCPUFeature = {"avx512bw", "true"}) // CPU: asimd -> vector_width: 32 -> elements in vector: 16 // positive byte_offset 14 can lead to cyclic dependency - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.MUL_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_S, "> 0", IRNode.MUL_VS, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIfAnd = {"AlignVector", "false", "MaxVectorSize", ">= 4", "MaxVectorSize", "<= 14"}, applyIfCPUFeature = {"asimd", "true"}) public static void testShortP7(short[] data) { @@ -4641,19 +4641,19 @@ public static void runShortP7() { @Test // CPU: sse4.1 to avx -> vector_width: 16 -> elements in vector: 8 - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.MUL_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_S, "> 0", IRNode.MUL_VS, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIfAnd = {"AlignVector", "false", "MaxVectorSize", ">= 4"}, applyIfCPUFeatureAnd = {"sse4.1", "true", "avx2", "false"}) // CPU: avx2 to avx512 without avx512bw -> vector_width: 32 -> elements in vector: 16 - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.MUL_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_S, "> 0", IRNode.MUL_VS, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIfAnd = {"AlignVector", "false", "MaxVectorSize", ">= 4"}, applyIfCPUFeatureAnd = {"avx2", "true", "avx512bw", "false"}) // CPU: avx512bw -> vector_width: 64 -> elements in vector: 32 - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.MUL_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_S, "> 0", IRNode.MUL_VS, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIfAnd = {"AlignVector", "false", "MaxVectorSize", ">= 4"}, applyIfCPUFeature = {"avx512bw", "true"}) // CPU: asimd -> vector_width: 32 -> elements in vector: 16 - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.MUL_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_S, "> 0", IRNode.MUL_VS, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIfAnd = {"AlignVector", "false", "MaxVectorSize", ">= 4"}, applyIfCPUFeature = {"asimd", "true"}) public static void testShortM8(short[] data) { @@ -4673,26 +4673,26 @@ public static void runShortM8() { @Test // CPU: sse4.1 to avx -> vector_width: 16 -> elements in vector: 8 - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.MUL_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_S, "> 0", IRNode.MUL_VS, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIfAnd = {"AlignVector", "false", "MaxVectorSize", ">= 4"}, applyIfCPUFeatureAnd = {"sse4.1", "true", "avx2", "false"}) // Vectorize when strict alignment guaranteed. - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.MUL_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_S, "> 0", IRNode.MUL_VS, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIfAnd = {"AlignVector", "true", "MaxVectorSize", ">= 4"}, applyIfCPUFeatureAnd = {"sse4.1", "true", "avx2", "false"}) // CPU: avx2 to avx512 without avx512bw -> vector_width: 32 -> elements in vector: 16 // positive byte_offset 16 can lead to cyclic dependency - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.MUL_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_S, "> 0", IRNode.MUL_VS, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIfAnd = {"AlignVector", "false", "MaxVectorSize", ">= 4", "MaxVectorSize", "<= 16"}, applyIfCPUFeatureAnd = {"avx2", "true", "avx512bw", "false"}) // CPU: avx512bw -> vector_width: 64 -> elements in vector: 32 // positive byte_offset 16 can lead to cyclic dependency - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.MUL_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_S, "> 0", IRNode.MUL_VS, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIfAnd = {"AlignVector", "false", "MaxVectorSize", ">= 4", "MaxVectorSize", "<= 16"}, applyIfCPUFeature = {"avx512bw", "true"}) // CPU: asimd -> vector_width: 32 -> elements in vector: 16 // positive byte_offset 16 can lead to cyclic dependency - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.MUL_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_S, "> 0", IRNode.MUL_VS, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIfAnd = {"AlignVector", "false", "MaxVectorSize", ">= 4", "MaxVectorSize", "<= 16"}, applyIfCPUFeature = {"asimd", "true"}) public static void testShortP8(short[] data) { @@ -4712,19 +4712,19 @@ public static void runShortP8() { @Test // CPU: sse4.1 to avx -> vector_width: 16 -> elements in vector: 8 - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.MUL_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_S, "> 0", IRNode.MUL_VS, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIfAnd = {"AlignVector", "false", "MaxVectorSize", ">= 4"}, applyIfCPUFeatureAnd = {"sse4.1", "true", "avx2", "false"}) // CPU: avx2 to avx512 without avx512bw -> vector_width: 32 -> elements in vector: 16 - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.MUL_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_S, "> 0", IRNode.MUL_VS, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIfAnd = {"AlignVector", "false", "MaxVectorSize", ">= 4"}, applyIfCPUFeatureAnd = {"avx2", "true", "avx512bw", "false"}) // CPU: avx512bw -> vector_width: 64 -> elements in vector: 32 - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.MUL_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_S, "> 0", IRNode.MUL_VS, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIfAnd = {"AlignVector", "false", "MaxVectorSize", ">= 4"}, applyIfCPUFeature = {"avx512bw", "true"}) // CPU: asimd -> vector_width: 32 -> elements in vector: 16 - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.MUL_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_S, "> 0", IRNode.MUL_VS, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIfAnd = {"AlignVector", "false", "MaxVectorSize", ">= 4"}, applyIfCPUFeature = {"asimd", "true"}) public static void testShortM14(short[] data) { @@ -4744,22 +4744,22 @@ public static void runShortM14() { @Test // CPU: sse4.1 to avx -> vector_width: 16 -> elements in vector: 8 - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.MUL_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_S, "> 0", IRNode.MUL_VS, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIfAnd = {"AlignVector", "false", "MaxVectorSize", ">= 4"}, applyIfCPUFeatureAnd = {"sse4.1", "true", "avx2", "false"}) // CPU: avx2 to avx512 without avx512bw -> vector_width: 32 -> elements in vector: 16 // positive byte_offset 28 can lead to cyclic dependency - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.MUL_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_S, "> 0", IRNode.MUL_VS, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIfAnd = {"AlignVector", "false", "MaxVectorSize", ">= 4", "MaxVectorSize", "<= 28"}, applyIfCPUFeatureAnd = {"avx2", "true", "avx512bw", "false"}) // CPU: avx512bw -> vector_width: 64 -> elements in vector: 32 // positive byte_offset 28 can lead to cyclic dependency - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.MUL_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_S, "> 0", IRNode.MUL_VS, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIfAnd = {"AlignVector", "false", "MaxVectorSize", ">= 4", "MaxVectorSize", "<= 28"}, applyIfCPUFeature = {"avx512bw", "true"}) // CPU: asimd -> vector_width: 32 -> elements in vector: 16 // positive byte_offset 28 can lead to cyclic dependency - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.MUL_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_S, "> 0", IRNode.MUL_VS, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIfAnd = {"AlignVector", "false", "MaxVectorSize", ">= 4", "MaxVectorSize", "<= 28"}, applyIfCPUFeature = {"asimd", "true"}) public static void testShortP14(short[] data) { @@ -4779,19 +4779,19 @@ public static void runShortP14() { @Test // CPU: sse4.1 to avx -> vector_width: 16 -> elements in vector: 8 - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.MUL_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_S, "> 0", IRNode.MUL_VS, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIfAnd = {"AlignVector", "false", "MaxVectorSize", ">= 4"}, applyIfCPUFeatureAnd = {"sse4.1", "true", "avx2", "false"}) // CPU: avx2 to avx512 without avx512bw -> vector_width: 32 -> elements in vector: 16 - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.MUL_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_S, "> 0", IRNode.MUL_VS, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIfAnd = {"AlignVector", "false", "MaxVectorSize", ">= 4"}, applyIfCPUFeatureAnd = {"avx2", "true", "avx512bw", "false"}) // CPU: avx512bw -> vector_width: 64 -> elements in vector: 32 - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.MUL_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_S, "> 0", IRNode.MUL_VS, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIfAnd = {"AlignVector", "false", "MaxVectorSize", ">= 4"}, applyIfCPUFeature = {"avx512bw", "true"}) // CPU: asimd -> vector_width: 32 -> elements in vector: 16 - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.MUL_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_S, "> 0", IRNode.MUL_VS, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIfAnd = {"AlignVector", "false", "MaxVectorSize", ">= 4"}, applyIfCPUFeature = {"asimd", "true"}) public static void testShortM16(short[] data) { @@ -4811,32 +4811,32 @@ public static void runShortM16() { @Test // CPU: sse4.1 to avx -> vector_width: 16 -> elements in vector: 8 - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.MUL_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_S, "> 0", IRNode.MUL_VS, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIfAnd = {"AlignVector", "false", "MaxVectorSize", ">= 4"}, applyIfCPUFeatureAnd = {"sse4.1", "true", "avx2", "false"}) // Vectorize when strict alignment guaranteed. - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.MUL_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_S, "> 0", IRNode.MUL_VS, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIfAnd = {"AlignVector", "true", "MaxVectorSize", ">= 4"}, applyIfCPUFeatureAnd = {"sse4.1", "true", "avx2", "false"}) // CPU: avx2 to avx512 without avx512bw -> vector_width: 32 -> elements in vector: 16 - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.MUL_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_S, "> 0", IRNode.MUL_VS, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIfAnd = {"AlignVector", "false", "MaxVectorSize", ">= 4"}, applyIfCPUFeatureAnd = {"avx2", "true", "avx512bw", "false"}) // Vectorize when strict alignment guaranteed. - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.MUL_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_S, "> 0", IRNode.MUL_VS, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIfAnd = {"AlignVector", "true", "MaxVectorSize", ">= 4"}, applyIfCPUFeatureAnd = {"avx2", "true", "avx512bw", "false"}) // CPU: avx512bw -> vector_width: 64 -> elements in vector: 32 // positive byte_offset 32 can lead to cyclic dependency - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.MUL_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_S, "> 0", IRNode.MUL_VS, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIfAnd = {"AlignVector", "false", "MaxVectorSize", ">= 4", "MaxVectorSize", "<= 32"}, applyIfCPUFeature = {"avx512bw", "true"}) // CPU: asimd -> vector_width: 32 -> elements in vector: 16 - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.MUL_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_S, "> 0", IRNode.MUL_VS, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIfAnd = {"AlignVector", "false", "MaxVectorSize", ">= 4"}, applyIfCPUFeature = {"asimd", "true"}) // Vectorize when strict alignment guaranteed. - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.MUL_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_S, "> 0", IRNode.MUL_VS, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIfAnd = {"AlignVector", "true", "MaxVectorSize", ">= 4"}, applyIfCPUFeature = {"asimd", "true"}) public static void testShortP16(short[] data) { @@ -4856,19 +4856,19 @@ public static void runShortP16() { @Test // CPU: sse4.1 to avx -> vector_width: 16 -> elements in vector: 8 - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.MUL_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_S, "> 0", IRNode.MUL_VS, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIfAnd = {"AlignVector", "false", "MaxVectorSize", ">= 4"}, applyIfCPUFeatureAnd = {"sse4.1", "true", "avx2", "false"}) // CPU: avx2 to avx512 without avx512bw -> vector_width: 32 -> elements in vector: 16 - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.MUL_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_S, "> 0", IRNode.MUL_VS, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIfAnd = {"AlignVector", "false", "MaxVectorSize", ">= 4"}, applyIfCPUFeatureAnd = {"avx2", "true", "avx512bw", "false"}) // CPU: avx512bw -> vector_width: 64 -> elements in vector: 32 - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.MUL_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_S, "> 0", IRNode.MUL_VS, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIfAnd = {"AlignVector", "false", "MaxVectorSize", ">= 4"}, applyIfCPUFeature = {"avx512bw", "true"}) // CPU: asimd -> vector_width: 32 -> elements in vector: 16 - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.MUL_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_S, "> 0", IRNode.MUL_VS, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIfAnd = {"AlignVector", "false", "MaxVectorSize", ">= 4"}, applyIfCPUFeature = {"asimd", "true"}) public static void testShortM18(short[] data) { @@ -4888,20 +4888,20 @@ public static void runShortM18() { @Test // CPU: sse4.1 to avx -> vector_width: 16 -> elements in vector: 8 - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.MUL_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_S, "> 0", IRNode.MUL_VS, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIfAnd = {"AlignVector", "false", "MaxVectorSize", ">= 4"}, applyIfCPUFeatureAnd = {"sse4.1", "true", "avx2", "false"}) // CPU: avx2 to avx512 without avx512bw -> vector_width: 32 -> elements in vector: 16 - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.MUL_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_S, "> 0", IRNode.MUL_VS, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIfAnd = {"AlignVector", "false", "MaxVectorSize", ">= 4"}, applyIfCPUFeatureAnd = {"avx2", "true", "avx512bw", "false"}) // CPU: avx512bw -> vector_width: 64 -> elements in vector: 32 // positive byte_offset 36 can lead to cyclic dependency - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.MUL_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_S, "> 0", IRNode.MUL_VS, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIfAnd = {"AlignVector", "false", "MaxVectorSize", ">= 4", "MaxVectorSize", "<= 36"}, applyIfCPUFeature = {"avx512bw", "true"}) // CPU: asimd -> vector_width: 32 -> elements in vector: 16 - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.MUL_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_S, "> 0", IRNode.MUL_VS, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIfAnd = {"AlignVector", "false", "MaxVectorSize", ">= 4"}, applyIfCPUFeature = {"asimd", "true"}) public static void testShortP18(short[] data) { @@ -4921,19 +4921,19 @@ public static void runShortP18() { @Test // CPU: sse4.1 to avx -> vector_width: 16 -> elements in vector: 8 - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.MUL_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_S, "> 0", IRNode.MUL_VS, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIfAnd = {"AlignVector", "false", "MaxVectorSize", ">= 4"}, applyIfCPUFeatureAnd = {"sse4.1", "true", "avx2", "false"}) // CPU: avx2 to avx512 without avx512bw -> vector_width: 32 -> elements in vector: 16 - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.MUL_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_S, "> 0", IRNode.MUL_VS, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIfAnd = {"AlignVector", "false", "MaxVectorSize", ">= 4"}, applyIfCPUFeatureAnd = {"avx2", "true", "avx512bw", "false"}) // CPU: avx512bw -> vector_width: 64 -> elements in vector: 32 - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.MUL_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_S, "> 0", IRNode.MUL_VS, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIfAnd = {"AlignVector", "false", "MaxVectorSize", ">= 4"}, applyIfCPUFeature = {"avx512bw", "true"}) // CPU: asimd -> vector_width: 32 -> elements in vector: 16 - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.MUL_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_S, "> 0", IRNode.MUL_VS, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIfAnd = {"AlignVector", "false", "MaxVectorSize", ">= 4"}, applyIfCPUFeature = {"asimd", "true"}) public static void testShortM20(short[] data) { @@ -4953,20 +4953,20 @@ public static void runShortM20() { @Test // CPU: sse4.1 to avx -> vector_width: 16 -> elements in vector: 8 - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.MUL_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_S, "> 0", IRNode.MUL_VS, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIfAnd = {"AlignVector", "false", "MaxVectorSize", ">= 4"}, applyIfCPUFeatureAnd = {"sse4.1", "true", "avx2", "false"}) // CPU: avx2 to avx512 without avx512bw -> vector_width: 32 -> elements in vector: 16 - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.MUL_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_S, "> 0", IRNode.MUL_VS, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIfAnd = {"AlignVector", "false", "MaxVectorSize", ">= 4"}, applyIfCPUFeatureAnd = {"avx2", "true", "avx512bw", "false"}) // CPU: avx512bw -> vector_width: 64 -> elements in vector: 32 // positive byte_offset 40 can lead to cyclic dependency - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.MUL_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_S, "> 0", IRNode.MUL_VS, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIfAnd = {"AlignVector", "false", "MaxVectorSize", ">= 4", "MaxVectorSize", "<= 40"}, applyIfCPUFeature = {"avx512bw", "true"}) // CPU: asimd -> vector_width: 32 -> elements in vector: 16 - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.MUL_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_S, "> 0", IRNode.MUL_VS, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIfAnd = {"AlignVector", "false", "MaxVectorSize", ">= 4"}, applyIfCPUFeature = {"asimd", "true"}) public static void testShortP20(short[] data) { @@ -4986,35 +4986,35 @@ public static void runShortP20() { @Test // CPU: sse4.1 to avx -> vector_width: 16 -> elements in vector: 8 - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.MUL_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_S, "> 0", IRNode.MUL_VS, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIfAnd = {"AlignVector", "false", "MaxVectorSize", ">= 4"}, applyIfCPUFeatureAnd = {"sse4.1", "true", "avx2", "false"}) // Strict alignment not possible. - @IR(failOn = {IRNode.LOAD_VECTOR, IRNode.MUL_V, IRNode.STORE_VECTOR}, + @IR(failOn = {IRNode.LOAD_VECTOR_S, IRNode.MUL_VS, IRNode.STORE_VECTOR}, applyIf = {"AlignVector", "true"}, applyIfCPUFeatureAnd = {"sse4.1", "true", "avx2", "false"}) // CPU: avx2 to avx512 without avx512bw -> vector_width: 32 -> elements in vector: 16 - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.MUL_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_S, "> 0", IRNode.MUL_VS, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIfAnd = {"AlignVector", "false", "MaxVectorSize", ">= 4"}, applyIfCPUFeatureAnd = {"avx2", "true", "avx512bw", "false"}) // Strict alignment not possible. - @IR(failOn = {IRNode.LOAD_VECTOR, IRNode.MUL_V, IRNode.STORE_VECTOR}, + @IR(failOn = {IRNode.LOAD_VECTOR_S, IRNode.MUL_VS, IRNode.STORE_VECTOR}, applyIf = {"AlignVector", "true"}, applyIfCPUFeatureAnd = {"avx2", "true", "avx512bw", "false"}) // CPU: avx512bw -> vector_width: 64 -> elements in vector: 32 - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.MUL_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_S, "> 0", IRNode.MUL_VS, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIfAnd = {"AlignVector", "false", "MaxVectorSize", ">= 4"}, applyIfCPUFeature = {"avx512bw", "true"}) // Strict alignment not possible. - @IR(failOn = {IRNode.LOAD_VECTOR, IRNode.MUL_V, IRNode.STORE_VECTOR}, + @IR(failOn = {IRNode.LOAD_VECTOR_S, IRNode.MUL_VS, IRNode.STORE_VECTOR}, applyIf = {"AlignVector", "true"}, applyIfCPUFeature = {"avx512bw", "true"}) // CPU: asimd -> vector_width: 32 -> elements in vector: 16 - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.MUL_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_S, "> 0", IRNode.MUL_VS, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIfAnd = {"AlignVector", "false", "MaxVectorSize", ">= 4"}, applyIfCPUFeature = {"asimd", "true"}) // Strict alignment not possible. - @IR(failOn = {IRNode.LOAD_VECTOR, IRNode.MUL_V, IRNode.STORE_VECTOR}, + @IR(failOn = {IRNode.LOAD_VECTOR_S, IRNode.MUL_VS, IRNode.STORE_VECTOR}, applyIf = {"AlignVector", "true"}, applyIfCPUFeature = {"asimd", "true"}) public static void testShortM31(short[] data) { @@ -5034,20 +5034,20 @@ public static void runShortM31() { @Test // CPU: sse4.1 to avx -> vector_width: 16 -> elements in vector: 8 - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.MUL_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_S, "> 0", IRNode.MUL_VS, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIfAnd = {"AlignVector", "false", "MaxVectorSize", ">= 4"}, applyIfCPUFeatureAnd = {"sse4.1", "true", "avx2", "false"}) // CPU: avx2 to avx512 without avx512bw -> vector_width: 32 -> elements in vector: 16 - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.MUL_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_S, "> 0", IRNode.MUL_VS, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIfAnd = {"AlignVector", "false", "MaxVectorSize", ">= 4"}, applyIfCPUFeatureAnd = {"avx2", "true", "avx512bw", "false"}) // CPU: avx512bw -> vector_width: 64 -> elements in vector: 32 // positive byte_offset 62 can lead to cyclic dependency - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.MUL_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_S, "> 0", IRNode.MUL_VS, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIfAnd = {"AlignVector", "false", "MaxVectorSize", ">= 4", "MaxVectorSize", "<= 62"}, applyIfCPUFeature = {"avx512bw", "true"}) // CPU: asimd -> vector_width: 32 -> elements in vector: 16 - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.MUL_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_S, "> 0", IRNode.MUL_VS, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIfAnd = {"AlignVector", "false", "MaxVectorSize", ">= 4"}, applyIfCPUFeature = {"asimd", "true"}) public static void testShortP31(short[] data) { @@ -5067,19 +5067,19 @@ public static void runShortP31() { @Test // CPU: sse4.1 to avx -> vector_width: 16 -> elements in vector: 8 - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.MUL_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_S, "> 0", IRNode.MUL_VS, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIfAnd = {"AlignVector", "false", "MaxVectorSize", ">= 4"}, applyIfCPUFeatureAnd = {"sse4.1", "true", "avx2", "false"}) // CPU: avx2 to avx512 without avx512bw -> vector_width: 32 -> elements in vector: 16 - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.MUL_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_S, "> 0", IRNode.MUL_VS, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIfAnd = {"AlignVector", "false", "MaxVectorSize", ">= 4"}, applyIfCPUFeatureAnd = {"avx2", "true", "avx512bw", "false"}) // CPU: avx512bw -> vector_width: 64 -> elements in vector: 32 - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.MUL_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_S, "> 0", IRNode.MUL_VS, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIfAnd = {"AlignVector", "false", "MaxVectorSize", ">= 4"}, applyIfCPUFeature = {"avx512bw", "true"}) // CPU: asimd -> vector_width: 32 -> elements in vector: 16 - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.MUL_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_S, "> 0", IRNode.MUL_VS, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIfAnd = {"AlignVector", "false", "MaxVectorSize", ">= 4"}, applyIfCPUFeature = {"asimd", "true"}) public static void testShortM32(short[] data) { @@ -5099,35 +5099,35 @@ public static void runShortM32() { @Test // CPU: sse4.1 to avx -> vector_width: 16 -> elements in vector: 8 - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.MUL_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_S, "> 0", IRNode.MUL_VS, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIfAnd = {"AlignVector", "false", "MaxVectorSize", ">= 4"}, applyIfCPUFeatureAnd = {"sse4.1", "true", "avx2", "false"}) // Vectorize when strict alignment guaranteed. - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.MUL_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_S, "> 0", IRNode.MUL_VS, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIfAnd = {"AlignVector", "true", "MaxVectorSize", ">= 4"}, applyIfCPUFeatureAnd = {"sse4.1", "true", "avx2", "false"}) // CPU: avx2 to avx512 without avx512bw -> vector_width: 32 -> elements in vector: 16 - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.MUL_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_S, "> 0", IRNode.MUL_VS, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIfAnd = {"AlignVector", "false", "MaxVectorSize", ">= 4"}, applyIfCPUFeatureAnd = {"avx2", "true", "avx512bw", "false"}) // Vectorize when strict alignment guaranteed. - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.MUL_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_S, "> 0", IRNode.MUL_VS, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIfAnd = {"AlignVector", "true", "MaxVectorSize", ">= 4"}, applyIfCPUFeatureAnd = {"avx2", "true", "avx512bw", "false"}) // CPU: avx512bw -> vector_width: 64 -> elements in vector: 32 - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.MUL_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_S, "> 0", IRNode.MUL_VS, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIfAnd = {"AlignVector", "false", "MaxVectorSize", ">= 4"}, applyIfCPUFeature = {"avx512bw", "true"}) // Vectorize when strict alignment guaranteed. - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.MUL_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_S, "> 0", IRNode.MUL_VS, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIfAnd = {"AlignVector", "true", "MaxVectorSize", ">= 4"}, applyIfCPUFeature = {"avx512bw", "true"}) // CPU: asimd -> vector_width: 32 -> elements in vector: 16 - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.MUL_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_S, "> 0", IRNode.MUL_VS, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIfAnd = {"AlignVector", "false", "MaxVectorSize", ">= 4"}, applyIfCPUFeature = {"asimd", "true"}) // Vectorize when strict alignment guaranteed. - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.MUL_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_S, "> 0", IRNode.MUL_VS, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIfAnd = {"AlignVector", "true", "MaxVectorSize", ">= 4"}, applyIfCPUFeature = {"asimd", "true"}) public static void testShortP32(short[] data) { @@ -5147,35 +5147,35 @@ public static void runShortP32() { @Test // CPU: sse4.1 to avx -> vector_width: 16 -> elements in vector: 8 - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.MUL_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_S, "> 0", IRNode.MUL_VS, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIfAnd = {"AlignVector", "false", "MaxVectorSize", ">= 4"}, applyIfCPUFeatureAnd = {"sse4.1", "true", "avx2", "false"}) // Strict alignment not possible. - @IR(failOn = {IRNode.LOAD_VECTOR, IRNode.MUL_V, IRNode.STORE_VECTOR}, + @IR(failOn = {IRNode.LOAD_VECTOR_S, IRNode.MUL_VS, IRNode.STORE_VECTOR}, applyIf = {"AlignVector", "true"}, applyIfCPUFeatureAnd = {"sse4.1", "true", "avx2", "false"}) // CPU: avx2 to avx512 without avx512bw -> vector_width: 32 -> elements in vector: 16 - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.MUL_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_S, "> 0", IRNode.MUL_VS, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIfAnd = {"AlignVector", "false", "MaxVectorSize", ">= 4"}, applyIfCPUFeatureAnd = {"avx2", "true", "avx512bw", "false"}) // Strict alignment not possible. - @IR(failOn = {IRNode.LOAD_VECTOR, IRNode.MUL_V, IRNode.STORE_VECTOR}, + @IR(failOn = {IRNode.LOAD_VECTOR_S, IRNode.MUL_VS, IRNode.STORE_VECTOR}, applyIf = {"AlignVector", "true"}, applyIfCPUFeatureAnd = {"avx2", "true", "avx512bw", "false"}) // CPU: avx512bw -> vector_width: 64 -> elements in vector: 32 - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.MUL_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_S, "> 0", IRNode.MUL_VS, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIfAnd = {"AlignVector", "false", "MaxVectorSize", ">= 4"}, applyIfCPUFeature = {"avx512bw", "true"}) // Strict alignment not possible. - @IR(failOn = {IRNode.LOAD_VECTOR, IRNode.MUL_V, IRNode.STORE_VECTOR}, + @IR(failOn = {IRNode.LOAD_VECTOR_S, IRNode.MUL_VS, IRNode.STORE_VECTOR}, applyIf = {"AlignVector", "true"}, applyIfCPUFeature = {"avx512bw", "true"}) // CPU: asimd -> vector_width: 32 -> elements in vector: 16 - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.MUL_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_S, "> 0", IRNode.MUL_VS, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIfAnd = {"AlignVector", "false", "MaxVectorSize", ">= 4"}, applyIfCPUFeature = {"asimd", "true"}) // Strict alignment not possible. - @IR(failOn = {IRNode.LOAD_VECTOR, IRNode.MUL_V, IRNode.STORE_VECTOR}, + @IR(failOn = {IRNode.LOAD_VECTOR_S, IRNode.MUL_VS, IRNode.STORE_VECTOR}, applyIf = {"AlignVector", "true"}, applyIfCPUFeature = {"asimd", "true"}) public static void testShortM63(short[] data) { @@ -5195,19 +5195,19 @@ public static void runShortM63() { @Test // CPU: sse4.1 to avx -> vector_width: 16 -> elements in vector: 8 - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.MUL_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_S, "> 0", IRNode.MUL_VS, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIfAnd = {"AlignVector", "false", "MaxVectorSize", ">= 4"}, applyIfCPUFeatureAnd = {"sse4.1", "true", "avx2", "false"}) // CPU: avx2 to avx512 without avx512bw -> vector_width: 32 -> elements in vector: 16 - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.MUL_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_S, "> 0", IRNode.MUL_VS, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIfAnd = {"AlignVector", "false", "MaxVectorSize", ">= 4"}, applyIfCPUFeatureAnd = {"avx2", "true", "avx512bw", "false"}) // CPU: avx512bw -> vector_width: 64 -> elements in vector: 32 - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.MUL_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_S, "> 0", IRNode.MUL_VS, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIfAnd = {"AlignVector", "false", "MaxVectorSize", ">= 4"}, applyIfCPUFeature = {"avx512bw", "true"}) // CPU: asimd -> vector_width: 32 -> elements in vector: 16 - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.MUL_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_S, "> 0", IRNode.MUL_VS, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIfAnd = {"AlignVector", "false", "MaxVectorSize", ">= 4"}, applyIfCPUFeature = {"asimd", "true"}) public static void testShortP63(short[] data) { @@ -5227,19 +5227,19 @@ public static void runShortP63() { @Test // CPU: sse4.1 to avx -> vector_width: 16 -> elements in vector: 8 - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.MUL_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_S, "> 0", IRNode.MUL_VS, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIfAnd = {"AlignVector", "false", "MaxVectorSize", ">= 4"}, applyIfCPUFeatureAnd = {"sse4.1", "true", "avx2", "false"}) // CPU: avx2 to avx512 without avx512bw -> vector_width: 32 -> elements in vector: 16 - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.MUL_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_S, "> 0", IRNode.MUL_VS, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIfAnd = {"AlignVector", "false", "MaxVectorSize", ">= 4"}, applyIfCPUFeatureAnd = {"avx2", "true", "avx512bw", "false"}) // CPU: avx512bw -> vector_width: 64 -> elements in vector: 32 - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.MUL_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_S, "> 0", IRNode.MUL_VS, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIfAnd = {"AlignVector", "false", "MaxVectorSize", ">= 4"}, applyIfCPUFeature = {"avx512bw", "true"}) // CPU: asimd -> vector_width: 32 -> elements in vector: 16 - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.MUL_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_S, "> 0", IRNode.MUL_VS, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIfAnd = {"AlignVector", "false", "MaxVectorSize", ">= 4"}, applyIfCPUFeature = {"asimd", "true"}) public static void testShortM64(short[] data) { @@ -5259,35 +5259,35 @@ public static void runShortM64() { @Test // CPU: sse4.1 to avx -> vector_width: 16 -> elements in vector: 8 - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.MUL_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_S, "> 0", IRNode.MUL_VS, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIfAnd = {"AlignVector", "false", "MaxVectorSize", ">= 4"}, applyIfCPUFeatureAnd = {"sse4.1", "true", "avx2", "false"}) // Vectorize when strict alignment guaranteed. - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.MUL_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_S, "> 0", IRNode.MUL_VS, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIfAnd = {"AlignVector", "true", "MaxVectorSize", ">= 4"}, applyIfCPUFeatureAnd = {"sse4.1", "true", "avx2", "false"}) // CPU: avx2 to avx512 without avx512bw -> vector_width: 32 -> elements in vector: 16 - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.MUL_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_S, "> 0", IRNode.MUL_VS, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIfAnd = {"AlignVector", "false", "MaxVectorSize", ">= 4"}, applyIfCPUFeatureAnd = {"avx2", "true", "avx512bw", "false"}) // Vectorize when strict alignment guaranteed. - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.MUL_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_S, "> 0", IRNode.MUL_VS, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIfAnd = {"AlignVector", "true", "MaxVectorSize", ">= 4"}, applyIfCPUFeatureAnd = {"avx2", "true", "avx512bw", "false"}) // CPU: avx512bw -> vector_width: 64 -> elements in vector: 32 - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.MUL_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_S, "> 0", IRNode.MUL_VS, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIfAnd = {"AlignVector", "false", "MaxVectorSize", ">= 4"}, applyIfCPUFeature = {"avx512bw", "true"}) // Vectorize when strict alignment guaranteed. - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.MUL_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_S, "> 0", IRNode.MUL_VS, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIfAnd = {"AlignVector", "true", "MaxVectorSize", ">= 4"}, applyIfCPUFeature = {"avx512bw", "true"}) // CPU: asimd -> vector_width: 32 -> elements in vector: 16 - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.MUL_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_S, "> 0", IRNode.MUL_VS, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIfAnd = {"AlignVector", "false", "MaxVectorSize", ">= 4"}, applyIfCPUFeature = {"asimd", "true"}) // Vectorize when strict alignment guaranteed. - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.MUL_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_S, "> 0", IRNode.MUL_VS, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIfAnd = {"AlignVector", "true", "MaxVectorSize", ">= 4"}, applyIfCPUFeature = {"asimd", "true"}) public static void testShortP64(short[] data) { @@ -5307,35 +5307,35 @@ public static void runShortP64() { @Test // CPU: sse4.1 to avx -> vector_width: 16 -> elements in vector: 8 - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.MUL_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_S, "> 0", IRNode.MUL_VS, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIfAnd = {"AlignVector", "false", "MaxVectorSize", ">= 4"}, applyIfCPUFeatureAnd = {"sse4.1", "true", "avx2", "false"}) // Strict alignment not possible. - @IR(failOn = {IRNode.LOAD_VECTOR, IRNode.MUL_V, IRNode.STORE_VECTOR}, + @IR(failOn = {IRNode.LOAD_VECTOR_S, IRNode.MUL_VS, IRNode.STORE_VECTOR}, applyIf = {"AlignVector", "true"}, applyIfCPUFeatureAnd = {"sse4.1", "true", "avx2", "false"}) // CPU: avx2 to avx512 without avx512bw -> vector_width: 32 -> elements in vector: 16 - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.MUL_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_S, "> 0", IRNode.MUL_VS, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIfAnd = {"AlignVector", "false", "MaxVectorSize", ">= 4"}, applyIfCPUFeatureAnd = {"avx2", "true", "avx512bw", "false"}) // Strict alignment not possible. - @IR(failOn = {IRNode.LOAD_VECTOR, IRNode.MUL_V, IRNode.STORE_VECTOR}, + @IR(failOn = {IRNode.LOAD_VECTOR_S, IRNode.MUL_VS, IRNode.STORE_VECTOR}, applyIf = {"AlignVector", "true"}, applyIfCPUFeatureAnd = {"avx2", "true", "avx512bw", "false"}) // CPU: avx512bw -> vector_width: 64 -> elements in vector: 32 - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.MUL_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_S, "> 0", IRNode.MUL_VS, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIfAnd = {"AlignVector", "false", "MaxVectorSize", ">= 4"}, applyIfCPUFeature = {"avx512bw", "true"}) // Strict alignment not possible. - @IR(failOn = {IRNode.LOAD_VECTOR, IRNode.MUL_V, IRNode.STORE_VECTOR}, + @IR(failOn = {IRNode.LOAD_VECTOR_S, IRNode.MUL_VS, IRNode.STORE_VECTOR}, applyIf = {"AlignVector", "true"}, applyIfCPUFeature = {"avx512bw", "true"}) // CPU: asimd -> vector_width: 32 -> elements in vector: 16 - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.MUL_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_S, "> 0", IRNode.MUL_VS, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIfAnd = {"AlignVector", "false", "MaxVectorSize", ">= 4"}, applyIfCPUFeature = {"asimd", "true"}) // Strict alignment not possible. - @IR(failOn = {IRNode.LOAD_VECTOR, IRNode.MUL_V, IRNode.STORE_VECTOR}, + @IR(failOn = {IRNode.LOAD_VECTOR_S, IRNode.MUL_VS, IRNode.STORE_VECTOR}, applyIf = {"AlignVector", "true"}, applyIfCPUFeature = {"asimd", "true"}) public static void testShortM65(short[] data) { @@ -5355,19 +5355,19 @@ public static void runShortM65() { @Test // CPU: sse4.1 to avx -> vector_width: 16 -> elements in vector: 8 - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.MUL_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_S, "> 0", IRNode.MUL_VS, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIfAnd = {"AlignVector", "false", "MaxVectorSize", ">= 4"}, applyIfCPUFeatureAnd = {"sse4.1", "true", "avx2", "false"}) // CPU: avx2 to avx512 without avx512bw -> vector_width: 32 -> elements in vector: 16 - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.MUL_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_S, "> 0", IRNode.MUL_VS, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIfAnd = {"AlignVector", "false", "MaxVectorSize", ">= 4"}, applyIfCPUFeatureAnd = {"avx2", "true", "avx512bw", "false"}) // CPU: avx512bw -> vector_width: 64 -> elements in vector: 32 - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.MUL_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_S, "> 0", IRNode.MUL_VS, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIfAnd = {"AlignVector", "false", "MaxVectorSize", ">= 4"}, applyIfCPUFeature = {"avx512bw", "true"}) // CPU: asimd -> vector_width: 32 -> elements in vector: 16 - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.MUL_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_S, "> 0", IRNode.MUL_VS, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIfAnd = {"AlignVector", "false", "MaxVectorSize", ">= 4"}, applyIfCPUFeature = {"asimd", "true"}) public static void testShortP65(short[] data) { @@ -5387,19 +5387,19 @@ public static void runShortP65() { @Test // CPU: sse4.1 to avx -> vector_width: 16 -> elements in vector: 8 - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.MUL_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_S, "> 0", IRNode.MUL_VS, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIfAnd = {"AlignVector", "false", "MaxVectorSize", ">= 4"}, applyIfCPUFeatureAnd = {"sse4.1", "true", "avx2", "false"}) // CPU: avx2 to avx512 without avx512bw -> vector_width: 32 -> elements in vector: 16 - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.MUL_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_S, "> 0", IRNode.MUL_VS, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIfAnd = {"AlignVector", "false", "MaxVectorSize", ">= 4"}, applyIfCPUFeatureAnd = {"avx2", "true", "avx512bw", "false"}) // CPU: avx512bw -> vector_width: 64 -> elements in vector: 32 - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.MUL_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_S, "> 0", IRNode.MUL_VS, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIfAnd = {"AlignVector", "false", "MaxVectorSize", ">= 4"}, applyIfCPUFeature = {"avx512bw", "true"}) // CPU: asimd -> vector_width: 32 -> elements in vector: 16 - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.MUL_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_S, "> 0", IRNode.MUL_VS, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIfAnd = {"AlignVector", "false", "MaxVectorSize", ">= 4"}, applyIfCPUFeature = {"asimd", "true"}) public static void testShortM128(short[] data) { @@ -5419,35 +5419,35 @@ public static void runShortM128() { @Test // CPU: sse4.1 to avx -> vector_width: 16 -> elements in vector: 8 - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.MUL_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_S, "> 0", IRNode.MUL_VS, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIfAnd = {"AlignVector", "false", "MaxVectorSize", ">= 4"}, applyIfCPUFeatureAnd = {"sse4.1", "true", "avx2", "false"}) // Vectorize when strict alignment guaranteed. - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.MUL_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_S, "> 0", IRNode.MUL_VS, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIfAnd = {"AlignVector", "true", "MaxVectorSize", ">= 4"}, applyIfCPUFeatureAnd = {"sse4.1", "true", "avx2", "false"}) // CPU: avx2 to avx512 without avx512bw -> vector_width: 32 -> elements in vector: 16 - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.MUL_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_S, "> 0", IRNode.MUL_VS, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIfAnd = {"AlignVector", "false", "MaxVectorSize", ">= 4"}, applyIfCPUFeatureAnd = {"avx2", "true", "avx512bw", "false"}) // Vectorize when strict alignment guaranteed. - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.MUL_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_S, "> 0", IRNode.MUL_VS, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIfAnd = {"AlignVector", "true", "MaxVectorSize", ">= 4"}, applyIfCPUFeatureAnd = {"avx2", "true", "avx512bw", "false"}) // CPU: avx512bw -> vector_width: 64 -> elements in vector: 32 - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.MUL_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_S, "> 0", IRNode.MUL_VS, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIfAnd = {"AlignVector", "false", "MaxVectorSize", ">= 4"}, applyIfCPUFeature = {"avx512bw", "true"}) // Vectorize when strict alignment guaranteed. - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.MUL_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_S, "> 0", IRNode.MUL_VS, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIfAnd = {"AlignVector", "true", "MaxVectorSize", ">= 4"}, applyIfCPUFeature = {"avx512bw", "true"}) // CPU: asimd -> vector_width: 32 -> elements in vector: 16 - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.MUL_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_S, "> 0", IRNode.MUL_VS, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIfAnd = {"AlignVector", "false", "MaxVectorSize", ">= 4"}, applyIfCPUFeature = {"asimd", "true"}) // Vectorize when strict alignment guaranteed. - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.MUL_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_S, "> 0", IRNode.MUL_VS, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIfAnd = {"AlignVector", "true", "MaxVectorSize", ">= 4"}, applyIfCPUFeature = {"asimd", "true"}) public static void testShortP128(short[] data) { @@ -5467,35 +5467,35 @@ public static void runShortP128() { @Test // CPU: sse4.1 to avx -> vector_width: 16 -> elements in vector: 8 - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.MUL_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_S, "> 0", IRNode.MUL_VS, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIfAnd = {"AlignVector", "false", "MaxVectorSize", ">= 4"}, applyIfCPUFeatureAnd = {"sse4.1", "true", "avx2", "false"}) // Strict alignment not possible. - @IR(failOn = {IRNode.LOAD_VECTOR, IRNode.MUL_V, IRNode.STORE_VECTOR}, + @IR(failOn = {IRNode.LOAD_VECTOR_S, IRNode.MUL_VS, IRNode.STORE_VECTOR}, applyIf = {"AlignVector", "true"}, applyIfCPUFeatureAnd = {"sse4.1", "true", "avx2", "false"}) // CPU: avx2 to avx512 without avx512bw -> vector_width: 32 -> elements in vector: 16 - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.MUL_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_S, "> 0", IRNode.MUL_VS, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIfAnd = {"AlignVector", "false", "MaxVectorSize", ">= 4"}, applyIfCPUFeatureAnd = {"avx2", "true", "avx512bw", "false"}) // Strict alignment not possible. - @IR(failOn = {IRNode.LOAD_VECTOR, IRNode.MUL_V, IRNode.STORE_VECTOR}, + @IR(failOn = {IRNode.LOAD_VECTOR_S, IRNode.MUL_VS, IRNode.STORE_VECTOR}, applyIf = {"AlignVector", "true"}, applyIfCPUFeatureAnd = {"avx2", "true", "avx512bw", "false"}) // CPU: avx512bw -> vector_width: 64 -> elements in vector: 32 - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.MUL_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_S, "> 0", IRNode.MUL_VS, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIfAnd = {"AlignVector", "false", "MaxVectorSize", ">= 4"}, applyIfCPUFeature = {"avx512bw", "true"}) // Strict alignment not possible. - @IR(failOn = {IRNode.LOAD_VECTOR, IRNode.MUL_V, IRNode.STORE_VECTOR}, + @IR(failOn = {IRNode.LOAD_VECTOR_S, IRNode.MUL_VS, IRNode.STORE_VECTOR}, applyIf = {"AlignVector", "true"}, applyIfCPUFeature = {"avx512bw", "true"}) // CPU: asimd -> vector_width: 32 -> elements in vector: 16 - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.MUL_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_S, "> 0", IRNode.MUL_VS, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIfAnd = {"AlignVector", "false", "MaxVectorSize", ">= 4"}, applyIfCPUFeature = {"asimd", "true"}) // Strict alignment not possible. - @IR(failOn = {IRNode.LOAD_VECTOR, IRNode.MUL_V, IRNode.STORE_VECTOR}, + @IR(failOn = {IRNode.LOAD_VECTOR_S, IRNode.MUL_VS, IRNode.STORE_VECTOR}, applyIf = {"AlignVector", "true"}, applyIfCPUFeature = {"asimd", "true"}) public static void testShortM129(short[] data) { @@ -5515,19 +5515,19 @@ public static void runShortM129() { @Test // CPU: sse4.1 to avx -> vector_width: 16 -> elements in vector: 8 - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.MUL_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_S, "> 0", IRNode.MUL_VS, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIfAnd = {"AlignVector", "false", "MaxVectorSize", ">= 4"}, applyIfCPUFeatureAnd = {"sse4.1", "true", "avx2", "false"}) // CPU: avx2 to avx512 without avx512bw -> vector_width: 32 -> elements in vector: 16 - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.MUL_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_S, "> 0", IRNode.MUL_VS, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIfAnd = {"AlignVector", "false", "MaxVectorSize", ">= 4"}, applyIfCPUFeatureAnd = {"avx2", "true", "avx512bw", "false"}) // CPU: avx512bw -> vector_width: 64 -> elements in vector: 32 - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.MUL_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_S, "> 0", IRNode.MUL_VS, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIfAnd = {"AlignVector", "false", "MaxVectorSize", ">= 4"}, applyIfCPUFeature = {"avx512bw", "true"}) // CPU: asimd -> vector_width: 32 -> elements in vector: 16 - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.MUL_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_S, "> 0", IRNode.MUL_VS, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIfAnd = {"AlignVector", "false", "MaxVectorSize", ">= 4"}, applyIfCPUFeature = {"asimd", "true"}) public static void testShortP129(short[] data) { @@ -5547,19 +5547,19 @@ public static void runShortP129() { @Test // CPU: sse4.1 to avx -> vector_width: 16 -> elements in vector: 8 - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.MUL_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_S, "> 0", IRNode.MUL_VS, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIfAnd = {"AlignVector", "false", "MaxVectorSize", ">= 4"}, applyIfCPUFeatureAnd = {"sse4.1", "true", "avx2", "false"}) // CPU: avx2 to avx512 without avx512bw -> vector_width: 32 -> elements in vector: 16 - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.MUL_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_S, "> 0", IRNode.MUL_VS, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIfAnd = {"AlignVector", "false", "MaxVectorSize", ">= 4"}, applyIfCPUFeatureAnd = {"avx2", "true", "avx512bw", "false"}) // CPU: avx512bw -> vector_width: 64 -> elements in vector: 32 - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.MUL_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_S, "> 0", IRNode.MUL_VS, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIfAnd = {"AlignVector", "false", "MaxVectorSize", ">= 4"}, applyIfCPUFeature = {"avx512bw", "true"}) // CPU: asimd -> vector_width: 32 -> elements in vector: 16 - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.MUL_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_S, "> 0", IRNode.MUL_VS, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIfAnd = {"AlignVector", "false", "MaxVectorSize", ">= 4"}, applyIfCPUFeature = {"asimd", "true"}) public static void testShortM192(short[] data) { @@ -5579,35 +5579,35 @@ public static void runShortM192() { @Test // CPU: sse4.1 to avx -> vector_width: 16 -> elements in vector: 8 - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.MUL_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_S, "> 0", IRNode.MUL_VS, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIfAnd = {"AlignVector", "false", "MaxVectorSize", ">= 4"}, applyIfCPUFeatureAnd = {"sse4.1", "true", "avx2", "false"}) // Vectorize when strict alignment guaranteed. - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.MUL_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_S, "> 0", IRNode.MUL_VS, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIfAnd = {"AlignVector", "true", "MaxVectorSize", ">= 4"}, applyIfCPUFeatureAnd = {"sse4.1", "true", "avx2", "false"}) // CPU: avx2 to avx512 without avx512bw -> vector_width: 32 -> elements in vector: 16 - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.MUL_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_S, "> 0", IRNode.MUL_VS, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIfAnd = {"AlignVector", "false", "MaxVectorSize", ">= 4"}, applyIfCPUFeatureAnd = {"avx2", "true", "avx512bw", "false"}) // Vectorize when strict alignment guaranteed. - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.MUL_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_S, "> 0", IRNode.MUL_VS, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIfAnd = {"AlignVector", "true", "MaxVectorSize", ">= 4"}, applyIfCPUFeatureAnd = {"avx2", "true", "avx512bw", "false"}) // CPU: avx512bw -> vector_width: 64 -> elements in vector: 32 - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.MUL_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_S, "> 0", IRNode.MUL_VS, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIfAnd = {"AlignVector", "false", "MaxVectorSize", ">= 4"}, applyIfCPUFeature = {"avx512bw", "true"}) // Vectorize when strict alignment guaranteed. - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.MUL_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_S, "> 0", IRNode.MUL_VS, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIfAnd = {"AlignVector", "true", "MaxVectorSize", ">= 4"}, applyIfCPUFeature = {"avx512bw", "true"}) // CPU: asimd -> vector_width: 32 -> elements in vector: 16 - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.MUL_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_S, "> 0", IRNode.MUL_VS, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIfAnd = {"AlignVector", "false", "MaxVectorSize", ">= 4"}, applyIfCPUFeature = {"asimd", "true"}) // Vectorize when strict alignment guaranteed. - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.MUL_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_S, "> 0", IRNode.MUL_VS, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIfAnd = {"AlignVector", "true", "MaxVectorSize", ">= 4"}, applyIfCPUFeature = {"asimd", "true"}) public static void testShortP192(short[] data) { @@ -5627,19 +5627,19 @@ public static void runShortP192() { @Test // CPU: sse4.1 to avx -> vector_width: 16 -> elements in vector: 8 - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.MUL_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_C, "> 0", IRNode.MUL_VS, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIfAnd = {"AlignVector", "false", "MaxVectorSize", ">= 4"}, applyIfCPUFeatureAnd = {"sse4.1", "true", "avx2", "false"}) // CPU: avx2 to avx512 without avx512bw -> vector_width: 32 -> elements in vector: 16 - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.MUL_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_C, "> 0", IRNode.MUL_VS, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIfAnd = {"AlignVector", "false", "MaxVectorSize", ">= 4"}, applyIfCPUFeatureAnd = {"avx2", "true", "avx512bw", "false"}) // CPU: avx512bw -> vector_width: 64 -> elements in vector: 32 - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.MUL_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_C, "> 0", IRNode.MUL_VS, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIfAnd = {"AlignVector", "false", "MaxVectorSize", ">= 4"}, applyIfCPUFeature = {"avx512bw", "true"}) // CPU: asimd -> vector_width: 32 -> elements in vector: 16 - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.MUL_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_C, "> 0", IRNode.MUL_VS, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIfAnd = {"AlignVector", "false", "MaxVectorSize", ">= 4"}, applyIfCPUFeature = {"asimd", "true"}) public static void testCharP0(char[] data) { @@ -5659,35 +5659,35 @@ public static void runCharP0() { @Test // CPU: sse4.1 to avx -> vector_width: 16 -> elements in vector: 8 - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.MUL_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_C, "> 0", IRNode.MUL_VS, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIfAnd = {"AlignVector", "false", "MaxVectorSize", ">= 4"}, applyIfCPUFeatureAnd = {"sse4.1", "true", "avx2", "false"}) // Strict alignment not possible. - @IR(failOn = {IRNode.LOAD_VECTOR, IRNode.MUL_V, IRNode.STORE_VECTOR}, + @IR(failOn = {IRNode.LOAD_VECTOR_C, IRNode.MUL_VS, IRNode.STORE_VECTOR}, applyIf = {"AlignVector", "true"}, applyIfCPUFeatureAnd = {"sse4.1", "true", "avx2", "false"}) // CPU: avx2 to avx512 without avx512bw -> vector_width: 32 -> elements in vector: 16 - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.MUL_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_C, "> 0", IRNode.MUL_VS, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIfAnd = {"AlignVector", "false", "MaxVectorSize", ">= 4"}, applyIfCPUFeatureAnd = {"avx2", "true", "avx512bw", "false"}) // Strict alignment not possible. - @IR(failOn = {IRNode.LOAD_VECTOR, IRNode.MUL_V, IRNode.STORE_VECTOR}, + @IR(failOn = {IRNode.LOAD_VECTOR_C, IRNode.MUL_VS, IRNode.STORE_VECTOR}, applyIf = {"AlignVector", "true"}, applyIfCPUFeatureAnd = {"avx2", "true", "avx512bw", "false"}) // CPU: avx512bw -> vector_width: 64 -> elements in vector: 32 - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.MUL_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_C, "> 0", IRNode.MUL_VS, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIfAnd = {"AlignVector", "false", "MaxVectorSize", ">= 4"}, applyIfCPUFeature = {"avx512bw", "true"}) // Strict alignment not possible. - @IR(failOn = {IRNode.LOAD_VECTOR, IRNode.MUL_V, IRNode.STORE_VECTOR}, + @IR(failOn = {IRNode.LOAD_VECTOR_C, IRNode.MUL_VS, IRNode.STORE_VECTOR}, applyIf = {"AlignVector", "true"}, applyIfCPUFeature = {"avx512bw", "true"}) // CPU: asimd -> vector_width: 32 -> elements in vector: 16 - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.MUL_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_C, "> 0", IRNode.MUL_VS, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIfAnd = {"AlignVector", "false", "MaxVectorSize", ">= 4"}, applyIfCPUFeature = {"asimd", "true"}) // Strict alignment not possible. - @IR(failOn = {IRNode.LOAD_VECTOR, IRNode.MUL_V, IRNode.STORE_VECTOR}, + @IR(failOn = {IRNode.LOAD_VECTOR_C, IRNode.MUL_VS, IRNode.STORE_VECTOR}, applyIf = {"AlignVector", "true"}, applyIfCPUFeature = {"asimd", "true"}) public static void testCharM1(char[] data) { @@ -5735,19 +5735,19 @@ public static void runCharP1() { @Test // CPU: sse4.1 to avx -> vector_width: 16 -> elements in vector: 8 - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.MUL_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_C, "> 0", IRNode.MUL_VS, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIfAnd = {"AlignVector", "false", "MaxVectorSize", ">= 4"}, applyIfCPUFeatureAnd = {"sse4.1", "true", "avx2", "false"}) // CPU: avx2 to avx512 without avx512bw -> vector_width: 32 -> elements in vector: 16 - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.MUL_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_C, "> 0", IRNode.MUL_VS, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIfAnd = {"AlignVector", "false", "MaxVectorSize", ">= 4"}, applyIfCPUFeatureAnd = {"avx2", "true", "avx512bw", "false"}) // CPU: avx512bw -> vector_width: 64 -> elements in vector: 32 - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.MUL_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_C, "> 0", IRNode.MUL_VS, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIfAnd = {"AlignVector", "false", "MaxVectorSize", ">= 4"}, applyIfCPUFeature = {"avx512bw", "true"}) // CPU: asimd -> vector_width: 32 -> elements in vector: 16 - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.MUL_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_C, "> 0", IRNode.MUL_VS, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIfAnd = {"AlignVector", "false", "MaxVectorSize", ">= 4"}, applyIfCPUFeature = {"asimd", "true"}) public static void testCharM2(char[] data) { @@ -5768,22 +5768,22 @@ public static void runCharM2() { @Test // CPU: sse4.1 to avx -> vector_width: 16 -> elements in vector: 8 // positive byte_offset 4 can lead to cyclic dependency - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.MUL_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_C, "> 0", IRNode.MUL_VS, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIfAnd = {"AlignVector", "false", "MaxVectorSize", ">= 4", "MaxVectorSize", "<= 4"}, applyIfCPUFeatureAnd = {"sse4.1", "true", "avx2", "false"}) // CPU: avx2 to avx512 without avx512bw -> vector_width: 32 -> elements in vector: 16 // positive byte_offset 4 can lead to cyclic dependency - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.MUL_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_C, "> 0", IRNode.MUL_VS, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIfAnd = {"AlignVector", "false", "MaxVectorSize", ">= 4", "MaxVectorSize", "<= 4"}, applyIfCPUFeatureAnd = {"avx2", "true", "avx512bw", "false"}) // CPU: avx512bw -> vector_width: 64 -> elements in vector: 32 // positive byte_offset 4 can lead to cyclic dependency - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.MUL_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_C, "> 0", IRNode.MUL_VS, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIfAnd = {"AlignVector", "false", "MaxVectorSize", ">= 4", "MaxVectorSize", "<= 4"}, applyIfCPUFeature = {"avx512bw", "true"}) // CPU: asimd -> vector_width: 32 -> elements in vector: 16 // positive byte_offset 4 can lead to cyclic dependency - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.MUL_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_C, "> 0", IRNode.MUL_VS, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIfAnd = {"AlignVector", "false", "MaxVectorSize", ">= 4", "MaxVectorSize", "<= 4"}, applyIfCPUFeature = {"asimd", "true"}) public static void testCharP2(char[] data) { @@ -5803,35 +5803,35 @@ public static void runCharP2() { @Test // CPU: sse4.1 to avx -> vector_width: 16 -> elements in vector: 8 - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.MUL_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_C, "> 0", IRNode.MUL_VS, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIfAnd = {"AlignVector", "false", "MaxVectorSize", ">= 4"}, applyIfCPUFeatureAnd = {"sse4.1", "true", "avx2", "false"}) // Strict alignment not possible. - @IR(failOn = {IRNode.LOAD_VECTOR, IRNode.MUL_V, IRNode.STORE_VECTOR}, + @IR(failOn = {IRNode.LOAD_VECTOR_C, IRNode.MUL_VS, IRNode.STORE_VECTOR}, applyIf = {"AlignVector", "true"}, applyIfCPUFeatureAnd = {"sse4.1", "true", "avx2", "false"}) // CPU: avx2 to avx512 without avx512bw -> vector_width: 32 -> elements in vector: 16 - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.MUL_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_C, "> 0", IRNode.MUL_VS, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIfAnd = {"AlignVector", "false", "MaxVectorSize", ">= 4"}, applyIfCPUFeatureAnd = {"avx2", "true", "avx512bw", "false"}) // Strict alignment not possible. - @IR(failOn = {IRNode.LOAD_VECTOR, IRNode.MUL_V, IRNode.STORE_VECTOR}, + @IR(failOn = {IRNode.LOAD_VECTOR_C, IRNode.MUL_VS, IRNode.STORE_VECTOR}, applyIf = {"AlignVector", "true"}, applyIfCPUFeatureAnd = {"avx2", "true", "avx512bw", "false"}) // CPU: avx512bw -> vector_width: 64 -> elements in vector: 32 - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.MUL_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_C, "> 0", IRNode.MUL_VS, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIfAnd = {"AlignVector", "false", "MaxVectorSize", ">= 4"}, applyIfCPUFeature = {"avx512bw", "true"}) // Strict alignment not possible. - @IR(failOn = {IRNode.LOAD_VECTOR, IRNode.MUL_V, IRNode.STORE_VECTOR}, + @IR(failOn = {IRNode.LOAD_VECTOR_C, IRNode.MUL_VS, IRNode.STORE_VECTOR}, applyIf = {"AlignVector", "true"}, applyIfCPUFeature = {"avx512bw", "true"}) // CPU: asimd -> vector_width: 32 -> elements in vector: 16 - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.MUL_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_C, "> 0", IRNode.MUL_VS, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIfAnd = {"AlignVector", "false", "MaxVectorSize", ">= 4"}, applyIfCPUFeature = {"asimd", "true"}) // Strict alignment not possible. - @IR(failOn = {IRNode.LOAD_VECTOR, IRNode.MUL_V, IRNode.STORE_VECTOR}, + @IR(failOn = {IRNode.LOAD_VECTOR_C, IRNode.MUL_VS, IRNode.STORE_VECTOR}, applyIf = {"AlignVector", "true"}, applyIfCPUFeature = {"asimd", "true"}) public static void testCharM3(char[] data) { @@ -5852,22 +5852,22 @@ public static void runCharM3() { @Test // CPU: sse4.1 to avx -> vector_width: 16 -> elements in vector: 8 // positive byte_offset 6 can lead to cyclic dependency - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.MUL_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_C, "> 0", IRNode.MUL_VS, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIfAnd = {"AlignVector", "false", "MaxVectorSize", ">= 4", "MaxVectorSize", "<= 6"}, applyIfCPUFeatureAnd = {"sse4.1", "true", "avx2", "false"}) // CPU: avx2 to avx512 without avx512bw -> vector_width: 32 -> elements in vector: 16 // positive byte_offset 6 can lead to cyclic dependency - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.MUL_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_C, "> 0", IRNode.MUL_VS, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIfAnd = {"AlignVector", "false", "MaxVectorSize", ">= 4", "MaxVectorSize", "<= 6"}, applyIfCPUFeatureAnd = {"avx2", "true", "avx512bw", "false"}) // CPU: avx512bw -> vector_width: 64 -> elements in vector: 32 // positive byte_offset 6 can lead to cyclic dependency - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.MUL_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_C, "> 0", IRNode.MUL_VS, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIfAnd = {"AlignVector", "false", "MaxVectorSize", ">= 4", "MaxVectorSize", "<= 6"}, applyIfCPUFeature = {"avx512bw", "true"}) // CPU: asimd -> vector_width: 32 -> elements in vector: 16 // positive byte_offset 6 can lead to cyclic dependency - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.MUL_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_C, "> 0", IRNode.MUL_VS, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIfAnd = {"AlignVector", "false", "MaxVectorSize", ">= 4", "MaxVectorSize", "<= 6"}, applyIfCPUFeature = {"asimd", "true"}) public static void testCharP3(char[] data) { @@ -5887,19 +5887,19 @@ public static void runCharP3() { @Test // CPU: sse4.1 to avx -> vector_width: 16 -> elements in vector: 8 - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.MUL_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_C, "> 0", IRNode.MUL_VS, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIfAnd = {"AlignVector", "false", "MaxVectorSize", ">= 4"}, applyIfCPUFeatureAnd = {"sse4.1", "true", "avx2", "false"}) // CPU: avx2 to avx512 without avx512bw -> vector_width: 32 -> elements in vector: 16 - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.MUL_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_C, "> 0", IRNode.MUL_VS, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIfAnd = {"AlignVector", "false", "MaxVectorSize", ">= 4"}, applyIfCPUFeatureAnd = {"avx2", "true", "avx512bw", "false"}) // CPU: avx512bw -> vector_width: 64 -> elements in vector: 32 - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.MUL_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_C, "> 0", IRNode.MUL_VS, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIfAnd = {"AlignVector", "false", "MaxVectorSize", ">= 4"}, applyIfCPUFeature = {"avx512bw", "true"}) // CPU: asimd -> vector_width: 32 -> elements in vector: 16 - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.MUL_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_C, "> 0", IRNode.MUL_VS, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIfAnd = {"AlignVector", "false", "MaxVectorSize", ">= 4"}, applyIfCPUFeature = {"asimd", "true"}) public static void testCharM4(char[] data) { @@ -5920,22 +5920,22 @@ public static void runCharM4() { @Test // CPU: sse4.1 to avx -> vector_width: 16 -> elements in vector: 8 // positive byte_offset 8 can lead to cyclic dependency - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.MUL_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_C, "> 0", IRNode.MUL_VS, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIfAnd = {"AlignVector", "false", "MaxVectorSize", ">= 4", "MaxVectorSize", "<= 8"}, applyIfCPUFeatureAnd = {"sse4.1", "true", "avx2", "false"}) // CPU: avx2 to avx512 without avx512bw -> vector_width: 32 -> elements in vector: 16 // positive byte_offset 8 can lead to cyclic dependency - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.MUL_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_C, "> 0", IRNode.MUL_VS, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIfAnd = {"AlignVector", "false", "MaxVectorSize", ">= 4", "MaxVectorSize", "<= 8"}, applyIfCPUFeatureAnd = {"avx2", "true", "avx512bw", "false"}) // CPU: avx512bw -> vector_width: 64 -> elements in vector: 32 // positive byte_offset 8 can lead to cyclic dependency - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.MUL_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_C, "> 0", IRNode.MUL_VS, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIfAnd = {"AlignVector", "false", "MaxVectorSize", ">= 4", "MaxVectorSize", "<= 8"}, applyIfCPUFeature = {"avx512bw", "true"}) // CPU: asimd -> vector_width: 32 -> elements in vector: 16 // positive byte_offset 8 can lead to cyclic dependency - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.MUL_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_C, "> 0", IRNode.MUL_VS, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIfAnd = {"AlignVector", "false", "MaxVectorSize", ">= 4", "MaxVectorSize", "<= 8"}, applyIfCPUFeature = {"asimd", "true"}) public static void testCharP4(char[] data) { @@ -5955,35 +5955,35 @@ public static void runCharP4() { @Test // CPU: sse4.1 to avx -> vector_width: 16 -> elements in vector: 8 - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.MUL_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_C, "> 0", IRNode.MUL_VS, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIfAnd = {"AlignVector", "false", "MaxVectorSize", ">= 4"}, applyIfCPUFeatureAnd = {"sse4.1", "true", "avx2", "false"}) // Strict alignment not possible. - @IR(failOn = {IRNode.LOAD_VECTOR, IRNode.MUL_V, IRNode.STORE_VECTOR}, + @IR(failOn = {IRNode.LOAD_VECTOR_C, IRNode.MUL_VS, IRNode.STORE_VECTOR}, applyIf = {"AlignVector", "true"}, applyIfCPUFeatureAnd = {"sse4.1", "true", "avx2", "false"}) // CPU: avx2 to avx512 without avx512bw -> vector_width: 32 -> elements in vector: 16 - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.MUL_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_C, "> 0", IRNode.MUL_VS, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIfAnd = {"AlignVector", "false", "MaxVectorSize", ">= 4"}, applyIfCPUFeatureAnd = {"avx2", "true", "avx512bw", "false"}) // Strict alignment not possible. - @IR(failOn = {IRNode.LOAD_VECTOR, IRNode.MUL_V, IRNode.STORE_VECTOR}, + @IR(failOn = {IRNode.LOAD_VECTOR_C, IRNode.MUL_VS, IRNode.STORE_VECTOR}, applyIf = {"AlignVector", "true"}, applyIfCPUFeatureAnd = {"avx2", "true", "avx512bw", "false"}) // CPU: avx512bw -> vector_width: 64 -> elements in vector: 32 - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.MUL_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_C, "> 0", IRNode.MUL_VS, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIfAnd = {"AlignVector", "false", "MaxVectorSize", ">= 4"}, applyIfCPUFeature = {"avx512bw", "true"}) // Strict alignment not possible. - @IR(failOn = {IRNode.LOAD_VECTOR, IRNode.MUL_V, IRNode.STORE_VECTOR}, + @IR(failOn = {IRNode.LOAD_VECTOR_C, IRNode.MUL_VS, IRNode.STORE_VECTOR}, applyIf = {"AlignVector", "true"}, applyIfCPUFeature = {"avx512bw", "true"}) // CPU: asimd -> vector_width: 32 -> elements in vector: 16 - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.MUL_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_C, "> 0", IRNode.MUL_VS, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIfAnd = {"AlignVector", "false", "MaxVectorSize", ">= 4"}, applyIfCPUFeature = {"asimd", "true"}) // Strict alignment not possible. - @IR(failOn = {IRNode.LOAD_VECTOR, IRNode.MUL_V, IRNode.STORE_VECTOR}, + @IR(failOn = {IRNode.LOAD_VECTOR_C, IRNode.MUL_VS, IRNode.STORE_VECTOR}, applyIf = {"AlignVector", "true"}, applyIfCPUFeature = {"asimd", "true"}) public static void testCharM7(char[] data) { @@ -6004,22 +6004,22 @@ public static void runCharM7() { @Test // CPU: sse4.1 to avx -> vector_width: 16 -> elements in vector: 8 // positive byte_offset 14 can lead to cyclic dependency - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.MUL_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_C, "> 0", IRNode.MUL_VS, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIfAnd = {"AlignVector", "false", "MaxVectorSize", ">= 4", "MaxVectorSize", "<= 14"}, applyIfCPUFeatureAnd = {"sse4.1", "true", "avx2", "false"}) // CPU: avx2 to avx512 without avx512bw -> vector_width: 32 -> elements in vector: 16 // positive byte_offset 14 can lead to cyclic dependency - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.MUL_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_C, "> 0", IRNode.MUL_VS, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIfAnd = {"AlignVector", "false", "MaxVectorSize", ">= 4", "MaxVectorSize", "<= 14"}, applyIfCPUFeatureAnd = {"avx2", "true", "avx512bw", "false"}) // CPU: avx512bw -> vector_width: 64 -> elements in vector: 32 // positive byte_offset 14 can lead to cyclic dependency - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.MUL_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_C, "> 0", IRNode.MUL_VS, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIfAnd = {"AlignVector", "false", "MaxVectorSize", ">= 4", "MaxVectorSize", "<= 14"}, applyIfCPUFeature = {"avx512bw", "true"}) // CPU: asimd -> vector_width: 32 -> elements in vector: 16 // positive byte_offset 14 can lead to cyclic dependency - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.MUL_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_C, "> 0", IRNode.MUL_VS, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIfAnd = {"AlignVector", "false", "MaxVectorSize", ">= 4", "MaxVectorSize", "<= 14"}, applyIfCPUFeature = {"asimd", "true"}) public static void testCharP7(char[] data) { @@ -6039,19 +6039,19 @@ public static void runCharP7() { @Test // CPU: sse4.1 to avx -> vector_width: 16 -> elements in vector: 8 - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.MUL_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_C, "> 0", IRNode.MUL_VS, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIfAnd = {"AlignVector", "false", "MaxVectorSize", ">= 4"}, applyIfCPUFeatureAnd = {"sse4.1", "true", "avx2", "false"}) // CPU: avx2 to avx512 without avx512bw -> vector_width: 32 -> elements in vector: 16 - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.MUL_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_C, "> 0", IRNode.MUL_VS, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIfAnd = {"AlignVector", "false", "MaxVectorSize", ">= 4"}, applyIfCPUFeatureAnd = {"avx2", "true", "avx512bw", "false"}) // CPU: avx512bw -> vector_width: 64 -> elements in vector: 32 - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.MUL_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_C, "> 0", IRNode.MUL_VS, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIfAnd = {"AlignVector", "false", "MaxVectorSize", ">= 4"}, applyIfCPUFeature = {"avx512bw", "true"}) // CPU: asimd -> vector_width: 32 -> elements in vector: 16 - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.MUL_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_C, "> 0", IRNode.MUL_VS, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIfAnd = {"AlignVector", "false", "MaxVectorSize", ">= 4"}, applyIfCPUFeature = {"asimd", "true"}) public static void testCharM8(char[] data) { @@ -6071,26 +6071,26 @@ public static void runCharM8() { @Test // CPU: sse4.1 to avx -> vector_width: 16 -> elements in vector: 8 - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.MUL_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_C, "> 0", IRNode.MUL_VS, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIfAnd = {"AlignVector", "false", "MaxVectorSize", ">= 4"}, applyIfCPUFeatureAnd = {"sse4.1", "true", "avx2", "false"}) // Vectorize when strict alignment guaranteed. - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.MUL_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_C, "> 0", IRNode.MUL_VS, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIfAnd = {"AlignVector", "true", "MaxVectorSize", ">= 4"}, applyIfCPUFeatureAnd = {"sse4.1", "true", "avx2", "false"}) // CPU: avx2 to avx512 without avx512bw -> vector_width: 32 -> elements in vector: 16 // positive byte_offset 16 can lead to cyclic dependency - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.MUL_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_C, "> 0", IRNode.MUL_VS, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIfAnd = {"AlignVector", "false", "MaxVectorSize", ">= 4", "MaxVectorSize", "<= 16"}, applyIfCPUFeatureAnd = {"avx2", "true", "avx512bw", "false"}) // CPU: avx512bw -> vector_width: 64 -> elements in vector: 32 // positive byte_offset 16 can lead to cyclic dependency - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.MUL_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_C, "> 0", IRNode.MUL_VS, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIfAnd = {"AlignVector", "false", "MaxVectorSize", ">= 4", "MaxVectorSize", "<= 16"}, applyIfCPUFeature = {"avx512bw", "true"}) // CPU: asimd -> vector_width: 32 -> elements in vector: 16 // positive byte_offset 16 can lead to cyclic dependency - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.MUL_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_C, "> 0", IRNode.MUL_VS, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIfAnd = {"AlignVector", "false", "MaxVectorSize", ">= 4", "MaxVectorSize", "<= 16"}, applyIfCPUFeature = {"asimd", "true"}) public static void testCharP8(char[] data) { @@ -6110,19 +6110,19 @@ public static void runCharP8() { @Test // CPU: sse4.1 to avx -> vector_width: 16 -> elements in vector: 8 - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.MUL_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_C, "> 0", IRNode.MUL_VS, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIfAnd = {"AlignVector", "false", "MaxVectorSize", ">= 4"}, applyIfCPUFeatureAnd = {"sse4.1", "true", "avx2", "false"}) // CPU: avx2 to avx512 without avx512bw -> vector_width: 32 -> elements in vector: 16 - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.MUL_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_C, "> 0", IRNode.MUL_VS, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIfAnd = {"AlignVector", "false", "MaxVectorSize", ">= 4"}, applyIfCPUFeatureAnd = {"avx2", "true", "avx512bw", "false"}) // CPU: avx512bw -> vector_width: 64 -> elements in vector: 32 - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.MUL_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_C, "> 0", IRNode.MUL_VS, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIfAnd = {"AlignVector", "false", "MaxVectorSize", ">= 4"}, applyIfCPUFeature = {"avx512bw", "true"}) // CPU: asimd -> vector_width: 32 -> elements in vector: 16 - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.MUL_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_C, "> 0", IRNode.MUL_VS, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIfAnd = {"AlignVector", "false", "MaxVectorSize", ">= 4"}, applyIfCPUFeature = {"asimd", "true"}) public static void testCharM14(char[] data) { @@ -6142,22 +6142,22 @@ public static void runCharM14() { @Test // CPU: sse4.1 to avx -> vector_width: 16 -> elements in vector: 8 - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.MUL_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_C, "> 0", IRNode.MUL_VS, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIfAnd = {"AlignVector", "false", "MaxVectorSize", ">= 4"}, applyIfCPUFeatureAnd = {"sse4.1", "true", "avx2", "false"}) // CPU: avx2 to avx512 without avx512bw -> vector_width: 32 -> elements in vector: 16 // positive byte_offset 28 can lead to cyclic dependency - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.MUL_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_C, "> 0", IRNode.MUL_VS, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIfAnd = {"AlignVector", "false", "MaxVectorSize", ">= 4", "MaxVectorSize", "<= 28"}, applyIfCPUFeatureAnd = {"avx2", "true", "avx512bw", "false"}) // CPU: avx512bw -> vector_width: 64 -> elements in vector: 32 // positive byte_offset 28 can lead to cyclic dependency - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.MUL_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_C, "> 0", IRNode.MUL_VS, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIfAnd = {"AlignVector", "false", "MaxVectorSize", ">= 4", "MaxVectorSize", "<= 28"}, applyIfCPUFeature = {"avx512bw", "true"}) // CPU: asimd -> vector_width: 32 -> elements in vector: 16 // positive byte_offset 28 can lead to cyclic dependency - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.MUL_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_C, "> 0", IRNode.MUL_VS, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIfAnd = {"AlignVector", "false", "MaxVectorSize", ">= 4", "MaxVectorSize", "<= 28"}, applyIfCPUFeature = {"asimd", "true"}) public static void testCharP14(char[] data) { @@ -6177,19 +6177,19 @@ public static void runCharP14() { @Test // CPU: sse4.1 to avx -> vector_width: 16 -> elements in vector: 8 - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.MUL_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_C, "> 0", IRNode.MUL_VS, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIfAnd = {"AlignVector", "false", "MaxVectorSize", ">= 4"}, applyIfCPUFeatureAnd = {"sse4.1", "true", "avx2", "false"}) // CPU: avx2 to avx512 without avx512bw -> vector_width: 32 -> elements in vector: 16 - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.MUL_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_C, "> 0", IRNode.MUL_VS, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIfAnd = {"AlignVector", "false", "MaxVectorSize", ">= 4"}, applyIfCPUFeatureAnd = {"avx2", "true", "avx512bw", "false"}) // CPU: avx512bw -> vector_width: 64 -> elements in vector: 32 - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.MUL_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_C, "> 0", IRNode.MUL_VS, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIfAnd = {"AlignVector", "false", "MaxVectorSize", ">= 4"}, applyIfCPUFeature = {"avx512bw", "true"}) // CPU: asimd -> vector_width: 32 -> elements in vector: 16 - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.MUL_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_C, "> 0", IRNode.MUL_VS, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIfAnd = {"AlignVector", "false", "MaxVectorSize", ">= 4"}, applyIfCPUFeature = {"asimd", "true"}) public static void testCharM16(char[] data) { @@ -6209,32 +6209,32 @@ public static void runCharM16() { @Test // CPU: sse4.1 to avx -> vector_width: 16 -> elements in vector: 8 - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.MUL_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_C, "> 0", IRNode.MUL_VS, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIfAnd = {"AlignVector", "false", "MaxVectorSize", ">= 4"}, applyIfCPUFeatureAnd = {"sse4.1", "true", "avx2", "false"}) // Vectorize when strict alignment guaranteed. - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.MUL_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_C, "> 0", IRNode.MUL_VS, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIfAnd = {"AlignVector", "true", "MaxVectorSize", ">= 4"}, applyIfCPUFeatureAnd = {"sse4.1", "true", "avx2", "false"}) // CPU: avx2 to avx512 without avx512bw -> vector_width: 32 -> elements in vector: 16 - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.MUL_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_C, "> 0", IRNode.MUL_VS, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIfAnd = {"AlignVector", "false", "MaxVectorSize", ">= 4"}, applyIfCPUFeatureAnd = {"avx2", "true", "avx512bw", "false"}) // Vectorize when strict alignment guaranteed. - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.MUL_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_C, "> 0", IRNode.MUL_VS, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIfAnd = {"AlignVector", "true", "MaxVectorSize", ">= 4"}, applyIfCPUFeatureAnd = {"avx2", "true", "avx512bw", "false"}) // CPU: avx512bw -> vector_width: 64 -> elements in vector: 32 // positive byte_offset 32 can lead to cyclic dependency - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.MUL_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_C, "> 0", IRNode.MUL_VS, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIfAnd = {"AlignVector", "false", "MaxVectorSize", ">= 4", "MaxVectorSize", "<= 32"}, applyIfCPUFeature = {"avx512bw", "true"}) // CPU: asimd -> vector_width: 32 -> elements in vector: 16 - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.MUL_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_C, "> 0", IRNode.MUL_VS, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIfAnd = {"AlignVector", "false", "MaxVectorSize", ">= 4"}, applyIfCPUFeature = {"asimd", "true"}) // Vectorize when strict alignment guaranteed. - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.MUL_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_C, "> 0", IRNode.MUL_VS, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIfAnd = {"AlignVector", "true", "MaxVectorSize", ">= 4"}, applyIfCPUFeature = {"asimd", "true"}) public static void testCharP16(char[] data) { @@ -6254,19 +6254,19 @@ public static void runCharP16() { @Test // CPU: sse4.1 to avx -> vector_width: 16 -> elements in vector: 8 - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.MUL_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_C, "> 0", IRNode.MUL_VS, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIfAnd = {"AlignVector", "false", "MaxVectorSize", ">= 4"}, applyIfCPUFeatureAnd = {"sse4.1", "true", "avx2", "false"}) // CPU: avx2 to avx512 without avx512bw -> vector_width: 32 -> elements in vector: 16 - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.MUL_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_C, "> 0", IRNode.MUL_VS, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIfAnd = {"AlignVector", "false", "MaxVectorSize", ">= 4"}, applyIfCPUFeatureAnd = {"avx2", "true", "avx512bw", "false"}) // CPU: avx512bw -> vector_width: 64 -> elements in vector: 32 - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.MUL_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_C, "> 0", IRNode.MUL_VS, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIfAnd = {"AlignVector", "false", "MaxVectorSize", ">= 4"}, applyIfCPUFeature = {"avx512bw", "true"}) // CPU: asimd -> vector_width: 32 -> elements in vector: 16 - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.MUL_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_C, "> 0", IRNode.MUL_VS, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIfAnd = {"AlignVector", "false", "MaxVectorSize", ">= 4"}, applyIfCPUFeature = {"asimd", "true"}) public static void testCharM18(char[] data) { @@ -6286,20 +6286,20 @@ public static void runCharM18() { @Test // CPU: sse4.1 to avx -> vector_width: 16 -> elements in vector: 8 - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.MUL_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_C, "> 0", IRNode.MUL_VS, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIfAnd = {"AlignVector", "false", "MaxVectorSize", ">= 4"}, applyIfCPUFeatureAnd = {"sse4.1", "true", "avx2", "false"}) // CPU: avx2 to avx512 without avx512bw -> vector_width: 32 -> elements in vector: 16 - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.MUL_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_C, "> 0", IRNode.MUL_VS, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIfAnd = {"AlignVector", "false", "MaxVectorSize", ">= 4"}, applyIfCPUFeatureAnd = {"avx2", "true", "avx512bw", "false"}) // CPU: avx512bw -> vector_width: 64 -> elements in vector: 32 // positive byte_offset 36 can lead to cyclic dependency - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.MUL_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_C, "> 0", IRNode.MUL_VS, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIfAnd = {"AlignVector", "false", "MaxVectorSize", ">= 4", "MaxVectorSize", "<= 36"}, applyIfCPUFeature = {"avx512bw", "true"}) // CPU: asimd -> vector_width: 32 -> elements in vector: 16 - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.MUL_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_C, "> 0", IRNode.MUL_VS, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIfAnd = {"AlignVector", "false", "MaxVectorSize", ">= 4"}, applyIfCPUFeature = {"asimd", "true"}) public static void testCharP18(char[] data) { @@ -6319,19 +6319,19 @@ public static void runCharP18() { @Test // CPU: sse4.1 to avx -> vector_width: 16 -> elements in vector: 8 - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.MUL_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_C, "> 0", IRNode.MUL_VS, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIfAnd = {"AlignVector", "false", "MaxVectorSize", ">= 4"}, applyIfCPUFeatureAnd = {"sse4.1", "true", "avx2", "false"}) // CPU: avx2 to avx512 without avx512bw -> vector_width: 32 -> elements in vector: 16 - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.MUL_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_C, "> 0", IRNode.MUL_VS, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIfAnd = {"AlignVector", "false", "MaxVectorSize", ">= 4"}, applyIfCPUFeatureAnd = {"avx2", "true", "avx512bw", "false"}) // CPU: avx512bw -> vector_width: 64 -> elements in vector: 32 - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.MUL_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_C, "> 0", IRNode.MUL_VS, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIfAnd = {"AlignVector", "false", "MaxVectorSize", ">= 4"}, applyIfCPUFeature = {"avx512bw", "true"}) // CPU: asimd -> vector_width: 32 -> elements in vector: 16 - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.MUL_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_C, "> 0", IRNode.MUL_VS, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIfAnd = {"AlignVector", "false", "MaxVectorSize", ">= 4"}, applyIfCPUFeature = {"asimd", "true"}) public static void testCharM20(char[] data) { @@ -6351,20 +6351,20 @@ public static void runCharM20() { @Test // CPU: sse4.1 to avx -> vector_width: 16 -> elements in vector: 8 - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.MUL_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_C, "> 0", IRNode.MUL_VS, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIfAnd = {"AlignVector", "false", "MaxVectorSize", ">= 4"}, applyIfCPUFeatureAnd = {"sse4.1", "true", "avx2", "false"}) // CPU: avx2 to avx512 without avx512bw -> vector_width: 32 -> elements in vector: 16 - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.MUL_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_C, "> 0", IRNode.MUL_VS, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIfAnd = {"AlignVector", "false", "MaxVectorSize", ">= 4"}, applyIfCPUFeatureAnd = {"avx2", "true", "avx512bw", "false"}) // CPU: avx512bw -> vector_width: 64 -> elements in vector: 32 // positive byte_offset 40 can lead to cyclic dependency - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.MUL_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_C, "> 0", IRNode.MUL_VS, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIfAnd = {"AlignVector", "false", "MaxVectorSize", ">= 4", "MaxVectorSize", "<= 40"}, applyIfCPUFeature = {"avx512bw", "true"}) // CPU: asimd -> vector_width: 32 -> elements in vector: 16 - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.MUL_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_C, "> 0", IRNode.MUL_VS, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIfAnd = {"AlignVector", "false", "MaxVectorSize", ">= 4"}, applyIfCPUFeature = {"asimd", "true"}) public static void testCharP20(char[] data) { @@ -6384,35 +6384,35 @@ public static void runCharP20() { @Test // CPU: sse4.1 to avx -> vector_width: 16 -> elements in vector: 8 - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.MUL_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_C, "> 0", IRNode.MUL_VS, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIfAnd = {"AlignVector", "false", "MaxVectorSize", ">= 4"}, applyIfCPUFeatureAnd = {"sse4.1", "true", "avx2", "false"}) // Strict alignment not possible. - @IR(failOn = {IRNode.LOAD_VECTOR, IRNode.MUL_V, IRNode.STORE_VECTOR}, + @IR(failOn = {IRNode.LOAD_VECTOR_C, IRNode.MUL_VS, IRNode.STORE_VECTOR}, applyIf = {"AlignVector", "true"}, applyIfCPUFeatureAnd = {"sse4.1", "true", "avx2", "false"}) // CPU: avx2 to avx512 without avx512bw -> vector_width: 32 -> elements in vector: 16 - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.MUL_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_C, "> 0", IRNode.MUL_VS, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIfAnd = {"AlignVector", "false", "MaxVectorSize", ">= 4"}, applyIfCPUFeatureAnd = {"avx2", "true", "avx512bw", "false"}) // Strict alignment not possible. - @IR(failOn = {IRNode.LOAD_VECTOR, IRNode.MUL_V, IRNode.STORE_VECTOR}, + @IR(failOn = {IRNode.LOAD_VECTOR_C, IRNode.MUL_VS, IRNode.STORE_VECTOR}, applyIf = {"AlignVector", "true"}, applyIfCPUFeatureAnd = {"avx2", "true", "avx512bw", "false"}) // CPU: avx512bw -> vector_width: 64 -> elements in vector: 32 - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.MUL_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_C, "> 0", IRNode.MUL_VS, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIfAnd = {"AlignVector", "false", "MaxVectorSize", ">= 4"}, applyIfCPUFeature = {"avx512bw", "true"}) // Strict alignment not possible. - @IR(failOn = {IRNode.LOAD_VECTOR, IRNode.MUL_V, IRNode.STORE_VECTOR}, + @IR(failOn = {IRNode.LOAD_VECTOR_C, IRNode.MUL_VS, IRNode.STORE_VECTOR}, applyIf = {"AlignVector", "true"}, applyIfCPUFeature = {"avx512bw", "true"}) // CPU: asimd -> vector_width: 32 -> elements in vector: 16 - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.MUL_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_C, "> 0", IRNode.MUL_VS, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIfAnd = {"AlignVector", "false", "MaxVectorSize", ">= 4"}, applyIfCPUFeature = {"asimd", "true"}) // Strict alignment not possible. - @IR(failOn = {IRNode.LOAD_VECTOR, IRNode.MUL_V, IRNode.STORE_VECTOR}, + @IR(failOn = {IRNode.LOAD_VECTOR_C, IRNode.MUL_VS, IRNode.STORE_VECTOR}, applyIf = {"AlignVector", "true"}, applyIfCPUFeature = {"asimd", "true"}) public static void testCharM31(char[] data) { @@ -6432,20 +6432,20 @@ public static void runCharM31() { @Test // CPU: sse4.1 to avx -> vector_width: 16 -> elements in vector: 8 - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.MUL_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_C, "> 0", IRNode.MUL_VS, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIfAnd = {"AlignVector", "false", "MaxVectorSize", ">= 4"}, applyIfCPUFeatureAnd = {"sse4.1", "true", "avx2", "false"}) // CPU: avx2 to avx512 without avx512bw -> vector_width: 32 -> elements in vector: 16 - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.MUL_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_C, "> 0", IRNode.MUL_VS, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIfAnd = {"AlignVector", "false", "MaxVectorSize", ">= 4"}, applyIfCPUFeatureAnd = {"avx2", "true", "avx512bw", "false"}) // CPU: avx512bw -> vector_width: 64 -> elements in vector: 32 // positive byte_offset 62 can lead to cyclic dependency - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.MUL_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_C, "> 0", IRNode.MUL_VS, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIfAnd = {"AlignVector", "false", "MaxVectorSize", ">= 4", "MaxVectorSize", "<= 62"}, applyIfCPUFeature = {"avx512bw", "true"}) // CPU: asimd -> vector_width: 32 -> elements in vector: 16 - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.MUL_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_C, "> 0", IRNode.MUL_VS, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIfAnd = {"AlignVector", "false", "MaxVectorSize", ">= 4"}, applyIfCPUFeature = {"asimd", "true"}) public static void testCharP31(char[] data) { @@ -6465,19 +6465,19 @@ public static void runCharP31() { @Test // CPU: sse4.1 to avx -> vector_width: 16 -> elements in vector: 8 - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.MUL_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_C, "> 0", IRNode.MUL_VS, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIfAnd = {"AlignVector", "false", "MaxVectorSize", ">= 4"}, applyIfCPUFeatureAnd = {"sse4.1", "true", "avx2", "false"}) // CPU: avx2 to avx512 without avx512bw -> vector_width: 32 -> elements in vector: 16 - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.MUL_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_C, "> 0", IRNode.MUL_VS, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIfAnd = {"AlignVector", "false", "MaxVectorSize", ">= 4"}, applyIfCPUFeatureAnd = {"avx2", "true", "avx512bw", "false"}) // CPU: avx512bw -> vector_width: 64 -> elements in vector: 32 - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.MUL_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_C, "> 0", IRNode.MUL_VS, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIfAnd = {"AlignVector", "false", "MaxVectorSize", ">= 4"}, applyIfCPUFeature = {"avx512bw", "true"}) // CPU: asimd -> vector_width: 32 -> elements in vector: 16 - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.MUL_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_C, "> 0", IRNode.MUL_VS, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIfAnd = {"AlignVector", "false", "MaxVectorSize", ">= 4"}, applyIfCPUFeature = {"asimd", "true"}) public static void testCharM32(char[] data) { @@ -6497,35 +6497,35 @@ public static void runCharM32() { @Test // CPU: sse4.1 to avx -> vector_width: 16 -> elements in vector: 8 - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.MUL_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_C, "> 0", IRNode.MUL_VS, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIfAnd = {"AlignVector", "false", "MaxVectorSize", ">= 4"}, applyIfCPUFeatureAnd = {"sse4.1", "true", "avx2", "false"}) // Vectorize when strict alignment guaranteed. - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.MUL_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_C, "> 0", IRNode.MUL_VS, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIfAnd = {"AlignVector", "true", "MaxVectorSize", ">= 4"}, applyIfCPUFeatureAnd = {"sse4.1", "true", "avx2", "false"}) // CPU: avx2 to avx512 without avx512bw -> vector_width: 32 -> elements in vector: 16 - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.MUL_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_C, "> 0", IRNode.MUL_VS, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIfAnd = {"AlignVector", "false", "MaxVectorSize", ">= 4"}, applyIfCPUFeatureAnd = {"avx2", "true", "avx512bw", "false"}) // Vectorize when strict alignment guaranteed. - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.MUL_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_C, "> 0", IRNode.MUL_VS, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIfAnd = {"AlignVector", "true", "MaxVectorSize", ">= 4"}, applyIfCPUFeatureAnd = {"avx2", "true", "avx512bw", "false"}) // CPU: avx512bw -> vector_width: 64 -> elements in vector: 32 - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.MUL_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_C, "> 0", IRNode.MUL_VS, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIfAnd = {"AlignVector", "false", "MaxVectorSize", ">= 4"}, applyIfCPUFeature = {"avx512bw", "true"}) // Vectorize when strict alignment guaranteed. - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.MUL_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_C, "> 0", IRNode.MUL_VS, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIfAnd = {"AlignVector", "true", "MaxVectorSize", ">= 4"}, applyIfCPUFeature = {"avx512bw", "true"}) // CPU: asimd -> vector_width: 32 -> elements in vector: 16 - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.MUL_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_C, "> 0", IRNode.MUL_VS, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIfAnd = {"AlignVector", "false", "MaxVectorSize", ">= 4"}, applyIfCPUFeature = {"asimd", "true"}) // Vectorize when strict alignment guaranteed. - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.MUL_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_C, "> 0", IRNode.MUL_VS, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIfAnd = {"AlignVector", "true", "MaxVectorSize", ">= 4"}, applyIfCPUFeature = {"asimd", "true"}) public static void testCharP32(char[] data) { @@ -6545,35 +6545,35 @@ public static void runCharP32() { @Test // CPU: sse4.1 to avx -> vector_width: 16 -> elements in vector: 8 - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.MUL_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_C, "> 0", IRNode.MUL_VS, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIfAnd = {"AlignVector", "false", "MaxVectorSize", ">= 4"}, applyIfCPUFeatureAnd = {"sse4.1", "true", "avx2", "false"}) // Strict alignment not possible. - @IR(failOn = {IRNode.LOAD_VECTOR, IRNode.MUL_V, IRNode.STORE_VECTOR}, + @IR(failOn = {IRNode.LOAD_VECTOR_C, IRNode.MUL_VS, IRNode.STORE_VECTOR}, applyIf = {"AlignVector", "true"}, applyIfCPUFeatureAnd = {"sse4.1", "true", "avx2", "false"}) // CPU: avx2 to avx512 without avx512bw -> vector_width: 32 -> elements in vector: 16 - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.MUL_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_C, "> 0", IRNode.MUL_VS, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIfAnd = {"AlignVector", "false", "MaxVectorSize", ">= 4"}, applyIfCPUFeatureAnd = {"avx2", "true", "avx512bw", "false"}) // Strict alignment not possible. - @IR(failOn = {IRNode.LOAD_VECTOR, IRNode.MUL_V, IRNode.STORE_VECTOR}, + @IR(failOn = {IRNode.LOAD_VECTOR_C, IRNode.MUL_VS, IRNode.STORE_VECTOR}, applyIf = {"AlignVector", "true"}, applyIfCPUFeatureAnd = {"avx2", "true", "avx512bw", "false"}) // CPU: avx512bw -> vector_width: 64 -> elements in vector: 32 - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.MUL_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_C, "> 0", IRNode.MUL_VS, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIfAnd = {"AlignVector", "false", "MaxVectorSize", ">= 4"}, applyIfCPUFeature = {"avx512bw", "true"}) // Strict alignment not possible. - @IR(failOn = {IRNode.LOAD_VECTOR, IRNode.MUL_V, IRNode.STORE_VECTOR}, + @IR(failOn = {IRNode.LOAD_VECTOR_C, IRNode.MUL_VS, IRNode.STORE_VECTOR}, applyIf = {"AlignVector", "true"}, applyIfCPUFeature = {"avx512bw", "true"}) // CPU: asimd -> vector_width: 32 -> elements in vector: 16 - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.MUL_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_C, "> 0", IRNode.MUL_VS, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIfAnd = {"AlignVector", "false", "MaxVectorSize", ">= 4"}, applyIfCPUFeature = {"asimd", "true"}) // Strict alignment not possible. - @IR(failOn = {IRNode.LOAD_VECTOR, IRNode.MUL_V, IRNode.STORE_VECTOR}, + @IR(failOn = {IRNode.LOAD_VECTOR_C, IRNode.MUL_VS, IRNode.STORE_VECTOR}, applyIf = {"AlignVector", "true"}, applyIfCPUFeature = {"asimd", "true"}) public static void testCharM63(char[] data) { @@ -6593,19 +6593,19 @@ public static void runCharM63() { @Test // CPU: sse4.1 to avx -> vector_width: 16 -> elements in vector: 8 - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.MUL_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_C, "> 0", IRNode.MUL_VS, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIfAnd = {"AlignVector", "false", "MaxVectorSize", ">= 4"}, applyIfCPUFeatureAnd = {"sse4.1", "true", "avx2", "false"}) // CPU: avx2 to avx512 without avx512bw -> vector_width: 32 -> elements in vector: 16 - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.MUL_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_C, "> 0", IRNode.MUL_VS, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIfAnd = {"AlignVector", "false", "MaxVectorSize", ">= 4"}, applyIfCPUFeatureAnd = {"avx2", "true", "avx512bw", "false"}) // CPU: avx512bw -> vector_width: 64 -> elements in vector: 32 - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.MUL_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_C, "> 0", IRNode.MUL_VS, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIfAnd = {"AlignVector", "false", "MaxVectorSize", ">= 4"}, applyIfCPUFeature = {"avx512bw", "true"}) // CPU: asimd -> vector_width: 32 -> elements in vector: 16 - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.MUL_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_C, "> 0", IRNode.MUL_VS, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIfAnd = {"AlignVector", "false", "MaxVectorSize", ">= 4"}, applyIfCPUFeature = {"asimd", "true"}) public static void testCharP63(char[] data) { @@ -6625,19 +6625,19 @@ public static void runCharP63() { @Test // CPU: sse4.1 to avx -> vector_width: 16 -> elements in vector: 8 - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.MUL_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_C, "> 0", IRNode.MUL_VS, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIfAnd = {"AlignVector", "false", "MaxVectorSize", ">= 4"}, applyIfCPUFeatureAnd = {"sse4.1", "true", "avx2", "false"}) // CPU: avx2 to avx512 without avx512bw -> vector_width: 32 -> elements in vector: 16 - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.MUL_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_C, "> 0", IRNode.MUL_VS, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIfAnd = {"AlignVector", "false", "MaxVectorSize", ">= 4"}, applyIfCPUFeatureAnd = {"avx2", "true", "avx512bw", "false"}) // CPU: avx512bw -> vector_width: 64 -> elements in vector: 32 - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.MUL_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_C, "> 0", IRNode.MUL_VS, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIfAnd = {"AlignVector", "false", "MaxVectorSize", ">= 4"}, applyIfCPUFeature = {"avx512bw", "true"}) // CPU: asimd -> vector_width: 32 -> elements in vector: 16 - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.MUL_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_C, "> 0", IRNode.MUL_VS, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIfAnd = {"AlignVector", "false", "MaxVectorSize", ">= 4"}, applyIfCPUFeature = {"asimd", "true"}) public static void testCharM64(char[] data) { @@ -6657,35 +6657,35 @@ public static void runCharM64() { @Test // CPU: sse4.1 to avx -> vector_width: 16 -> elements in vector: 8 - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.MUL_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_C, "> 0", IRNode.MUL_VS, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIfAnd = {"AlignVector", "false", "MaxVectorSize", ">= 4"}, applyIfCPUFeatureAnd = {"sse4.1", "true", "avx2", "false"}) // Vectorize when strict alignment guaranteed. - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.MUL_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_C, "> 0", IRNode.MUL_VS, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIfAnd = {"AlignVector", "true", "MaxVectorSize", ">= 4"}, applyIfCPUFeatureAnd = {"sse4.1", "true", "avx2", "false"}) // CPU: avx2 to avx512 without avx512bw -> vector_width: 32 -> elements in vector: 16 - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.MUL_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_C, "> 0", IRNode.MUL_VS, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIfAnd = {"AlignVector", "false", "MaxVectorSize", ">= 4"}, applyIfCPUFeatureAnd = {"avx2", "true", "avx512bw", "false"}) // Vectorize when strict alignment guaranteed. - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.MUL_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_C, "> 0", IRNode.MUL_VS, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIfAnd = {"AlignVector", "true", "MaxVectorSize", ">= 4"}, applyIfCPUFeatureAnd = {"avx2", "true", "avx512bw", "false"}) // CPU: avx512bw -> vector_width: 64 -> elements in vector: 32 - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.MUL_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_C, "> 0", IRNode.MUL_VS, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIfAnd = {"AlignVector", "false", "MaxVectorSize", ">= 4"}, applyIfCPUFeature = {"avx512bw", "true"}) // Vectorize when strict alignment guaranteed. - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.MUL_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_C, "> 0", IRNode.MUL_VS, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIfAnd = {"AlignVector", "true", "MaxVectorSize", ">= 4"}, applyIfCPUFeature = {"avx512bw", "true"}) // CPU: asimd -> vector_width: 32 -> elements in vector: 16 - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.MUL_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_C, "> 0", IRNode.MUL_VS, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIfAnd = {"AlignVector", "false", "MaxVectorSize", ">= 4"}, applyIfCPUFeature = {"asimd", "true"}) // Vectorize when strict alignment guaranteed. - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.MUL_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_C, "> 0", IRNode.MUL_VS, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIfAnd = {"AlignVector", "true", "MaxVectorSize", ">= 4"}, applyIfCPUFeature = {"asimd", "true"}) public static void testCharP64(char[] data) { @@ -6705,35 +6705,35 @@ public static void runCharP64() { @Test // CPU: sse4.1 to avx -> vector_width: 16 -> elements in vector: 8 - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.MUL_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_C, "> 0", IRNode.MUL_VS, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIfAnd = {"AlignVector", "false", "MaxVectorSize", ">= 4"}, applyIfCPUFeatureAnd = {"sse4.1", "true", "avx2", "false"}) // Strict alignment not possible. - @IR(failOn = {IRNode.LOAD_VECTOR, IRNode.MUL_V, IRNode.STORE_VECTOR}, + @IR(failOn = {IRNode.LOAD_VECTOR_C, IRNode.MUL_VS, IRNode.STORE_VECTOR}, applyIf = {"AlignVector", "true"}, applyIfCPUFeatureAnd = {"sse4.1", "true", "avx2", "false"}) // CPU: avx2 to avx512 without avx512bw -> vector_width: 32 -> elements in vector: 16 - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.MUL_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_C, "> 0", IRNode.MUL_VS, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIfAnd = {"AlignVector", "false", "MaxVectorSize", ">= 4"}, applyIfCPUFeatureAnd = {"avx2", "true", "avx512bw", "false"}) // Strict alignment not possible. - @IR(failOn = {IRNode.LOAD_VECTOR, IRNode.MUL_V, IRNode.STORE_VECTOR}, + @IR(failOn = {IRNode.LOAD_VECTOR_C, IRNode.MUL_VS, IRNode.STORE_VECTOR}, applyIf = {"AlignVector", "true"}, applyIfCPUFeatureAnd = {"avx2", "true", "avx512bw", "false"}) // CPU: avx512bw -> vector_width: 64 -> elements in vector: 32 - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.MUL_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_C, "> 0", IRNode.MUL_VS, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIfAnd = {"AlignVector", "false", "MaxVectorSize", ">= 4"}, applyIfCPUFeature = {"avx512bw", "true"}) // Strict alignment not possible. - @IR(failOn = {IRNode.LOAD_VECTOR, IRNode.MUL_V, IRNode.STORE_VECTOR}, + @IR(failOn = {IRNode.LOAD_VECTOR_C, IRNode.MUL_VS, IRNode.STORE_VECTOR}, applyIf = {"AlignVector", "true"}, applyIfCPUFeature = {"avx512bw", "true"}) // CPU: asimd -> vector_width: 32 -> elements in vector: 16 - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.MUL_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_C, "> 0", IRNode.MUL_VS, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIfAnd = {"AlignVector", "false", "MaxVectorSize", ">= 4"}, applyIfCPUFeature = {"asimd", "true"}) // Strict alignment not possible. - @IR(failOn = {IRNode.LOAD_VECTOR, IRNode.MUL_V, IRNode.STORE_VECTOR}, + @IR(failOn = {IRNode.LOAD_VECTOR_C, IRNode.MUL_VS, IRNode.STORE_VECTOR}, applyIf = {"AlignVector", "true"}, applyIfCPUFeature = {"asimd", "true"}) public static void testCharM65(char[] data) { @@ -6753,19 +6753,19 @@ public static void runCharM65() { @Test // CPU: sse4.1 to avx -> vector_width: 16 -> elements in vector: 8 - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.MUL_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_C, "> 0", IRNode.MUL_VS, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIfAnd = {"AlignVector", "false", "MaxVectorSize", ">= 4"}, applyIfCPUFeatureAnd = {"sse4.1", "true", "avx2", "false"}) // CPU: avx2 to avx512 without avx512bw -> vector_width: 32 -> elements in vector: 16 - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.MUL_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_C, "> 0", IRNode.MUL_VS, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIfAnd = {"AlignVector", "false", "MaxVectorSize", ">= 4"}, applyIfCPUFeatureAnd = {"avx2", "true", "avx512bw", "false"}) // CPU: avx512bw -> vector_width: 64 -> elements in vector: 32 - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.MUL_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_C, "> 0", IRNode.MUL_VS, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIfAnd = {"AlignVector", "false", "MaxVectorSize", ">= 4"}, applyIfCPUFeature = {"avx512bw", "true"}) // CPU: asimd -> vector_width: 32 -> elements in vector: 16 - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.MUL_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_C, "> 0", IRNode.MUL_VS, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIfAnd = {"AlignVector", "false", "MaxVectorSize", ">= 4"}, applyIfCPUFeature = {"asimd", "true"}) public static void testCharP65(char[] data) { @@ -6785,19 +6785,19 @@ public static void runCharP65() { @Test // CPU: sse4.1 to avx -> vector_width: 16 -> elements in vector: 8 - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.MUL_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_C, "> 0", IRNode.MUL_VS, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIfAnd = {"AlignVector", "false", "MaxVectorSize", ">= 4"}, applyIfCPUFeatureAnd = {"sse4.1", "true", "avx2", "false"}) // CPU: avx2 to avx512 without avx512bw -> vector_width: 32 -> elements in vector: 16 - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.MUL_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_C, "> 0", IRNode.MUL_VS, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIfAnd = {"AlignVector", "false", "MaxVectorSize", ">= 4"}, applyIfCPUFeatureAnd = {"avx2", "true", "avx512bw", "false"}) // CPU: avx512bw -> vector_width: 64 -> elements in vector: 32 - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.MUL_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_C, "> 0", IRNode.MUL_VS, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIfAnd = {"AlignVector", "false", "MaxVectorSize", ">= 4"}, applyIfCPUFeature = {"avx512bw", "true"}) // CPU: asimd -> vector_width: 32 -> elements in vector: 16 - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.MUL_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_C, "> 0", IRNode.MUL_VS, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIfAnd = {"AlignVector", "false", "MaxVectorSize", ">= 4"}, applyIfCPUFeature = {"asimd", "true"}) public static void testCharM128(char[] data) { @@ -6817,35 +6817,35 @@ public static void runCharM128() { @Test // CPU: sse4.1 to avx -> vector_width: 16 -> elements in vector: 8 - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.MUL_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_C, "> 0", IRNode.MUL_VS, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIfAnd = {"AlignVector", "false", "MaxVectorSize", ">= 4"}, applyIfCPUFeatureAnd = {"sse4.1", "true", "avx2", "false"}) // Vectorize when strict alignment guaranteed. - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.MUL_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_C, "> 0", IRNode.MUL_VS, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIfAnd = {"AlignVector", "true", "MaxVectorSize", ">= 4"}, applyIfCPUFeatureAnd = {"sse4.1", "true", "avx2", "false"}) // CPU: avx2 to avx512 without avx512bw -> vector_width: 32 -> elements in vector: 16 - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.MUL_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_C, "> 0", IRNode.MUL_VS, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIfAnd = {"AlignVector", "false", "MaxVectorSize", ">= 4"}, applyIfCPUFeatureAnd = {"avx2", "true", "avx512bw", "false"}) // Vectorize when strict alignment guaranteed. - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.MUL_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_C, "> 0", IRNode.MUL_VS, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIfAnd = {"AlignVector", "true", "MaxVectorSize", ">= 4"}, applyIfCPUFeatureAnd = {"avx2", "true", "avx512bw", "false"}) // CPU: avx512bw -> vector_width: 64 -> elements in vector: 32 - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.MUL_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_C, "> 0", IRNode.MUL_VS, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIfAnd = {"AlignVector", "false", "MaxVectorSize", ">= 4"}, applyIfCPUFeature = {"avx512bw", "true"}) // Vectorize when strict alignment guaranteed. - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.MUL_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_C, "> 0", IRNode.MUL_VS, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIfAnd = {"AlignVector", "true", "MaxVectorSize", ">= 4"}, applyIfCPUFeature = {"avx512bw", "true"}) // CPU: asimd -> vector_width: 32 -> elements in vector: 16 - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.MUL_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_C, "> 0", IRNode.MUL_VS, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIfAnd = {"AlignVector", "false", "MaxVectorSize", ">= 4"}, applyIfCPUFeature = {"asimd", "true"}) // Vectorize when strict alignment guaranteed. - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.MUL_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_C, "> 0", IRNode.MUL_VS, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIfAnd = {"AlignVector", "true", "MaxVectorSize", ">= 4"}, applyIfCPUFeature = {"asimd", "true"}) public static void testCharP128(char[] data) { @@ -6865,35 +6865,35 @@ public static void runCharP128() { @Test // CPU: sse4.1 to avx -> vector_width: 16 -> elements in vector: 8 - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.MUL_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_C, "> 0", IRNode.MUL_VS, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIfAnd = {"AlignVector", "false", "MaxVectorSize", ">= 4"}, applyIfCPUFeatureAnd = {"sse4.1", "true", "avx2", "false"}) // Strict alignment not possible. - @IR(failOn = {IRNode.LOAD_VECTOR, IRNode.MUL_V, IRNode.STORE_VECTOR}, + @IR(failOn = {IRNode.LOAD_VECTOR_C, IRNode.MUL_VS, IRNode.STORE_VECTOR}, applyIf = {"AlignVector", "true"}, applyIfCPUFeatureAnd = {"sse4.1", "true", "avx2", "false"}) // CPU: avx2 to avx512 without avx512bw -> vector_width: 32 -> elements in vector: 16 - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.MUL_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_C, "> 0", IRNode.MUL_VS, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIfAnd = {"AlignVector", "false", "MaxVectorSize", ">= 4"}, applyIfCPUFeatureAnd = {"avx2", "true", "avx512bw", "false"}) // Strict alignment not possible. - @IR(failOn = {IRNode.LOAD_VECTOR, IRNode.MUL_V, IRNode.STORE_VECTOR}, + @IR(failOn = {IRNode.LOAD_VECTOR_C, IRNode.MUL_VS, IRNode.STORE_VECTOR}, applyIf = {"AlignVector", "true"}, applyIfCPUFeatureAnd = {"avx2", "true", "avx512bw", "false"}) // CPU: avx512bw -> vector_width: 64 -> elements in vector: 32 - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.MUL_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_C, "> 0", IRNode.MUL_VS, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIfAnd = {"AlignVector", "false", "MaxVectorSize", ">= 4"}, applyIfCPUFeature = {"avx512bw", "true"}) // Strict alignment not possible. - @IR(failOn = {IRNode.LOAD_VECTOR, IRNode.MUL_V, IRNode.STORE_VECTOR}, + @IR(failOn = {IRNode.LOAD_VECTOR_C, IRNode.MUL_VS, IRNode.STORE_VECTOR}, applyIf = {"AlignVector", "true"}, applyIfCPUFeature = {"avx512bw", "true"}) // CPU: asimd -> vector_width: 32 -> elements in vector: 16 - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.MUL_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_C, "> 0", IRNode.MUL_VS, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIfAnd = {"AlignVector", "false", "MaxVectorSize", ">= 4"}, applyIfCPUFeature = {"asimd", "true"}) // Strict alignment not possible. - @IR(failOn = {IRNode.LOAD_VECTOR, IRNode.MUL_V, IRNode.STORE_VECTOR}, + @IR(failOn = {IRNode.LOAD_VECTOR_C, IRNode.MUL_VS, IRNode.STORE_VECTOR}, applyIf = {"AlignVector", "true"}, applyIfCPUFeature = {"asimd", "true"}) public static void testCharM129(char[] data) { @@ -6913,19 +6913,19 @@ public static void runCharM129() { @Test // CPU: sse4.1 to avx -> vector_width: 16 -> elements in vector: 8 - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.MUL_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_C, "> 0", IRNode.MUL_VS, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIfAnd = {"AlignVector", "false", "MaxVectorSize", ">= 4"}, applyIfCPUFeatureAnd = {"sse4.1", "true", "avx2", "false"}) // CPU: avx2 to avx512 without avx512bw -> vector_width: 32 -> elements in vector: 16 - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.MUL_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_C, "> 0", IRNode.MUL_VS, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIfAnd = {"AlignVector", "false", "MaxVectorSize", ">= 4"}, applyIfCPUFeatureAnd = {"avx2", "true", "avx512bw", "false"}) // CPU: avx512bw -> vector_width: 64 -> elements in vector: 32 - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.MUL_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_C, "> 0", IRNode.MUL_VS, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIfAnd = {"AlignVector", "false", "MaxVectorSize", ">= 4"}, applyIfCPUFeature = {"avx512bw", "true"}) // CPU: asimd -> vector_width: 32 -> elements in vector: 16 - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.MUL_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_C, "> 0", IRNode.MUL_VS, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIfAnd = {"AlignVector", "false", "MaxVectorSize", ">= 4"}, applyIfCPUFeature = {"asimd", "true"}) public static void testCharP129(char[] data) { @@ -6945,19 +6945,19 @@ public static void runCharP129() { @Test // CPU: sse4.1 to avx -> vector_width: 16 -> elements in vector: 8 - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.MUL_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_C, "> 0", IRNode.MUL_VS, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIfAnd = {"AlignVector", "false", "MaxVectorSize", ">= 4"}, applyIfCPUFeatureAnd = {"sse4.1", "true", "avx2", "false"}) // CPU: avx2 to avx512 without avx512bw -> vector_width: 32 -> elements in vector: 16 - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.MUL_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_C, "> 0", IRNode.MUL_VS, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIfAnd = {"AlignVector", "false", "MaxVectorSize", ">= 4"}, applyIfCPUFeatureAnd = {"avx2", "true", "avx512bw", "false"}) // CPU: avx512bw -> vector_width: 64 -> elements in vector: 32 - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.MUL_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_C, "> 0", IRNode.MUL_VS, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIfAnd = {"AlignVector", "false", "MaxVectorSize", ">= 4"}, applyIfCPUFeature = {"avx512bw", "true"}) // CPU: asimd -> vector_width: 32 -> elements in vector: 16 - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.MUL_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_C, "> 0", IRNode.MUL_VS, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIfAnd = {"AlignVector", "false", "MaxVectorSize", ">= 4"}, applyIfCPUFeature = {"asimd", "true"}) public static void testCharM192(char[] data) { @@ -6977,35 +6977,35 @@ public static void runCharM192() { @Test // CPU: sse4.1 to avx -> vector_width: 16 -> elements in vector: 8 - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.MUL_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_C, "> 0", IRNode.MUL_VS, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIfAnd = {"AlignVector", "false", "MaxVectorSize", ">= 4"}, applyIfCPUFeatureAnd = {"sse4.1", "true", "avx2", "false"}) // Vectorize when strict alignment guaranteed. - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.MUL_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_C, "> 0", IRNode.MUL_VS, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIfAnd = {"AlignVector", "true", "MaxVectorSize", ">= 4"}, applyIfCPUFeatureAnd = {"sse4.1", "true", "avx2", "false"}) // CPU: avx2 to avx512 without avx512bw -> vector_width: 32 -> elements in vector: 16 - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.MUL_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_C, "> 0", IRNode.MUL_VS, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIfAnd = {"AlignVector", "false", "MaxVectorSize", ">= 4"}, applyIfCPUFeatureAnd = {"avx2", "true", "avx512bw", "false"}) // Vectorize when strict alignment guaranteed. - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.MUL_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_C, "> 0", IRNode.MUL_VS, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIfAnd = {"AlignVector", "true", "MaxVectorSize", ">= 4"}, applyIfCPUFeatureAnd = {"avx2", "true", "avx512bw", "false"}) // CPU: avx512bw -> vector_width: 64 -> elements in vector: 32 - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.MUL_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_C, "> 0", IRNode.MUL_VS, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIfAnd = {"AlignVector", "false", "MaxVectorSize", ">= 4"}, applyIfCPUFeature = {"avx512bw", "true"}) // Vectorize when strict alignment guaranteed. - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.MUL_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_C, "> 0", IRNode.MUL_VS, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIfAnd = {"AlignVector", "true", "MaxVectorSize", ">= 4"}, applyIfCPUFeature = {"avx512bw", "true"}) // CPU: asimd -> vector_width: 32 -> elements in vector: 16 - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.MUL_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_C, "> 0", IRNode.MUL_VS, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIfAnd = {"AlignVector", "false", "MaxVectorSize", ">= 4"}, applyIfCPUFeature = {"asimd", "true"}) // Vectorize when strict alignment guaranteed. - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.MUL_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_C, "> 0", IRNode.MUL_VS, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIfAnd = {"AlignVector", "true", "MaxVectorSize", ">= 4"}, applyIfCPUFeature = {"asimd", "true"}) public static void testCharP192(char[] data) { @@ -7025,19 +7025,19 @@ public static void runCharP192() { @Test // CPU: sse4.1 to avx -> vector_width: 16 -> elements in vector: 16 - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.MUL_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_B, "> 0", IRNode.MUL_VB, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIfAnd = {"AlignVector", "false", "MaxVectorSize", ">= 4"}, applyIfCPUFeatureAnd = {"sse4.1", "true", "avx2", "false"}) // CPU: avx2 to avx512 without avx512bw -> vector_width: 32 -> elements in vector: 32 - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.MUL_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_B, "> 0", IRNode.MUL_VB, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIfAnd = {"AlignVector", "false", "MaxVectorSize", ">= 4"}, applyIfCPUFeatureAnd = {"avx2", "true", "avx512bw", "false"}) // CPU: avx512bw -> vector_width: 64 -> elements in vector: 64 - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.MUL_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_B, "> 0", IRNode.MUL_VB, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIfAnd = {"AlignVector", "false", "MaxVectorSize", ">= 4"}, applyIfCPUFeature = {"avx512bw", "true"}) // CPU: asimd -> vector_width: 32 -> elements in vector: 32 - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.MUL_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_B, "> 0", IRNode.MUL_VB, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIfAnd = {"AlignVector", "false", "MaxVectorSize", ">= 4"}, applyIfCPUFeature = {"asimd", "true"}) public static void testByteP0(byte[] data) { @@ -7057,35 +7057,35 @@ public static void runByteP0() { @Test // CPU: sse4.1 to avx -> vector_width: 16 -> elements in vector: 16 - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.MUL_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_B, "> 0", IRNode.MUL_VB, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIfAnd = {"AlignVector", "false", "MaxVectorSize", ">= 4"}, applyIfCPUFeatureAnd = {"sse4.1", "true", "avx2", "false"}) // Strict alignment not possible. - @IR(failOn = {IRNode.LOAD_VECTOR, IRNode.MUL_V, IRNode.STORE_VECTOR}, + @IR(failOn = {IRNode.LOAD_VECTOR_B, IRNode.MUL_VB, IRNode.STORE_VECTOR}, applyIf = {"AlignVector", "true"}, applyIfCPUFeatureAnd = {"sse4.1", "true", "avx2", "false"}) // CPU: avx2 to avx512 without avx512bw -> vector_width: 32 -> elements in vector: 32 - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.MUL_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_B, "> 0", IRNode.MUL_VB, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIfAnd = {"AlignVector", "false", "MaxVectorSize", ">= 4"}, applyIfCPUFeatureAnd = {"avx2", "true", "avx512bw", "false"}) // Strict alignment not possible. - @IR(failOn = {IRNode.LOAD_VECTOR, IRNode.MUL_V, IRNode.STORE_VECTOR}, + @IR(failOn = {IRNode.LOAD_VECTOR_B, IRNode.MUL_VB, IRNode.STORE_VECTOR}, applyIf = {"AlignVector", "true"}, applyIfCPUFeatureAnd = {"avx2", "true", "avx512bw", "false"}) // CPU: avx512bw -> vector_width: 64 -> elements in vector: 64 - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.MUL_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_B, "> 0", IRNode.MUL_VB, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIfAnd = {"AlignVector", "false", "MaxVectorSize", ">= 4"}, applyIfCPUFeature = {"avx512bw", "true"}) // Strict alignment not possible. - @IR(failOn = {IRNode.LOAD_VECTOR, IRNode.MUL_V, IRNode.STORE_VECTOR}, + @IR(failOn = {IRNode.LOAD_VECTOR_B, IRNode.MUL_VB, IRNode.STORE_VECTOR}, applyIf = {"AlignVector", "true"}, applyIfCPUFeature = {"avx512bw", "true"}) // CPU: asimd -> vector_width: 32 -> elements in vector: 32 - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.MUL_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_B, "> 0", IRNode.MUL_VB, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIfAnd = {"AlignVector", "false", "MaxVectorSize", ">= 4"}, applyIfCPUFeature = {"asimd", "true"}) // Strict alignment not possible. - @IR(failOn = {IRNode.LOAD_VECTOR, IRNode.MUL_V, IRNode.STORE_VECTOR}, + @IR(failOn = {IRNode.LOAD_VECTOR_B, IRNode.MUL_VB, IRNode.STORE_VECTOR}, applyIf = {"AlignVector", "true"}, applyIfCPUFeature = {"asimd", "true"}) public static void testByteM1(byte[] data) { @@ -7133,35 +7133,35 @@ public static void runByteP1() { @Test // CPU: sse4.1 to avx -> vector_width: 16 -> elements in vector: 16 - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.MUL_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_B, "> 0", IRNode.MUL_VB, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIfAnd = {"AlignVector", "false", "MaxVectorSize", ">= 4"}, applyIfCPUFeatureAnd = {"sse4.1", "true", "avx2", "false"}) // Strict alignment not possible. - @IR(failOn = {IRNode.LOAD_VECTOR, IRNode.MUL_V, IRNode.STORE_VECTOR}, + @IR(failOn = {IRNode.LOAD_VECTOR_B, IRNode.MUL_VB, IRNode.STORE_VECTOR}, applyIf = {"AlignVector", "true"}, applyIfCPUFeatureAnd = {"sse4.1", "true", "avx2", "false"}) // CPU: avx2 to avx512 without avx512bw -> vector_width: 32 -> elements in vector: 32 - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.MUL_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_B, "> 0", IRNode.MUL_VB, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIfAnd = {"AlignVector", "false", "MaxVectorSize", ">= 4"}, applyIfCPUFeatureAnd = {"avx2", "true", "avx512bw", "false"}) // Strict alignment not possible. - @IR(failOn = {IRNode.LOAD_VECTOR, IRNode.MUL_V, IRNode.STORE_VECTOR}, + @IR(failOn = {IRNode.LOAD_VECTOR_B, IRNode.MUL_VB, IRNode.STORE_VECTOR}, applyIf = {"AlignVector", "true"}, applyIfCPUFeatureAnd = {"avx2", "true", "avx512bw", "false"}) // CPU: avx512bw -> vector_width: 64 -> elements in vector: 64 - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.MUL_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_B, "> 0", IRNode.MUL_VB, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIfAnd = {"AlignVector", "false", "MaxVectorSize", ">= 4"}, applyIfCPUFeature = {"avx512bw", "true"}) // Strict alignment not possible. - @IR(failOn = {IRNode.LOAD_VECTOR, IRNode.MUL_V, IRNode.STORE_VECTOR}, + @IR(failOn = {IRNode.LOAD_VECTOR_B, IRNode.MUL_VB, IRNode.STORE_VECTOR}, applyIf = {"AlignVector", "true"}, applyIfCPUFeature = {"avx512bw", "true"}) // CPU: asimd -> vector_width: 32 -> elements in vector: 32 - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.MUL_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_B, "> 0", IRNode.MUL_VB, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIfAnd = {"AlignVector", "false", "MaxVectorSize", ">= 4"}, applyIfCPUFeature = {"asimd", "true"}) // Strict alignment not possible. - @IR(failOn = {IRNode.LOAD_VECTOR, IRNode.MUL_V, IRNode.STORE_VECTOR}, + @IR(failOn = {IRNode.LOAD_VECTOR_B, IRNode.MUL_VB, IRNode.STORE_VECTOR}, applyIf = {"AlignVector", "true"}, applyIfCPUFeature = {"asimd", "true"}) public static void testByteM2(byte[] data) { @@ -7209,35 +7209,35 @@ public static void runByteP2() { @Test // CPU: sse4.1 to avx -> vector_width: 16 -> elements in vector: 16 - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.MUL_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_B, "> 0", IRNode.MUL_VB, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIfAnd = {"AlignVector", "false", "MaxVectorSize", ">= 4"}, applyIfCPUFeatureAnd = {"sse4.1", "true", "avx2", "false"}) // Strict alignment not possible. - @IR(failOn = {IRNode.LOAD_VECTOR, IRNode.MUL_V, IRNode.STORE_VECTOR}, + @IR(failOn = {IRNode.LOAD_VECTOR_B, IRNode.MUL_VB, IRNode.STORE_VECTOR}, applyIf = {"AlignVector", "true"}, applyIfCPUFeatureAnd = {"sse4.1", "true", "avx2", "false"}) // CPU: avx2 to avx512 without avx512bw -> vector_width: 32 -> elements in vector: 32 - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.MUL_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_B, "> 0", IRNode.MUL_VB, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIfAnd = {"AlignVector", "false", "MaxVectorSize", ">= 4"}, applyIfCPUFeatureAnd = {"avx2", "true", "avx512bw", "false"}) // Strict alignment not possible. - @IR(failOn = {IRNode.LOAD_VECTOR, IRNode.MUL_V, IRNode.STORE_VECTOR}, + @IR(failOn = {IRNode.LOAD_VECTOR_B, IRNode.MUL_VB, IRNode.STORE_VECTOR}, applyIf = {"AlignVector", "true"}, applyIfCPUFeatureAnd = {"avx2", "true", "avx512bw", "false"}) // CPU: avx512bw -> vector_width: 64 -> elements in vector: 64 - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.MUL_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_B, "> 0", IRNode.MUL_VB, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIfAnd = {"AlignVector", "false", "MaxVectorSize", ">= 4"}, applyIfCPUFeature = {"avx512bw", "true"}) // Strict alignment not possible. - @IR(failOn = {IRNode.LOAD_VECTOR, IRNode.MUL_V, IRNode.STORE_VECTOR}, + @IR(failOn = {IRNode.LOAD_VECTOR_B, IRNode.MUL_VB, IRNode.STORE_VECTOR}, applyIf = {"AlignVector", "true"}, applyIfCPUFeature = {"avx512bw", "true"}) // CPU: asimd -> vector_width: 32 -> elements in vector: 32 - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.MUL_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_B, "> 0", IRNode.MUL_VB, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIfAnd = {"AlignVector", "false", "MaxVectorSize", ">= 4"}, applyIfCPUFeature = {"asimd", "true"}) // Strict alignment not possible. - @IR(failOn = {IRNode.LOAD_VECTOR, IRNode.MUL_V, IRNode.STORE_VECTOR}, + @IR(failOn = {IRNode.LOAD_VECTOR_B, IRNode.MUL_VB, IRNode.STORE_VECTOR}, applyIf = {"AlignVector", "true"}, applyIfCPUFeature = {"asimd", "true"}) public static void testByteM3(byte[] data) { @@ -7285,19 +7285,19 @@ public static void runByteP3() { @Test // CPU: sse4.1 to avx -> vector_width: 16 -> elements in vector: 16 - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.MUL_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_B, "> 0", IRNode.MUL_VB, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIfAnd = {"AlignVector", "false", "MaxVectorSize", ">= 4"}, applyIfCPUFeatureAnd = {"sse4.1", "true", "avx2", "false"}) // CPU: avx2 to avx512 without avx512bw -> vector_width: 32 -> elements in vector: 32 - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.MUL_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_B, "> 0", IRNode.MUL_VB, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIfAnd = {"AlignVector", "false", "MaxVectorSize", ">= 4"}, applyIfCPUFeatureAnd = {"avx2", "true", "avx512bw", "false"}) // CPU: avx512bw -> vector_width: 64 -> elements in vector: 64 - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.MUL_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_B, "> 0", IRNode.MUL_VB, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIfAnd = {"AlignVector", "false", "MaxVectorSize", ">= 4"}, applyIfCPUFeature = {"avx512bw", "true"}) // CPU: asimd -> vector_width: 32 -> elements in vector: 32 - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.MUL_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_B, "> 0", IRNode.MUL_VB, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIfAnd = {"AlignVector", "false", "MaxVectorSize", ">= 4"}, applyIfCPUFeature = {"asimd", "true"}) public static void testByteM4(byte[] data) { @@ -7318,22 +7318,22 @@ public static void runByteM4() { @Test // CPU: sse4.1 to avx -> vector_width: 16 -> elements in vector: 16 // positive byte_offset 4 can lead to cyclic dependency - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.MUL_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_B, "> 0", IRNode.MUL_VB, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIfAnd = {"AlignVector", "false", "MaxVectorSize", ">= 4", "MaxVectorSize", "<= 4"}, applyIfCPUFeatureAnd = {"sse4.1", "true", "avx2", "false"}) // CPU: avx2 to avx512 without avx512bw -> vector_width: 32 -> elements in vector: 32 // positive byte_offset 4 can lead to cyclic dependency - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.MUL_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_B, "> 0", IRNode.MUL_VB, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIfAnd = {"AlignVector", "false", "MaxVectorSize", ">= 4", "MaxVectorSize", "<= 4"}, applyIfCPUFeatureAnd = {"avx2", "true", "avx512bw", "false"}) // CPU: avx512bw -> vector_width: 64 -> elements in vector: 64 // positive byte_offset 4 can lead to cyclic dependency - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.MUL_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_B, "> 0", IRNode.MUL_VB, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIfAnd = {"AlignVector", "false", "MaxVectorSize", ">= 4", "MaxVectorSize", "<= 4"}, applyIfCPUFeature = {"avx512bw", "true"}) // CPU: asimd -> vector_width: 32 -> elements in vector: 32 // positive byte_offset 4 can lead to cyclic dependency - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.MUL_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_B, "> 0", IRNode.MUL_VB, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIfAnd = {"AlignVector", "false", "MaxVectorSize", ">= 4", "MaxVectorSize", "<= 4"}, applyIfCPUFeature = {"asimd", "true"}) public static void testByteP4(byte[] data) { @@ -7353,35 +7353,35 @@ public static void runByteP4() { @Test // CPU: sse4.1 to avx -> vector_width: 16 -> elements in vector: 16 - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.MUL_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_B, "> 0", IRNode.MUL_VB, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIfAnd = {"AlignVector", "false", "MaxVectorSize", ">= 4"}, applyIfCPUFeatureAnd = {"sse4.1", "true", "avx2", "false"}) // Strict alignment not possible. - @IR(failOn = {IRNode.LOAD_VECTOR, IRNode.MUL_V, IRNode.STORE_VECTOR}, + @IR(failOn = {IRNode.LOAD_VECTOR_B, IRNode.MUL_VB, IRNode.STORE_VECTOR}, applyIf = {"AlignVector", "true"}, applyIfCPUFeatureAnd = {"sse4.1", "true", "avx2", "false"}) // CPU: avx2 to avx512 without avx512bw -> vector_width: 32 -> elements in vector: 32 - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.MUL_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_B, "> 0", IRNode.MUL_VB, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIfAnd = {"AlignVector", "false", "MaxVectorSize", ">= 4"}, applyIfCPUFeatureAnd = {"avx2", "true", "avx512bw", "false"}) // Strict alignment not possible. - @IR(failOn = {IRNode.LOAD_VECTOR, IRNode.MUL_V, IRNode.STORE_VECTOR}, + @IR(failOn = {IRNode.LOAD_VECTOR_B, IRNode.MUL_VB, IRNode.STORE_VECTOR}, applyIf = {"AlignVector", "true"}, applyIfCPUFeatureAnd = {"avx2", "true", "avx512bw", "false"}) // CPU: avx512bw -> vector_width: 64 -> elements in vector: 64 - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.MUL_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_B, "> 0", IRNode.MUL_VB, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIfAnd = {"AlignVector", "false", "MaxVectorSize", ">= 4"}, applyIfCPUFeature = {"avx512bw", "true"}) // Strict alignment not possible. - @IR(failOn = {IRNode.LOAD_VECTOR, IRNode.MUL_V, IRNode.STORE_VECTOR}, + @IR(failOn = {IRNode.LOAD_VECTOR_B, IRNode.MUL_VB, IRNode.STORE_VECTOR}, applyIf = {"AlignVector", "true"}, applyIfCPUFeature = {"avx512bw", "true"}) // CPU: asimd -> vector_width: 32 -> elements in vector: 32 - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.MUL_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_B, "> 0", IRNode.MUL_VB, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIfAnd = {"AlignVector", "false", "MaxVectorSize", ">= 4"}, applyIfCPUFeature = {"asimd", "true"}) // Strict alignment not possible. - @IR(failOn = {IRNode.LOAD_VECTOR, IRNode.MUL_V, IRNode.STORE_VECTOR}, + @IR(failOn = {IRNode.LOAD_VECTOR_B, IRNode.MUL_VB, IRNode.STORE_VECTOR}, applyIf = {"AlignVector", "true"}, applyIfCPUFeature = {"asimd", "true"}) public static void testByteM7(byte[] data) { @@ -7402,22 +7402,22 @@ public static void runByteM7() { @Test // CPU: sse4.1 to avx -> vector_width: 16 -> elements in vector: 16 // positive byte_offset 7 can lead to cyclic dependency - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.MUL_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_B, "> 0", IRNode.MUL_VB, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIfAnd = {"AlignVector", "false", "MaxVectorSize", ">= 4", "MaxVectorSize", "<= 7"}, applyIfCPUFeatureAnd = {"sse4.1", "true", "avx2", "false"}) // CPU: avx2 to avx512 without avx512bw -> vector_width: 32 -> elements in vector: 32 // positive byte_offset 7 can lead to cyclic dependency - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.MUL_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_B, "> 0", IRNode.MUL_VB, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIfAnd = {"AlignVector", "false", "MaxVectorSize", ">= 4", "MaxVectorSize", "<= 7"}, applyIfCPUFeatureAnd = {"avx2", "true", "avx512bw", "false"}) // CPU: avx512bw -> vector_width: 64 -> elements in vector: 64 // positive byte_offset 7 can lead to cyclic dependency - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.MUL_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_B, "> 0", IRNode.MUL_VB, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIfAnd = {"AlignVector", "false", "MaxVectorSize", ">= 4", "MaxVectorSize", "<= 7"}, applyIfCPUFeature = {"avx512bw", "true"}) // CPU: asimd -> vector_width: 32 -> elements in vector: 32 // positive byte_offset 7 can lead to cyclic dependency - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.MUL_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_B, "> 0", IRNode.MUL_VB, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIfAnd = {"AlignVector", "false", "MaxVectorSize", ">= 4", "MaxVectorSize", "<= 7"}, applyIfCPUFeature = {"asimd", "true"}) public static void testByteP7(byte[] data) { @@ -7437,19 +7437,19 @@ public static void runByteP7() { @Test // CPU: sse4.1 to avx -> vector_width: 16 -> elements in vector: 16 - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.MUL_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_B, "> 0", IRNode.MUL_VB, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIfAnd = {"AlignVector", "false", "MaxVectorSize", ">= 4"}, applyIfCPUFeatureAnd = {"sse4.1", "true", "avx2", "false"}) // CPU: avx2 to avx512 without avx512bw -> vector_width: 32 -> elements in vector: 32 - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.MUL_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_B, "> 0", IRNode.MUL_VB, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIfAnd = {"AlignVector", "false", "MaxVectorSize", ">= 4"}, applyIfCPUFeatureAnd = {"avx2", "true", "avx512bw", "false"}) // CPU: avx512bw -> vector_width: 64 -> elements in vector: 64 - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.MUL_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_B, "> 0", IRNode.MUL_VB, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIfAnd = {"AlignVector", "false", "MaxVectorSize", ">= 4"}, applyIfCPUFeature = {"avx512bw", "true"}) // CPU: asimd -> vector_width: 32 -> elements in vector: 32 - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.MUL_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_B, "> 0", IRNode.MUL_VB, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIfAnd = {"AlignVector", "false", "MaxVectorSize", ">= 4"}, applyIfCPUFeature = {"asimd", "true"}) public static void testByteM8(byte[] data) { @@ -7470,22 +7470,22 @@ public static void runByteM8() { @Test // CPU: sse4.1 to avx -> vector_width: 16 -> elements in vector: 16 // positive byte_offset 8 can lead to cyclic dependency - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.MUL_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_B, "> 0", IRNode.MUL_VB, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIfAnd = {"AlignVector", "false", "MaxVectorSize", ">= 4", "MaxVectorSize", "<= 8"}, applyIfCPUFeatureAnd = {"sse4.1", "true", "avx2", "false"}) // CPU: avx2 to avx512 without avx512bw -> vector_width: 32 -> elements in vector: 32 // positive byte_offset 8 can lead to cyclic dependency - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.MUL_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_B, "> 0", IRNode.MUL_VB, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIfAnd = {"AlignVector", "false", "MaxVectorSize", ">= 4", "MaxVectorSize", "<= 8"}, applyIfCPUFeatureAnd = {"avx2", "true", "avx512bw", "false"}) // CPU: avx512bw -> vector_width: 64 -> elements in vector: 64 // positive byte_offset 8 can lead to cyclic dependency - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.MUL_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_B, "> 0", IRNode.MUL_VB, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIfAnd = {"AlignVector", "false", "MaxVectorSize", ">= 4", "MaxVectorSize", "<= 8"}, applyIfCPUFeature = {"avx512bw", "true"}) // CPU: asimd -> vector_width: 32 -> elements in vector: 32 // positive byte_offset 8 can lead to cyclic dependency - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.MUL_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_B, "> 0", IRNode.MUL_VB, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIfAnd = {"AlignVector", "false", "MaxVectorSize", ">= 4", "MaxVectorSize", "<= 8"}, applyIfCPUFeature = {"asimd", "true"}) public static void testByteP8(byte[] data) { @@ -7505,35 +7505,35 @@ public static void runByteP8() { @Test // CPU: sse4.1 to avx -> vector_width: 16 -> elements in vector: 16 - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.MUL_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_B, "> 0", IRNode.MUL_VB, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIfAnd = {"AlignVector", "false", "MaxVectorSize", ">= 4"}, applyIfCPUFeatureAnd = {"sse4.1", "true", "avx2", "false"}) // Strict alignment not possible. - @IR(failOn = {IRNode.LOAD_VECTOR, IRNode.MUL_V, IRNode.STORE_VECTOR}, + @IR(failOn = {IRNode.LOAD_VECTOR_B, IRNode.MUL_VB, IRNode.STORE_VECTOR}, applyIf = {"AlignVector", "true"}, applyIfCPUFeatureAnd = {"sse4.1", "true", "avx2", "false"}) // CPU: avx2 to avx512 without avx512bw -> vector_width: 32 -> elements in vector: 32 - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.MUL_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_B, "> 0", IRNode.MUL_VB, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIfAnd = {"AlignVector", "false", "MaxVectorSize", ">= 4"}, applyIfCPUFeatureAnd = {"avx2", "true", "avx512bw", "false"}) // Strict alignment not possible. - @IR(failOn = {IRNode.LOAD_VECTOR, IRNode.MUL_V, IRNode.STORE_VECTOR}, + @IR(failOn = {IRNode.LOAD_VECTOR_B, IRNode.MUL_VB, IRNode.STORE_VECTOR}, applyIf = {"AlignVector", "true"}, applyIfCPUFeatureAnd = {"avx2", "true", "avx512bw", "false"}) // CPU: avx512bw -> vector_width: 64 -> elements in vector: 64 - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.MUL_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_B, "> 0", IRNode.MUL_VB, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIfAnd = {"AlignVector", "false", "MaxVectorSize", ">= 4"}, applyIfCPUFeature = {"avx512bw", "true"}) // Strict alignment not possible. - @IR(failOn = {IRNode.LOAD_VECTOR, IRNode.MUL_V, IRNode.STORE_VECTOR}, + @IR(failOn = {IRNode.LOAD_VECTOR_B, IRNode.MUL_VB, IRNode.STORE_VECTOR}, applyIf = {"AlignVector", "true"}, applyIfCPUFeature = {"avx512bw", "true"}) // CPU: asimd -> vector_width: 32 -> elements in vector: 32 - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.MUL_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_B, "> 0", IRNode.MUL_VB, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIfAnd = {"AlignVector", "false", "MaxVectorSize", ">= 4"}, applyIfCPUFeature = {"asimd", "true"}) // Strict alignment not possible. - @IR(failOn = {IRNode.LOAD_VECTOR, IRNode.MUL_V, IRNode.STORE_VECTOR}, + @IR(failOn = {IRNode.LOAD_VECTOR_B, IRNode.MUL_VB, IRNode.STORE_VECTOR}, applyIf = {"AlignVector", "true"}, applyIfCPUFeature = {"asimd", "true"}) public static void testByteM14(byte[] data) { @@ -7554,22 +7554,22 @@ public static void runByteM14() { @Test // CPU: sse4.1 to avx -> vector_width: 16 -> elements in vector: 16 // positive byte_offset 14 can lead to cyclic dependency - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.MUL_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_B, "> 0", IRNode.MUL_VB, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIfAnd = {"AlignVector", "false", "MaxVectorSize", ">= 4", "MaxVectorSize", "<= 14"}, applyIfCPUFeatureAnd = {"sse4.1", "true", "avx2", "false"}) // CPU: avx2 to avx512 without avx512bw -> vector_width: 32 -> elements in vector: 32 // positive byte_offset 14 can lead to cyclic dependency - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.MUL_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_B, "> 0", IRNode.MUL_VB, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIfAnd = {"AlignVector", "false", "MaxVectorSize", ">= 4", "MaxVectorSize", "<= 14"}, applyIfCPUFeatureAnd = {"avx2", "true", "avx512bw", "false"}) // CPU: avx512bw -> vector_width: 64 -> elements in vector: 64 // positive byte_offset 14 can lead to cyclic dependency - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.MUL_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_B, "> 0", IRNode.MUL_VB, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIfAnd = {"AlignVector", "false", "MaxVectorSize", ">= 4", "MaxVectorSize", "<= 14"}, applyIfCPUFeature = {"avx512bw", "true"}) // CPU: asimd -> vector_width: 32 -> elements in vector: 32 // positive byte_offset 14 can lead to cyclic dependency - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.MUL_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_B, "> 0", IRNode.MUL_VB, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIfAnd = {"AlignVector", "false", "MaxVectorSize", ">= 4", "MaxVectorSize", "<= 14"}, applyIfCPUFeature = {"asimd", "true"}) public static void testByteP14(byte[] data) { @@ -7589,19 +7589,19 @@ public static void runByteP14() { @Test // CPU: sse4.1 to avx -> vector_width: 16 -> elements in vector: 16 - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.MUL_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_B, "> 0", IRNode.MUL_VB, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIfAnd = {"AlignVector", "false", "MaxVectorSize", ">= 4"}, applyIfCPUFeatureAnd = {"sse4.1", "true", "avx2", "false"}) // CPU: avx2 to avx512 without avx512bw -> vector_width: 32 -> elements in vector: 32 - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.MUL_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_B, "> 0", IRNode.MUL_VB, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIfAnd = {"AlignVector", "false", "MaxVectorSize", ">= 4"}, applyIfCPUFeatureAnd = {"avx2", "true", "avx512bw", "false"}) // CPU: avx512bw -> vector_width: 64 -> elements in vector: 64 - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.MUL_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_B, "> 0", IRNode.MUL_VB, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIfAnd = {"AlignVector", "false", "MaxVectorSize", ">= 4"}, applyIfCPUFeature = {"avx512bw", "true"}) // CPU: asimd -> vector_width: 32 -> elements in vector: 32 - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.MUL_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_B, "> 0", IRNode.MUL_VB, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIfAnd = {"AlignVector", "false", "MaxVectorSize", ">= 4"}, applyIfCPUFeature = {"asimd", "true"}) public static void testByteM16(byte[] data) { @@ -7621,26 +7621,26 @@ public static void runByteM16() { @Test // CPU: sse4.1 to avx -> vector_width: 16 -> elements in vector: 16 - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.MUL_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_B, "> 0", IRNode.MUL_VB, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIfAnd = {"AlignVector", "false", "MaxVectorSize", ">= 4"}, applyIfCPUFeatureAnd = {"sse4.1", "true", "avx2", "false"}) // Vectorize when strict alignment guaranteed. - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.MUL_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_B, "> 0", IRNode.MUL_VB, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIfAnd = {"AlignVector", "true", "MaxVectorSize", ">= 4"}, applyIfCPUFeatureAnd = {"sse4.1", "true", "avx2", "false"}) // CPU: avx2 to avx512 without avx512bw -> vector_width: 32 -> elements in vector: 32 // positive byte_offset 16 can lead to cyclic dependency - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.MUL_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_B, "> 0", IRNode.MUL_VB, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIfAnd = {"AlignVector", "false", "MaxVectorSize", ">= 4", "MaxVectorSize", "<= 16"}, applyIfCPUFeatureAnd = {"avx2", "true", "avx512bw", "false"}) // CPU: avx512bw -> vector_width: 64 -> elements in vector: 64 // positive byte_offset 16 can lead to cyclic dependency - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.MUL_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_B, "> 0", IRNode.MUL_VB, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIfAnd = {"AlignVector", "false", "MaxVectorSize", ">= 4", "MaxVectorSize", "<= 16"}, applyIfCPUFeature = {"avx512bw", "true"}) // CPU: asimd -> vector_width: 32 -> elements in vector: 32 // positive byte_offset 16 can lead to cyclic dependency - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.MUL_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_B, "> 0", IRNode.MUL_VB, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIfAnd = {"AlignVector", "false", "MaxVectorSize", ">= 4", "MaxVectorSize", "<= 16"}, applyIfCPUFeature = {"asimd", "true"}) public static void testByteP16(byte[] data) { @@ -7660,35 +7660,35 @@ public static void runByteP16() { @Test // CPU: sse4.1 to avx -> vector_width: 16 -> elements in vector: 16 - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.MUL_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_B, "> 0", IRNode.MUL_VB, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIfAnd = {"AlignVector", "false", "MaxVectorSize", ">= 4"}, applyIfCPUFeatureAnd = {"sse4.1", "true", "avx2", "false"}) // Strict alignment not possible. - @IR(failOn = {IRNode.LOAD_VECTOR, IRNode.MUL_V, IRNode.STORE_VECTOR}, + @IR(failOn = {IRNode.LOAD_VECTOR_B, IRNode.MUL_VB, IRNode.STORE_VECTOR}, applyIf = {"AlignVector", "true"}, applyIfCPUFeatureAnd = {"sse4.1", "true", "avx2", "false"}) // CPU: avx2 to avx512 without avx512bw -> vector_width: 32 -> elements in vector: 32 - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.MUL_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_B, "> 0", IRNode.MUL_VB, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIfAnd = {"AlignVector", "false", "MaxVectorSize", ">= 4"}, applyIfCPUFeatureAnd = {"avx2", "true", "avx512bw", "false"}) // Strict alignment not possible. - @IR(failOn = {IRNode.LOAD_VECTOR, IRNode.MUL_V, IRNode.STORE_VECTOR}, + @IR(failOn = {IRNode.LOAD_VECTOR_B, IRNode.MUL_VB, IRNode.STORE_VECTOR}, applyIf = {"AlignVector", "true"}, applyIfCPUFeatureAnd = {"avx2", "true", "avx512bw", "false"}) // CPU: avx512bw -> vector_width: 64 -> elements in vector: 64 - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.MUL_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_B, "> 0", IRNode.MUL_VB, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIfAnd = {"AlignVector", "false", "MaxVectorSize", ">= 4"}, applyIfCPUFeature = {"avx512bw", "true"}) // Strict alignment not possible. - @IR(failOn = {IRNode.LOAD_VECTOR, IRNode.MUL_V, IRNode.STORE_VECTOR}, + @IR(failOn = {IRNode.LOAD_VECTOR_B, IRNode.MUL_VB, IRNode.STORE_VECTOR}, applyIf = {"AlignVector", "true"}, applyIfCPUFeature = {"avx512bw", "true"}) // CPU: asimd -> vector_width: 32 -> elements in vector: 32 - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.MUL_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_B, "> 0", IRNode.MUL_VB, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIfAnd = {"AlignVector", "false", "MaxVectorSize", ">= 4"}, applyIfCPUFeature = {"asimd", "true"}) // Strict alignment not possible. - @IR(failOn = {IRNode.LOAD_VECTOR, IRNode.MUL_V, IRNode.STORE_VECTOR}, + @IR(failOn = {IRNode.LOAD_VECTOR_B, IRNode.MUL_VB, IRNode.STORE_VECTOR}, applyIf = {"AlignVector", "true"}, applyIfCPUFeature = {"asimd", "true"}) public static void testByteM18(byte[] data) { @@ -7708,22 +7708,22 @@ public static void runByteM18() { @Test // CPU: sse4.1 to avx -> vector_width: 16 -> elements in vector: 16 - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.MUL_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_B, "> 0", IRNode.MUL_VB, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIfAnd = {"AlignVector", "false", "MaxVectorSize", ">= 4"}, applyIfCPUFeatureAnd = {"sse4.1", "true", "avx2", "false"}) // CPU: avx2 to avx512 without avx512bw -> vector_width: 32 -> elements in vector: 32 // positive byte_offset 18 can lead to cyclic dependency - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.MUL_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_B, "> 0", IRNode.MUL_VB, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIfAnd = {"AlignVector", "false", "MaxVectorSize", ">= 4", "MaxVectorSize", "<= 18"}, applyIfCPUFeatureAnd = {"avx2", "true", "avx512bw", "false"}) // CPU: avx512bw -> vector_width: 64 -> elements in vector: 64 // positive byte_offset 18 can lead to cyclic dependency - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.MUL_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_B, "> 0", IRNode.MUL_VB, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIfAnd = {"AlignVector", "false", "MaxVectorSize", ">= 4", "MaxVectorSize", "<= 18"}, applyIfCPUFeature = {"avx512bw", "true"}) // CPU: asimd -> vector_width: 32 -> elements in vector: 32 // positive byte_offset 18 can lead to cyclic dependency - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.MUL_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_B, "> 0", IRNode.MUL_VB, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIfAnd = {"AlignVector", "false", "MaxVectorSize", ">= 4", "MaxVectorSize", "<= 18"}, applyIfCPUFeature = {"asimd", "true"}) public static void testByteP18(byte[] data) { @@ -7743,19 +7743,19 @@ public static void runByteP18() { @Test // CPU: sse4.1 to avx -> vector_width: 16 -> elements in vector: 16 - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.MUL_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_B, "> 0", IRNode.MUL_VB, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIfAnd = {"AlignVector", "false", "MaxVectorSize", ">= 4"}, applyIfCPUFeatureAnd = {"sse4.1", "true", "avx2", "false"}) // CPU: avx2 to avx512 without avx512bw -> vector_width: 32 -> elements in vector: 32 - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.MUL_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_B, "> 0", IRNode.MUL_VB, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIfAnd = {"AlignVector", "false", "MaxVectorSize", ">= 4"}, applyIfCPUFeatureAnd = {"avx2", "true", "avx512bw", "false"}) // CPU: avx512bw -> vector_width: 64 -> elements in vector: 64 - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.MUL_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_B, "> 0", IRNode.MUL_VB, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIfAnd = {"AlignVector", "false", "MaxVectorSize", ">= 4"}, applyIfCPUFeature = {"avx512bw", "true"}) // CPU: asimd -> vector_width: 32 -> elements in vector: 32 - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.MUL_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_B, "> 0", IRNode.MUL_VB, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIfAnd = {"AlignVector", "false", "MaxVectorSize", ">= 4"}, applyIfCPUFeature = {"asimd", "true"}) public static void testByteM20(byte[] data) { @@ -7775,22 +7775,22 @@ public static void runByteM20() { @Test // CPU: sse4.1 to avx -> vector_width: 16 -> elements in vector: 16 - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.MUL_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_B, "> 0", IRNode.MUL_VB, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIfAnd = {"AlignVector", "false", "MaxVectorSize", ">= 4"}, applyIfCPUFeatureAnd = {"sse4.1", "true", "avx2", "false"}) // CPU: avx2 to avx512 without avx512bw -> vector_width: 32 -> elements in vector: 32 // positive byte_offset 20 can lead to cyclic dependency - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.MUL_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_B, "> 0", IRNode.MUL_VB, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIfAnd = {"AlignVector", "false", "MaxVectorSize", ">= 4", "MaxVectorSize", "<= 20"}, applyIfCPUFeatureAnd = {"avx2", "true", "avx512bw", "false"}) // CPU: avx512bw -> vector_width: 64 -> elements in vector: 64 // positive byte_offset 20 can lead to cyclic dependency - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.MUL_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_B, "> 0", IRNode.MUL_VB, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIfAnd = {"AlignVector", "false", "MaxVectorSize", ">= 4", "MaxVectorSize", "<= 20"}, applyIfCPUFeature = {"avx512bw", "true"}) // CPU: asimd -> vector_width: 32 -> elements in vector: 32 // positive byte_offset 20 can lead to cyclic dependency - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.MUL_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_B, "> 0", IRNode.MUL_VB, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIfAnd = {"AlignVector", "false", "MaxVectorSize", ">= 4", "MaxVectorSize", "<= 20"}, applyIfCPUFeature = {"asimd", "true"}) public static void testByteP20(byte[] data) { @@ -7810,35 +7810,35 @@ public static void runByteP20() { @Test // CPU: sse4.1 to avx -> vector_width: 16 -> elements in vector: 16 - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.MUL_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_B, "> 0", IRNode.MUL_VB, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIfAnd = {"AlignVector", "false", "MaxVectorSize", ">= 4"}, applyIfCPUFeatureAnd = {"sse4.1", "true", "avx2", "false"}) // Strict alignment not possible. - @IR(failOn = {IRNode.LOAD_VECTOR, IRNode.MUL_V, IRNode.STORE_VECTOR}, + @IR(failOn = {IRNode.LOAD_VECTOR_B, IRNode.MUL_VB, IRNode.STORE_VECTOR}, applyIf = {"AlignVector", "true"}, applyIfCPUFeatureAnd = {"sse4.1", "true", "avx2", "false"}) // CPU: avx2 to avx512 without avx512bw -> vector_width: 32 -> elements in vector: 32 - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.MUL_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_B, "> 0", IRNode.MUL_VB, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIfAnd = {"AlignVector", "false", "MaxVectorSize", ">= 4"}, applyIfCPUFeatureAnd = {"avx2", "true", "avx512bw", "false"}) // Strict alignment not possible. - @IR(failOn = {IRNode.LOAD_VECTOR, IRNode.MUL_V, IRNode.STORE_VECTOR}, + @IR(failOn = {IRNode.LOAD_VECTOR_B, IRNode.MUL_VB, IRNode.STORE_VECTOR}, applyIf = {"AlignVector", "true"}, applyIfCPUFeatureAnd = {"avx2", "true", "avx512bw", "false"}) // CPU: avx512bw -> vector_width: 64 -> elements in vector: 64 - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.MUL_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_B, "> 0", IRNode.MUL_VB, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIfAnd = {"AlignVector", "false", "MaxVectorSize", ">= 4"}, applyIfCPUFeature = {"avx512bw", "true"}) // Strict alignment not possible. - @IR(failOn = {IRNode.LOAD_VECTOR, IRNode.MUL_V, IRNode.STORE_VECTOR}, + @IR(failOn = {IRNode.LOAD_VECTOR_B, IRNode.MUL_VB, IRNode.STORE_VECTOR}, applyIf = {"AlignVector", "true"}, applyIfCPUFeature = {"avx512bw", "true"}) // CPU: asimd -> vector_width: 32 -> elements in vector: 32 - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.MUL_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_B, "> 0", IRNode.MUL_VB, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIfAnd = {"AlignVector", "false", "MaxVectorSize", ">= 4"}, applyIfCPUFeature = {"asimd", "true"}) // Strict alignment not possible. - @IR(failOn = {IRNode.LOAD_VECTOR, IRNode.MUL_V, IRNode.STORE_VECTOR}, + @IR(failOn = {IRNode.LOAD_VECTOR_B, IRNode.MUL_VB, IRNode.STORE_VECTOR}, applyIf = {"AlignVector", "true"}, applyIfCPUFeature = {"asimd", "true"}) public static void testByteM31(byte[] data) { @@ -7858,22 +7858,22 @@ public static void runByteM31() { @Test // CPU: sse4.1 to avx -> vector_width: 16 -> elements in vector: 16 - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.MUL_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_B, "> 0", IRNode.MUL_VB, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIfAnd = {"AlignVector", "false", "MaxVectorSize", ">= 4"}, applyIfCPUFeatureAnd = {"sse4.1", "true", "avx2", "false"}) // CPU: avx2 to avx512 without avx512bw -> vector_width: 32 -> elements in vector: 32 // positive byte_offset 31 can lead to cyclic dependency - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.MUL_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_B, "> 0", IRNode.MUL_VB, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIfAnd = {"AlignVector", "false", "MaxVectorSize", ">= 4", "MaxVectorSize", "<= 31"}, applyIfCPUFeatureAnd = {"avx2", "true", "avx512bw", "false"}) // CPU: avx512bw -> vector_width: 64 -> elements in vector: 64 // positive byte_offset 31 can lead to cyclic dependency - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.MUL_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_B, "> 0", IRNode.MUL_VB, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIfAnd = {"AlignVector", "false", "MaxVectorSize", ">= 4", "MaxVectorSize", "<= 31"}, applyIfCPUFeature = {"avx512bw", "true"}) // CPU: asimd -> vector_width: 32 -> elements in vector: 32 // positive byte_offset 31 can lead to cyclic dependency - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.MUL_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_B, "> 0", IRNode.MUL_VB, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIfAnd = {"AlignVector", "false", "MaxVectorSize", ">= 4", "MaxVectorSize", "<= 31"}, applyIfCPUFeature = {"asimd", "true"}) public static void testByteP31(byte[] data) { @@ -7893,19 +7893,19 @@ public static void runByteP31() { @Test // CPU: sse4.1 to avx -> vector_width: 16 -> elements in vector: 16 - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.MUL_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_B, "> 0", IRNode.MUL_VB, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIfAnd = {"AlignVector", "false", "MaxVectorSize", ">= 4"}, applyIfCPUFeatureAnd = {"sse4.1", "true", "avx2", "false"}) // CPU: avx2 to avx512 without avx512bw -> vector_width: 32 -> elements in vector: 32 - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.MUL_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_B, "> 0", IRNode.MUL_VB, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIfAnd = {"AlignVector", "false", "MaxVectorSize", ">= 4"}, applyIfCPUFeatureAnd = {"avx2", "true", "avx512bw", "false"}) // CPU: avx512bw -> vector_width: 64 -> elements in vector: 64 - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.MUL_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_B, "> 0", IRNode.MUL_VB, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIfAnd = {"AlignVector", "false", "MaxVectorSize", ">= 4"}, applyIfCPUFeature = {"avx512bw", "true"}) // CPU: asimd -> vector_width: 32 -> elements in vector: 32 - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.MUL_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_B, "> 0", IRNode.MUL_VB, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIfAnd = {"AlignVector", "false", "MaxVectorSize", ">= 4"}, applyIfCPUFeature = {"asimd", "true"}) public static void testByteM32(byte[] data) { @@ -7925,32 +7925,32 @@ public static void runByteM32() { @Test // CPU: sse4.1 to avx -> vector_width: 16 -> elements in vector: 16 - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.MUL_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_B, "> 0", IRNode.MUL_VB, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIfAnd = {"AlignVector", "false", "MaxVectorSize", ">= 4"}, applyIfCPUFeatureAnd = {"sse4.1", "true", "avx2", "false"}) // Vectorize when strict alignment guaranteed. - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.MUL_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_B, "> 0", IRNode.MUL_VB, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIfAnd = {"AlignVector", "true", "MaxVectorSize", ">= 4"}, applyIfCPUFeatureAnd = {"sse4.1", "true", "avx2", "false"}) // CPU: avx2 to avx512 without avx512bw -> vector_width: 32 -> elements in vector: 32 - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.MUL_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_B, "> 0", IRNode.MUL_VB, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIfAnd = {"AlignVector", "false", "MaxVectorSize", ">= 4"}, applyIfCPUFeatureAnd = {"avx2", "true", "avx512bw", "false"}) // Vectorize when strict alignment guaranteed. - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.MUL_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_B, "> 0", IRNode.MUL_VB, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIfAnd = {"AlignVector", "true", "MaxVectorSize", ">= 4"}, applyIfCPUFeatureAnd = {"avx2", "true", "avx512bw", "false"}) // CPU: avx512bw -> vector_width: 64 -> elements in vector: 64 // positive byte_offset 32 can lead to cyclic dependency - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.MUL_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_B, "> 0", IRNode.MUL_VB, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIfAnd = {"AlignVector", "false", "MaxVectorSize", ">= 4", "MaxVectorSize", "<= 32"}, applyIfCPUFeature = {"avx512bw", "true"}) // CPU: asimd -> vector_width: 32 -> elements in vector: 32 - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.MUL_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_B, "> 0", IRNode.MUL_VB, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIfAnd = {"AlignVector", "false", "MaxVectorSize", ">= 4"}, applyIfCPUFeature = {"asimd", "true"}) // Vectorize when strict alignment guaranteed. - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.MUL_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_B, "> 0", IRNode.MUL_VB, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIfAnd = {"AlignVector", "true", "MaxVectorSize", ">= 4"}, applyIfCPUFeature = {"asimd", "true"}) public static void testByteP32(byte[] data) { @@ -7970,35 +7970,35 @@ public static void runByteP32() { @Test // CPU: sse4.1 to avx -> vector_width: 16 -> elements in vector: 16 - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.MUL_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_B, "> 0", IRNode.MUL_VB, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIfAnd = {"AlignVector", "false", "MaxVectorSize", ">= 4"}, applyIfCPUFeatureAnd = {"sse4.1", "true", "avx2", "false"}) // Strict alignment not possible. - @IR(failOn = {IRNode.LOAD_VECTOR, IRNode.MUL_V, IRNode.STORE_VECTOR}, + @IR(failOn = {IRNode.LOAD_VECTOR_B, IRNode.MUL_VB, IRNode.STORE_VECTOR}, applyIf = {"AlignVector", "true"}, applyIfCPUFeatureAnd = {"sse4.1", "true", "avx2", "false"}) // CPU: avx2 to avx512 without avx512bw -> vector_width: 32 -> elements in vector: 32 - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.MUL_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_B, "> 0", IRNode.MUL_VB, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIfAnd = {"AlignVector", "false", "MaxVectorSize", ">= 4"}, applyIfCPUFeatureAnd = {"avx2", "true", "avx512bw", "false"}) // Strict alignment not possible. - @IR(failOn = {IRNode.LOAD_VECTOR, IRNode.MUL_V, IRNode.STORE_VECTOR}, + @IR(failOn = {IRNode.LOAD_VECTOR_B, IRNode.MUL_VB, IRNode.STORE_VECTOR}, applyIf = {"AlignVector", "true"}, applyIfCPUFeatureAnd = {"avx2", "true", "avx512bw", "false"}) // CPU: avx512bw -> vector_width: 64 -> elements in vector: 64 - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.MUL_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_B, "> 0", IRNode.MUL_VB, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIfAnd = {"AlignVector", "false", "MaxVectorSize", ">= 4"}, applyIfCPUFeature = {"avx512bw", "true"}) // Strict alignment not possible. - @IR(failOn = {IRNode.LOAD_VECTOR, IRNode.MUL_V, IRNode.STORE_VECTOR}, + @IR(failOn = {IRNode.LOAD_VECTOR_B, IRNode.MUL_VB, IRNode.STORE_VECTOR}, applyIf = {"AlignVector", "true"}, applyIfCPUFeature = {"avx512bw", "true"}) // CPU: asimd -> vector_width: 32 -> elements in vector: 32 - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.MUL_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_B, "> 0", IRNode.MUL_VB, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIfAnd = {"AlignVector", "false", "MaxVectorSize", ">= 4"}, applyIfCPUFeature = {"asimd", "true"}) // Strict alignment not possible. - @IR(failOn = {IRNode.LOAD_VECTOR, IRNode.MUL_V, IRNode.STORE_VECTOR}, + @IR(failOn = {IRNode.LOAD_VECTOR_B, IRNode.MUL_VB, IRNode.STORE_VECTOR}, applyIf = {"AlignVector", "true"}, applyIfCPUFeature = {"asimd", "true"}) public static void testByteM63(byte[] data) { @@ -8018,20 +8018,20 @@ public static void runByteM63() { @Test // CPU: sse4.1 to avx -> vector_width: 16 -> elements in vector: 16 - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.MUL_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_B, "> 0", IRNode.MUL_VB, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIfAnd = {"AlignVector", "false", "MaxVectorSize", ">= 4"}, applyIfCPUFeatureAnd = {"sse4.1", "true", "avx2", "false"}) // CPU: avx2 to avx512 without avx512bw -> vector_width: 32 -> elements in vector: 32 - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.MUL_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_B, "> 0", IRNode.MUL_VB, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIfAnd = {"AlignVector", "false", "MaxVectorSize", ">= 4"}, applyIfCPUFeatureAnd = {"avx2", "true", "avx512bw", "false"}) // CPU: avx512bw -> vector_width: 64 -> elements in vector: 64 // positive byte_offset 63 can lead to cyclic dependency - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.MUL_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_B, "> 0", IRNode.MUL_VB, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIfAnd = {"AlignVector", "false", "MaxVectorSize", ">= 4", "MaxVectorSize", "<= 63"}, applyIfCPUFeature = {"avx512bw", "true"}) // CPU: asimd -> vector_width: 32 -> elements in vector: 32 - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.MUL_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_B, "> 0", IRNode.MUL_VB, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIfAnd = {"AlignVector", "false", "MaxVectorSize", ">= 4"}, applyIfCPUFeature = {"asimd", "true"}) public static void testByteP63(byte[] data) { @@ -8051,19 +8051,19 @@ public static void runByteP63() { @Test // CPU: sse4.1 to avx -> vector_width: 16 -> elements in vector: 16 - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.MUL_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_B, "> 0", IRNode.MUL_VB, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIfAnd = {"AlignVector", "false", "MaxVectorSize", ">= 4"}, applyIfCPUFeatureAnd = {"sse4.1", "true", "avx2", "false"}) // CPU: avx2 to avx512 without avx512bw -> vector_width: 32 -> elements in vector: 32 - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.MUL_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_B, "> 0", IRNode.MUL_VB, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIfAnd = {"AlignVector", "false", "MaxVectorSize", ">= 4"}, applyIfCPUFeatureAnd = {"avx2", "true", "avx512bw", "false"}) // CPU: avx512bw -> vector_width: 64 -> elements in vector: 64 - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.MUL_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_B, "> 0", IRNode.MUL_VB, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIfAnd = {"AlignVector", "false", "MaxVectorSize", ">= 4"}, applyIfCPUFeature = {"avx512bw", "true"}) // CPU: asimd -> vector_width: 32 -> elements in vector: 32 - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.MUL_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_B, "> 0", IRNode.MUL_VB, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIfAnd = {"AlignVector", "false", "MaxVectorSize", ">= 4"}, applyIfCPUFeature = {"asimd", "true"}) public static void testByteM64(byte[] data) { @@ -8083,35 +8083,35 @@ public static void runByteM64() { @Test // CPU: sse4.1 to avx -> vector_width: 16 -> elements in vector: 16 - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.MUL_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_B, "> 0", IRNode.MUL_VB, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIfAnd = {"AlignVector", "false", "MaxVectorSize", ">= 4"}, applyIfCPUFeatureAnd = {"sse4.1", "true", "avx2", "false"}) // Vectorize when strict alignment guaranteed. - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.MUL_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_B, "> 0", IRNode.MUL_VB, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIfAnd = {"AlignVector", "true", "MaxVectorSize", ">= 4"}, applyIfCPUFeatureAnd = {"sse4.1", "true", "avx2", "false"}) // CPU: avx2 to avx512 without avx512bw -> vector_width: 32 -> elements in vector: 32 - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.MUL_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_B, "> 0", IRNode.MUL_VB, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIfAnd = {"AlignVector", "false", "MaxVectorSize", ">= 4"}, applyIfCPUFeatureAnd = {"avx2", "true", "avx512bw", "false"}) // Vectorize when strict alignment guaranteed. - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.MUL_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_B, "> 0", IRNode.MUL_VB, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIfAnd = {"AlignVector", "true", "MaxVectorSize", ">= 4"}, applyIfCPUFeatureAnd = {"avx2", "true", "avx512bw", "false"}) // CPU: avx512bw -> vector_width: 64 -> elements in vector: 64 - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.MUL_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_B, "> 0", IRNode.MUL_VB, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIfAnd = {"AlignVector", "false", "MaxVectorSize", ">= 4"}, applyIfCPUFeature = {"avx512bw", "true"}) // Vectorize when strict alignment guaranteed. - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.MUL_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_B, "> 0", IRNode.MUL_VB, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIfAnd = {"AlignVector", "true", "MaxVectorSize", ">= 4"}, applyIfCPUFeature = {"avx512bw", "true"}) // CPU: asimd -> vector_width: 32 -> elements in vector: 32 - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.MUL_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_B, "> 0", IRNode.MUL_VB, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIfAnd = {"AlignVector", "false", "MaxVectorSize", ">= 4"}, applyIfCPUFeature = {"asimd", "true"}) // Vectorize when strict alignment guaranteed. - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.MUL_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_B, "> 0", IRNode.MUL_VB, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIfAnd = {"AlignVector", "true", "MaxVectorSize", ">= 4"}, applyIfCPUFeature = {"asimd", "true"}) public static void testByteP64(byte[] data) { @@ -8131,35 +8131,35 @@ public static void runByteP64() { @Test // CPU: sse4.1 to avx -> vector_width: 16 -> elements in vector: 16 - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.MUL_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_B, "> 0", IRNode.MUL_VB, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIfAnd = {"AlignVector", "false", "MaxVectorSize", ">= 4"}, applyIfCPUFeatureAnd = {"sse4.1", "true", "avx2", "false"}) // Strict alignment not possible. - @IR(failOn = {IRNode.LOAD_VECTOR, IRNode.MUL_V, IRNode.STORE_VECTOR}, + @IR(failOn = {IRNode.LOAD_VECTOR_B, IRNode.MUL_VB, IRNode.STORE_VECTOR}, applyIf = {"AlignVector", "true"}, applyIfCPUFeatureAnd = {"sse4.1", "true", "avx2", "false"}) // CPU: avx2 to avx512 without avx512bw -> vector_width: 32 -> elements in vector: 32 - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.MUL_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_B, "> 0", IRNode.MUL_VB, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIfAnd = {"AlignVector", "false", "MaxVectorSize", ">= 4"}, applyIfCPUFeatureAnd = {"avx2", "true", "avx512bw", "false"}) // Strict alignment not possible. - @IR(failOn = {IRNode.LOAD_VECTOR, IRNode.MUL_V, IRNode.STORE_VECTOR}, + @IR(failOn = {IRNode.LOAD_VECTOR_B, IRNode.MUL_VB, IRNode.STORE_VECTOR}, applyIf = {"AlignVector", "true"}, applyIfCPUFeatureAnd = {"avx2", "true", "avx512bw", "false"}) // CPU: avx512bw -> vector_width: 64 -> elements in vector: 64 - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.MUL_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_B, "> 0", IRNode.MUL_VB, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIfAnd = {"AlignVector", "false", "MaxVectorSize", ">= 4"}, applyIfCPUFeature = {"avx512bw", "true"}) // Strict alignment not possible. - @IR(failOn = {IRNode.LOAD_VECTOR, IRNode.MUL_V, IRNode.STORE_VECTOR}, + @IR(failOn = {IRNode.LOAD_VECTOR_B, IRNode.MUL_VB, IRNode.STORE_VECTOR}, applyIf = {"AlignVector", "true"}, applyIfCPUFeature = {"avx512bw", "true"}) // CPU: asimd -> vector_width: 32 -> elements in vector: 32 - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.MUL_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_B, "> 0", IRNode.MUL_VB, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIfAnd = {"AlignVector", "false", "MaxVectorSize", ">= 4"}, applyIfCPUFeature = {"asimd", "true"}) // Strict alignment not possible. - @IR(failOn = {IRNode.LOAD_VECTOR, IRNode.MUL_V, IRNode.STORE_VECTOR}, + @IR(failOn = {IRNode.LOAD_VECTOR_B, IRNode.MUL_VB, IRNode.STORE_VECTOR}, applyIf = {"AlignVector", "true"}, applyIfCPUFeature = {"asimd", "true"}) public static void testByteM65(byte[] data) { @@ -8179,19 +8179,19 @@ public static void runByteM65() { @Test // CPU: sse4.1 to avx -> vector_width: 16 -> elements in vector: 16 - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.MUL_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_B, "> 0", IRNode.MUL_VB, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIfAnd = {"AlignVector", "false", "MaxVectorSize", ">= 4"}, applyIfCPUFeatureAnd = {"sse4.1", "true", "avx2", "false"}) // CPU: avx2 to avx512 without avx512bw -> vector_width: 32 -> elements in vector: 32 - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.MUL_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_B, "> 0", IRNode.MUL_VB, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIfAnd = {"AlignVector", "false", "MaxVectorSize", ">= 4"}, applyIfCPUFeatureAnd = {"avx2", "true", "avx512bw", "false"}) // CPU: avx512bw -> vector_width: 64 -> elements in vector: 64 - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.MUL_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_B, "> 0", IRNode.MUL_VB, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIfAnd = {"AlignVector", "false", "MaxVectorSize", ">= 4"}, applyIfCPUFeature = {"avx512bw", "true"}) // CPU: asimd -> vector_width: 32 -> elements in vector: 32 - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.MUL_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_B, "> 0", IRNode.MUL_VB, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIfAnd = {"AlignVector", "false", "MaxVectorSize", ">= 4"}, applyIfCPUFeature = {"asimd", "true"}) public static void testByteP65(byte[] data) { @@ -8211,19 +8211,19 @@ public static void runByteP65() { @Test // CPU: sse4.1 to avx -> vector_width: 16 -> elements in vector: 16 - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.MUL_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_B, "> 0", IRNode.MUL_VB, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIfAnd = {"AlignVector", "false", "MaxVectorSize", ">= 4"}, applyIfCPUFeatureAnd = {"sse4.1", "true", "avx2", "false"}) // CPU: avx2 to avx512 without avx512bw -> vector_width: 32 -> elements in vector: 32 - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.MUL_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_B, "> 0", IRNode.MUL_VB, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIfAnd = {"AlignVector", "false", "MaxVectorSize", ">= 4"}, applyIfCPUFeatureAnd = {"avx2", "true", "avx512bw", "false"}) // CPU: avx512bw -> vector_width: 64 -> elements in vector: 64 - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.MUL_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_B, "> 0", IRNode.MUL_VB, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIfAnd = {"AlignVector", "false", "MaxVectorSize", ">= 4"}, applyIfCPUFeature = {"avx512bw", "true"}) // CPU: asimd -> vector_width: 32 -> elements in vector: 32 - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.MUL_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_B, "> 0", IRNode.MUL_VB, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIfAnd = {"AlignVector", "false", "MaxVectorSize", ">= 4"}, applyIfCPUFeature = {"asimd", "true"}) public static void testByteM128(byte[] data) { @@ -8243,35 +8243,35 @@ public static void runByteM128() { @Test // CPU: sse4.1 to avx -> vector_width: 16 -> elements in vector: 16 - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.MUL_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_B, "> 0", IRNode.MUL_VB, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIfAnd = {"AlignVector", "false", "MaxVectorSize", ">= 4"}, applyIfCPUFeatureAnd = {"sse4.1", "true", "avx2", "false"}) // Vectorize when strict alignment guaranteed. - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.MUL_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_B, "> 0", IRNode.MUL_VB, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIfAnd = {"AlignVector", "true", "MaxVectorSize", ">= 4"}, applyIfCPUFeatureAnd = {"sse4.1", "true", "avx2", "false"}) // CPU: avx2 to avx512 without avx512bw -> vector_width: 32 -> elements in vector: 32 - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.MUL_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_B, "> 0", IRNode.MUL_VB, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIfAnd = {"AlignVector", "false", "MaxVectorSize", ">= 4"}, applyIfCPUFeatureAnd = {"avx2", "true", "avx512bw", "false"}) // Vectorize when strict alignment guaranteed. - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.MUL_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_B, "> 0", IRNode.MUL_VB, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIfAnd = {"AlignVector", "true", "MaxVectorSize", ">= 4"}, applyIfCPUFeatureAnd = {"avx2", "true", "avx512bw", "false"}) // CPU: avx512bw -> vector_width: 64 -> elements in vector: 64 - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.MUL_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_B, "> 0", IRNode.MUL_VB, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIfAnd = {"AlignVector", "false", "MaxVectorSize", ">= 4"}, applyIfCPUFeature = {"avx512bw", "true"}) // Vectorize when strict alignment guaranteed. - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.MUL_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_B, "> 0", IRNode.MUL_VB, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIfAnd = {"AlignVector", "true", "MaxVectorSize", ">= 4"}, applyIfCPUFeature = {"avx512bw", "true"}) // CPU: asimd -> vector_width: 32 -> elements in vector: 32 - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.MUL_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_B, "> 0", IRNode.MUL_VB, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIfAnd = {"AlignVector", "false", "MaxVectorSize", ">= 4"}, applyIfCPUFeature = {"asimd", "true"}) // Vectorize when strict alignment guaranteed. - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.MUL_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_B, "> 0", IRNode.MUL_VB, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIfAnd = {"AlignVector", "true", "MaxVectorSize", ">= 4"}, applyIfCPUFeature = {"asimd", "true"}) public static void testByteP128(byte[] data) { @@ -8291,35 +8291,35 @@ public static void runByteP128() { @Test // CPU: sse4.1 to avx -> vector_width: 16 -> elements in vector: 16 - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.MUL_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_B, "> 0", IRNode.MUL_VB, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIfAnd = {"AlignVector", "false", "MaxVectorSize", ">= 4"}, applyIfCPUFeatureAnd = {"sse4.1", "true", "avx2", "false"}) // Strict alignment not possible. - @IR(failOn = {IRNode.LOAD_VECTOR, IRNode.MUL_V, IRNode.STORE_VECTOR}, + @IR(failOn = {IRNode.LOAD_VECTOR_B, IRNode.MUL_VB, IRNode.STORE_VECTOR}, applyIf = {"AlignVector", "true"}, applyIfCPUFeatureAnd = {"sse4.1", "true", "avx2", "false"}) // CPU: avx2 to avx512 without avx512bw -> vector_width: 32 -> elements in vector: 32 - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.MUL_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_B, "> 0", IRNode.MUL_VB, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIfAnd = {"AlignVector", "false", "MaxVectorSize", ">= 4"}, applyIfCPUFeatureAnd = {"avx2", "true", "avx512bw", "false"}) // Strict alignment not possible. - @IR(failOn = {IRNode.LOAD_VECTOR, IRNode.MUL_V, IRNode.STORE_VECTOR}, + @IR(failOn = {IRNode.LOAD_VECTOR_B, IRNode.MUL_VB, IRNode.STORE_VECTOR}, applyIf = {"AlignVector", "true"}, applyIfCPUFeatureAnd = {"avx2", "true", "avx512bw", "false"}) // CPU: avx512bw -> vector_width: 64 -> elements in vector: 64 - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.MUL_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_B, "> 0", IRNode.MUL_VB, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIfAnd = {"AlignVector", "false", "MaxVectorSize", ">= 4"}, applyIfCPUFeature = {"avx512bw", "true"}) // Strict alignment not possible. - @IR(failOn = {IRNode.LOAD_VECTOR, IRNode.MUL_V, IRNode.STORE_VECTOR}, + @IR(failOn = {IRNode.LOAD_VECTOR_B, IRNode.MUL_VB, IRNode.STORE_VECTOR}, applyIf = {"AlignVector", "true"}, applyIfCPUFeature = {"avx512bw", "true"}) // CPU: asimd -> vector_width: 32 -> elements in vector: 32 - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.MUL_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_B, "> 0", IRNode.MUL_VB, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIfAnd = {"AlignVector", "false", "MaxVectorSize", ">= 4"}, applyIfCPUFeature = {"asimd", "true"}) // Strict alignment not possible. - @IR(failOn = {IRNode.LOAD_VECTOR, IRNode.MUL_V, IRNode.STORE_VECTOR}, + @IR(failOn = {IRNode.LOAD_VECTOR_B, IRNode.MUL_VB, IRNode.STORE_VECTOR}, applyIf = {"AlignVector", "true"}, applyIfCPUFeature = {"asimd", "true"}) public static void testByteM129(byte[] data) { @@ -8339,19 +8339,19 @@ public static void runByteM129() { @Test // CPU: sse4.1 to avx -> vector_width: 16 -> elements in vector: 16 - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.MUL_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_B, "> 0", IRNode.MUL_VB, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIfAnd = {"AlignVector", "false", "MaxVectorSize", ">= 4"}, applyIfCPUFeatureAnd = {"sse4.1", "true", "avx2", "false"}) // CPU: avx2 to avx512 without avx512bw -> vector_width: 32 -> elements in vector: 32 - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.MUL_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_B, "> 0", IRNode.MUL_VB, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIfAnd = {"AlignVector", "false", "MaxVectorSize", ">= 4"}, applyIfCPUFeatureAnd = {"avx2", "true", "avx512bw", "false"}) // CPU: avx512bw -> vector_width: 64 -> elements in vector: 64 - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.MUL_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_B, "> 0", IRNode.MUL_VB, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIfAnd = {"AlignVector", "false", "MaxVectorSize", ">= 4"}, applyIfCPUFeature = {"avx512bw", "true"}) // CPU: asimd -> vector_width: 32 -> elements in vector: 32 - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.MUL_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_B, "> 0", IRNode.MUL_VB, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIfAnd = {"AlignVector", "false", "MaxVectorSize", ">= 4"}, applyIfCPUFeature = {"asimd", "true"}) public static void testByteP129(byte[] data) { @@ -8371,19 +8371,19 @@ public static void runByteP129() { @Test // CPU: sse4.1 to avx -> vector_width: 16 -> elements in vector: 16 - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.MUL_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_B, "> 0", IRNode.MUL_VB, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIfAnd = {"AlignVector", "false", "MaxVectorSize", ">= 4"}, applyIfCPUFeatureAnd = {"sse4.1", "true", "avx2", "false"}) // CPU: avx2 to avx512 without avx512bw -> vector_width: 32 -> elements in vector: 32 - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.MUL_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_B, "> 0", IRNode.MUL_VB, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIfAnd = {"AlignVector", "false", "MaxVectorSize", ">= 4"}, applyIfCPUFeatureAnd = {"avx2", "true", "avx512bw", "false"}) // CPU: avx512bw -> vector_width: 64 -> elements in vector: 64 - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.MUL_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_B, "> 0", IRNode.MUL_VB, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIfAnd = {"AlignVector", "false", "MaxVectorSize", ">= 4"}, applyIfCPUFeature = {"avx512bw", "true"}) // CPU: asimd -> vector_width: 32 -> elements in vector: 32 - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.MUL_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_B, "> 0", IRNode.MUL_VB, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIfAnd = {"AlignVector", "false", "MaxVectorSize", ">= 4"}, applyIfCPUFeature = {"asimd", "true"}) public static void testByteM192(byte[] data) { @@ -8403,35 +8403,35 @@ public static void runByteM192() { @Test // CPU: sse4.1 to avx -> vector_width: 16 -> elements in vector: 16 - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.MUL_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_B, "> 0", IRNode.MUL_VB, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIfAnd = {"AlignVector", "false", "MaxVectorSize", ">= 4"}, applyIfCPUFeatureAnd = {"sse4.1", "true", "avx2", "false"}) // Vectorize when strict alignment guaranteed. - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.MUL_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_B, "> 0", IRNode.MUL_VB, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIfAnd = {"AlignVector", "true", "MaxVectorSize", ">= 4"}, applyIfCPUFeatureAnd = {"sse4.1", "true", "avx2", "false"}) // CPU: avx2 to avx512 without avx512bw -> vector_width: 32 -> elements in vector: 32 - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.MUL_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_B, "> 0", IRNode.MUL_VB, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIfAnd = {"AlignVector", "false", "MaxVectorSize", ">= 4"}, applyIfCPUFeatureAnd = {"avx2", "true", "avx512bw", "false"}) // Vectorize when strict alignment guaranteed. - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.MUL_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_B, "> 0", IRNode.MUL_VB, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIfAnd = {"AlignVector", "true", "MaxVectorSize", ">= 4"}, applyIfCPUFeatureAnd = {"avx2", "true", "avx512bw", "false"}) // CPU: avx512bw -> vector_width: 64 -> elements in vector: 64 - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.MUL_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_B, "> 0", IRNode.MUL_VB, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIfAnd = {"AlignVector", "false", "MaxVectorSize", ">= 4"}, applyIfCPUFeature = {"avx512bw", "true"}) // Vectorize when strict alignment guaranteed. - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.MUL_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_B, "> 0", IRNode.MUL_VB, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIfAnd = {"AlignVector", "true", "MaxVectorSize", ">= 4"}, applyIfCPUFeature = {"avx512bw", "true"}) // CPU: asimd -> vector_width: 32 -> elements in vector: 32 - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.MUL_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_B, "> 0", IRNode.MUL_VB, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIfAnd = {"AlignVector", "false", "MaxVectorSize", ">= 4"}, applyIfCPUFeature = {"asimd", "true"}) // Vectorize when strict alignment guaranteed. - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.MUL_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_B, "> 0", IRNode.MUL_VB, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIfAnd = {"AlignVector", "true", "MaxVectorSize", ">= 4"}, applyIfCPUFeature = {"asimd", "true"}) public static void testByteP192(byte[] data) { @@ -8451,19 +8451,19 @@ public static void runByteP192() { @Test // CPU: sse4.1 -> vector_width: 16 -> elements in vector: 4 - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.MUL_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_F, "> 0", IRNode.MUL_VF, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIfAnd = {"AlignVector", "false", "MaxVectorSize", ">= 8"}, applyIfCPUFeatureAnd = {"sse4.1", "true", "avx", "false"}) // CPU: avx and avx2 -> vector_width: 32 -> elements in vector: 8 - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.MUL_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_F, "> 0", IRNode.MUL_VF, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIfAnd = {"AlignVector", "false", "MaxVectorSize", ">= 8"}, applyIfCPUFeatureAnd = {"avx", "true", "avx512", "false"}) // CPU: avx512 -> vector_width: 64 -> elements in vector: 16 - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.MUL_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_F, "> 0", IRNode.MUL_VF, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIfAnd = {"AlignVector", "false", "MaxVectorSize", ">= 8"}, applyIfCPUFeature = {"avx512", "true"}) // CPU: asimd -> vector_width: 32 -> elements in vector: 8 - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.MUL_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_F, "> 0", IRNode.MUL_VF, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIfAnd = {"AlignVector", "false", "MaxVectorSize", ">= 8"}, applyIfCPUFeature = {"asimd", "true"}) public static void testFloatP0(float[] data) { @@ -8483,35 +8483,35 @@ public static void runFloatP0() { @Test // CPU: sse4.1 -> vector_width: 16 -> elements in vector: 4 - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.MUL_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_F, "> 0", IRNode.MUL_VF, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIfAnd = {"AlignVector", "false", "MaxVectorSize", ">= 8"}, applyIfCPUFeatureAnd = {"sse4.1", "true", "avx", "false"}) // Strict alignment not possible. - @IR(failOn = {IRNode.LOAD_VECTOR, IRNode.MUL_V, IRNode.STORE_VECTOR}, + @IR(failOn = {IRNode.LOAD_VECTOR_F, IRNode.MUL_VF, IRNode.STORE_VECTOR}, applyIf = {"AlignVector", "true"}, applyIfCPUFeatureAnd = {"sse4.1", "true", "avx", "false"}) // CPU: avx and avx2 -> vector_width: 32 -> elements in vector: 8 - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.MUL_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_F, "> 0", IRNode.MUL_VF, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIfAnd = {"AlignVector", "false", "MaxVectorSize", ">= 8"}, applyIfCPUFeatureAnd = {"avx", "true", "avx512", "false"}) // Strict alignment not possible. - @IR(failOn = {IRNode.LOAD_VECTOR, IRNode.MUL_V, IRNode.STORE_VECTOR}, + @IR(failOn = {IRNode.LOAD_VECTOR_F, IRNode.MUL_VF, IRNode.STORE_VECTOR}, applyIf = {"AlignVector", "true"}, applyIfCPUFeatureAnd = {"avx", "true", "avx512", "false"}) // CPU: avx512 -> vector_width: 64 -> elements in vector: 16 - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.MUL_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_F, "> 0", IRNode.MUL_VF, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIfAnd = {"AlignVector", "false", "MaxVectorSize", ">= 8"}, applyIfCPUFeature = {"avx512", "true"}) // Strict alignment not possible. - @IR(failOn = {IRNode.LOAD_VECTOR, IRNode.MUL_V, IRNode.STORE_VECTOR}, + @IR(failOn = {IRNode.LOAD_VECTOR_F, IRNode.MUL_VF, IRNode.STORE_VECTOR}, applyIf = {"AlignVector", "true"}, applyIfCPUFeature = {"avx512", "true"}) // CPU: asimd -> vector_width: 32 -> elements in vector: 8 - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.MUL_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_F, "> 0", IRNode.MUL_VF, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIfAnd = {"AlignVector", "false", "MaxVectorSize", ">= 8"}, applyIfCPUFeature = {"asimd", "true"}) // Strict alignment not possible. - @IR(failOn = {IRNode.LOAD_VECTOR, IRNode.MUL_V, IRNode.STORE_VECTOR}, + @IR(failOn = {IRNode.LOAD_VECTOR_F, IRNode.MUL_VF, IRNode.STORE_VECTOR}, applyIf = {"AlignVector", "true"}, applyIfCPUFeature = {"asimd", "true"}) public static void testFloatM1(float[] data) { @@ -8559,19 +8559,19 @@ public static void runFloatP1() { @Test // CPU: sse4.1 -> vector_width: 16 -> elements in vector: 4 - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.MUL_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_F, "> 0", IRNode.MUL_VF, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIfAnd = {"AlignVector", "false", "MaxVectorSize", ">= 8"}, applyIfCPUFeatureAnd = {"sse4.1", "true", "avx", "false"}) // CPU: avx and avx2 -> vector_width: 32 -> elements in vector: 8 - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.MUL_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_F, "> 0", IRNode.MUL_VF, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIfAnd = {"AlignVector", "false", "MaxVectorSize", ">= 8"}, applyIfCPUFeatureAnd = {"avx", "true", "avx512", "false"}) // CPU: avx512 -> vector_width: 64 -> elements in vector: 16 - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.MUL_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_F, "> 0", IRNode.MUL_VF, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIfAnd = {"AlignVector", "false", "MaxVectorSize", ">= 8"}, applyIfCPUFeature = {"avx512", "true"}) // CPU: asimd -> vector_width: 32 -> elements in vector: 8 - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.MUL_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_F, "> 0", IRNode.MUL_VF, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIfAnd = {"AlignVector", "false", "MaxVectorSize", ">= 8"}, applyIfCPUFeature = {"asimd", "true"}) public static void testFloatM2(float[] data) { @@ -8592,22 +8592,22 @@ public static void runFloatM2() { @Test // CPU: sse4.1 -> vector_width: 16 -> elements in vector: 4 // positive byte_offset 8 can lead to cyclic dependency - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.MUL_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_F, "> 0", IRNode.MUL_VF, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIfAnd = {"AlignVector", "false", "MaxVectorSize", ">= 8", "MaxVectorSize", "<= 8"}, applyIfCPUFeatureAnd = {"sse4.1", "true", "avx", "false"}) // CPU: avx and avx2 -> vector_width: 32 -> elements in vector: 8 // positive byte_offset 8 can lead to cyclic dependency - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.MUL_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_F, "> 0", IRNode.MUL_VF, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIfAnd = {"AlignVector", "false", "MaxVectorSize", ">= 8", "MaxVectorSize", "<= 8"}, applyIfCPUFeatureAnd = {"avx", "true", "avx512", "false"}) // CPU: avx512 -> vector_width: 64 -> elements in vector: 16 // positive byte_offset 8 can lead to cyclic dependency - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.MUL_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_F, "> 0", IRNode.MUL_VF, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIfAnd = {"AlignVector", "false", "MaxVectorSize", ">= 8", "MaxVectorSize", "<= 8"}, applyIfCPUFeature = {"avx512", "true"}) // CPU: asimd -> vector_width: 32 -> elements in vector: 8 // positive byte_offset 8 can lead to cyclic dependency - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.MUL_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_F, "> 0", IRNode.MUL_VF, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIfAnd = {"AlignVector", "false", "MaxVectorSize", ">= 8", "MaxVectorSize", "<= 8"}, applyIfCPUFeature = {"asimd", "true"}) public static void testFloatP2(float[] data) { @@ -8627,35 +8627,35 @@ public static void runFloatP2() { @Test // CPU: sse4.1 -> vector_width: 16 -> elements in vector: 4 - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.MUL_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_F, "> 0", IRNode.MUL_VF, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIfAnd = {"AlignVector", "false", "MaxVectorSize", ">= 8"}, applyIfCPUFeatureAnd = {"sse4.1", "true", "avx", "false"}) // Strict alignment not possible. - @IR(failOn = {IRNode.LOAD_VECTOR, IRNode.MUL_V, IRNode.STORE_VECTOR}, + @IR(failOn = {IRNode.LOAD_VECTOR_F, IRNode.MUL_VF, IRNode.STORE_VECTOR}, applyIf = {"AlignVector", "true"}, applyIfCPUFeatureAnd = {"sse4.1", "true", "avx", "false"}) // CPU: avx and avx2 -> vector_width: 32 -> elements in vector: 8 - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.MUL_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_F, "> 0", IRNode.MUL_VF, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIfAnd = {"AlignVector", "false", "MaxVectorSize", ">= 8"}, applyIfCPUFeatureAnd = {"avx", "true", "avx512", "false"}) // Strict alignment not possible. - @IR(failOn = {IRNode.LOAD_VECTOR, IRNode.MUL_V, IRNode.STORE_VECTOR}, + @IR(failOn = {IRNode.LOAD_VECTOR_F, IRNode.MUL_VF, IRNode.STORE_VECTOR}, applyIf = {"AlignVector", "true"}, applyIfCPUFeatureAnd = {"avx", "true", "avx512", "false"}) // CPU: avx512 -> vector_width: 64 -> elements in vector: 16 - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.MUL_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_F, "> 0", IRNode.MUL_VF, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIfAnd = {"AlignVector", "false", "MaxVectorSize", ">= 8"}, applyIfCPUFeature = {"avx512", "true"}) // Strict alignment not possible. - @IR(failOn = {IRNode.LOAD_VECTOR, IRNode.MUL_V, IRNode.STORE_VECTOR}, + @IR(failOn = {IRNode.LOAD_VECTOR_F, IRNode.MUL_VF, IRNode.STORE_VECTOR}, applyIf = {"AlignVector", "true"}, applyIfCPUFeature = {"avx512", "true"}) // CPU: asimd -> vector_width: 32 -> elements in vector: 8 - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.MUL_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_F, "> 0", IRNode.MUL_VF, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIfAnd = {"AlignVector", "false", "MaxVectorSize", ">= 8"}, applyIfCPUFeature = {"asimd", "true"}) // Strict alignment not possible. - @IR(failOn = {IRNode.LOAD_VECTOR, IRNode.MUL_V, IRNode.STORE_VECTOR}, + @IR(failOn = {IRNode.LOAD_VECTOR_F, IRNode.MUL_VF, IRNode.STORE_VECTOR}, applyIf = {"AlignVector", "true"}, applyIfCPUFeature = {"asimd", "true"}) public static void testFloatM3(float[] data) { @@ -8676,22 +8676,22 @@ public static void runFloatM3() { @Test // CPU: sse4.1 -> vector_width: 16 -> elements in vector: 4 // positive byte_offset 12 can lead to cyclic dependency - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.MUL_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_F, "> 0", IRNode.MUL_VF, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIfAnd = {"AlignVector", "false", "MaxVectorSize", ">= 8", "MaxVectorSize", "<= 12"}, applyIfCPUFeatureAnd = {"sse4.1", "true", "avx", "false"}) // CPU: avx and avx2 -> vector_width: 32 -> elements in vector: 8 // positive byte_offset 12 can lead to cyclic dependency - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.MUL_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_F, "> 0", IRNode.MUL_VF, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIfAnd = {"AlignVector", "false", "MaxVectorSize", ">= 8", "MaxVectorSize", "<= 12"}, applyIfCPUFeatureAnd = {"avx", "true", "avx512", "false"}) // CPU: avx512 -> vector_width: 64 -> elements in vector: 16 // positive byte_offset 12 can lead to cyclic dependency - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.MUL_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_F, "> 0", IRNode.MUL_VF, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIfAnd = {"AlignVector", "false", "MaxVectorSize", ">= 8", "MaxVectorSize", "<= 12"}, applyIfCPUFeature = {"avx512", "true"}) // CPU: asimd -> vector_width: 32 -> elements in vector: 8 // positive byte_offset 12 can lead to cyclic dependency - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.MUL_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_F, "> 0", IRNode.MUL_VF, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIfAnd = {"AlignVector", "false", "MaxVectorSize", ">= 8", "MaxVectorSize", "<= 12"}, applyIfCPUFeature = {"asimd", "true"}) public static void testFloatP3(float[] data) { @@ -8711,19 +8711,19 @@ public static void runFloatP3() { @Test // CPU: sse4.1 -> vector_width: 16 -> elements in vector: 4 - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.MUL_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_F, "> 0", IRNode.MUL_VF, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIfAnd = {"AlignVector", "false", "MaxVectorSize", ">= 8"}, applyIfCPUFeatureAnd = {"sse4.1", "true", "avx", "false"}) // CPU: avx and avx2 -> vector_width: 32 -> elements in vector: 8 - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.MUL_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_F, "> 0", IRNode.MUL_VF, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIfAnd = {"AlignVector", "false", "MaxVectorSize", ">= 8"}, applyIfCPUFeatureAnd = {"avx", "true", "avx512", "false"}) // CPU: avx512 -> vector_width: 64 -> elements in vector: 16 - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.MUL_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_F, "> 0", IRNode.MUL_VF, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIfAnd = {"AlignVector", "false", "MaxVectorSize", ">= 8"}, applyIfCPUFeature = {"avx512", "true"}) // CPU: asimd -> vector_width: 32 -> elements in vector: 8 - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.MUL_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_F, "> 0", IRNode.MUL_VF, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIfAnd = {"AlignVector", "false", "MaxVectorSize", ">= 8"}, applyIfCPUFeature = {"asimd", "true"}) public static void testFloatM4(float[] data) { @@ -8743,26 +8743,26 @@ public static void runFloatM4() { @Test // CPU: sse4.1 -> vector_width: 16 -> elements in vector: 4 - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.MUL_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_F, "> 0", IRNode.MUL_VF, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIfAnd = {"AlignVector", "false", "MaxVectorSize", ">= 8"}, applyIfCPUFeatureAnd = {"sse4.1", "true", "avx", "false"}) // Vectorize when strict alignment guaranteed. - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.MUL_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_F, "> 0", IRNode.MUL_VF, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIfAnd = {"AlignVector", "true", "MaxVectorSize", ">= 8"}, applyIfCPUFeatureAnd = {"sse4.1", "true", "avx", "false"}) // CPU: avx and avx2 -> vector_width: 32 -> elements in vector: 8 // positive byte_offset 16 can lead to cyclic dependency - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.MUL_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_F, "> 0", IRNode.MUL_VF, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIfAnd = {"AlignVector", "false", "MaxVectorSize", ">= 8", "MaxVectorSize", "<= 16"}, applyIfCPUFeatureAnd = {"avx", "true", "avx512", "false"}) // CPU: avx512 -> vector_width: 64 -> elements in vector: 16 // positive byte_offset 16 can lead to cyclic dependency - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.MUL_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_F, "> 0", IRNode.MUL_VF, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIfAnd = {"AlignVector", "false", "MaxVectorSize", ">= 8", "MaxVectorSize", "<= 16"}, applyIfCPUFeature = {"avx512", "true"}) // CPU: asimd -> vector_width: 32 -> elements in vector: 8 // positive byte_offset 16 can lead to cyclic dependency - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.MUL_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_F, "> 0", IRNode.MUL_VF, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIfAnd = {"AlignVector", "false", "MaxVectorSize", ">= 8", "MaxVectorSize", "<= 16"}, applyIfCPUFeature = {"asimd", "true"}) public static void testFloatP4(float[] data) { @@ -8782,35 +8782,35 @@ public static void runFloatP4() { @Test // CPU: sse4.1 -> vector_width: 16 -> elements in vector: 4 - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.MUL_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_F, "> 0", IRNode.MUL_VF, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIfAnd = {"AlignVector", "false", "MaxVectorSize", ">= 8"}, applyIfCPUFeatureAnd = {"sse4.1", "true", "avx", "false"}) // Strict alignment not possible. - @IR(failOn = {IRNode.LOAD_VECTOR, IRNode.MUL_V, IRNode.STORE_VECTOR}, + @IR(failOn = {IRNode.LOAD_VECTOR_F, IRNode.MUL_VF, IRNode.STORE_VECTOR}, applyIf = {"AlignVector", "true"}, applyIfCPUFeatureAnd = {"sse4.1", "true", "avx", "false"}) // CPU: avx and avx2 -> vector_width: 32 -> elements in vector: 8 - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.MUL_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_F, "> 0", IRNode.MUL_VF, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIfAnd = {"AlignVector", "false", "MaxVectorSize", ">= 8"}, applyIfCPUFeatureAnd = {"avx", "true", "avx512", "false"}) // Strict alignment not possible. - @IR(failOn = {IRNode.LOAD_VECTOR, IRNode.MUL_V, IRNode.STORE_VECTOR}, + @IR(failOn = {IRNode.LOAD_VECTOR_F, IRNode.MUL_VF, IRNode.STORE_VECTOR}, applyIf = {"AlignVector", "true"}, applyIfCPUFeatureAnd = {"avx", "true", "avx512", "false"}) // CPU: avx512 -> vector_width: 64 -> elements in vector: 16 - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.MUL_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_F, "> 0", IRNode.MUL_VF, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIfAnd = {"AlignVector", "false", "MaxVectorSize", ">= 8"}, applyIfCPUFeature = {"avx512", "true"}) // Strict alignment not possible. - @IR(failOn = {IRNode.LOAD_VECTOR, IRNode.MUL_V, IRNode.STORE_VECTOR}, + @IR(failOn = {IRNode.LOAD_VECTOR_F, IRNode.MUL_VF, IRNode.STORE_VECTOR}, applyIf = {"AlignVector", "true"}, applyIfCPUFeature = {"avx512", "true"}) // CPU: asimd -> vector_width: 32 -> elements in vector: 8 - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.MUL_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_F, "> 0", IRNode.MUL_VF, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIfAnd = {"AlignVector", "false", "MaxVectorSize", ">= 8"}, applyIfCPUFeature = {"asimd", "true"}) // Strict alignment not possible. - @IR(failOn = {IRNode.LOAD_VECTOR, IRNode.MUL_V, IRNode.STORE_VECTOR}, + @IR(failOn = {IRNode.LOAD_VECTOR_F, IRNode.MUL_VF, IRNode.STORE_VECTOR}, applyIf = {"AlignVector", "true"}, applyIfCPUFeature = {"asimd", "true"}) public static void testFloatM7(float[] data) { @@ -8830,22 +8830,22 @@ public static void runFloatM7() { @Test // CPU: sse4.1 -> vector_width: 16 -> elements in vector: 4 - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.MUL_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_F, "> 0", IRNode.MUL_VF, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIfAnd = {"AlignVector", "false", "MaxVectorSize", ">= 8"}, applyIfCPUFeatureAnd = {"sse4.1", "true", "avx", "false"}) // CPU: avx and avx2 -> vector_width: 32 -> elements in vector: 8 // positive byte_offset 28 can lead to cyclic dependency - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.MUL_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_F, "> 0", IRNode.MUL_VF, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIfAnd = {"AlignVector", "false", "MaxVectorSize", ">= 8", "MaxVectorSize", "<= 28"}, applyIfCPUFeatureAnd = {"avx", "true", "avx512", "false"}) // CPU: avx512 -> vector_width: 64 -> elements in vector: 16 // positive byte_offset 28 can lead to cyclic dependency - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.MUL_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_F, "> 0", IRNode.MUL_VF, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIfAnd = {"AlignVector", "false", "MaxVectorSize", ">= 8", "MaxVectorSize", "<= 28"}, applyIfCPUFeature = {"avx512", "true"}) // CPU: asimd -> vector_width: 32 -> elements in vector: 8 // positive byte_offset 28 can lead to cyclic dependency - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.MUL_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_F, "> 0", IRNode.MUL_VF, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIfAnd = {"AlignVector", "false", "MaxVectorSize", ">= 8", "MaxVectorSize", "<= 28"}, applyIfCPUFeature = {"asimd", "true"}) public static void testFloatP7(float[] data) { @@ -8865,19 +8865,19 @@ public static void runFloatP7() { @Test // CPU: sse4.1 -> vector_width: 16 -> elements in vector: 4 - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.MUL_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_F, "> 0", IRNode.MUL_VF, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIfAnd = {"AlignVector", "false", "MaxVectorSize", ">= 8"}, applyIfCPUFeatureAnd = {"sse4.1", "true", "avx", "false"}) // CPU: avx and avx2 -> vector_width: 32 -> elements in vector: 8 - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.MUL_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_F, "> 0", IRNode.MUL_VF, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIfAnd = {"AlignVector", "false", "MaxVectorSize", ">= 8"}, applyIfCPUFeatureAnd = {"avx", "true", "avx512", "false"}) // CPU: avx512 -> vector_width: 64 -> elements in vector: 16 - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.MUL_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_F, "> 0", IRNode.MUL_VF, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIfAnd = {"AlignVector", "false", "MaxVectorSize", ">= 8"}, applyIfCPUFeature = {"avx512", "true"}) // CPU: asimd -> vector_width: 32 -> elements in vector: 8 - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.MUL_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_F, "> 0", IRNode.MUL_VF, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIfAnd = {"AlignVector", "false", "MaxVectorSize", ">= 8"}, applyIfCPUFeature = {"asimd", "true"}) public static void testFloatM8(float[] data) { @@ -8897,32 +8897,32 @@ public static void runFloatM8() { @Test // CPU: sse4.1 -> vector_width: 16 -> elements in vector: 4 - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.MUL_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_F, "> 0", IRNode.MUL_VF, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIfAnd = {"AlignVector", "false", "MaxVectorSize", ">= 8"}, applyIfCPUFeatureAnd = {"sse4.1", "true", "avx", "false"}) // Vectorize when strict alignment guaranteed. - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.MUL_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_F, "> 0", IRNode.MUL_VF, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIfAnd = {"AlignVector", "true", "MaxVectorSize", ">= 8"}, applyIfCPUFeatureAnd = {"sse4.1", "true", "avx", "false"}) // CPU: avx and avx2 -> vector_width: 32 -> elements in vector: 8 - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.MUL_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_F, "> 0", IRNode.MUL_VF, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIfAnd = {"AlignVector", "false", "MaxVectorSize", ">= 8"}, applyIfCPUFeatureAnd = {"avx", "true", "avx512", "false"}) // Vectorize when strict alignment guaranteed. - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.MUL_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_F, "> 0", IRNode.MUL_VF, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIfAnd = {"AlignVector", "true", "MaxVectorSize", ">= 8"}, applyIfCPUFeatureAnd = {"avx", "true", "avx512", "false"}) // CPU: avx512 -> vector_width: 64 -> elements in vector: 16 // positive byte_offset 32 can lead to cyclic dependency - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.MUL_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_F, "> 0", IRNode.MUL_VF, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIfAnd = {"AlignVector", "false", "MaxVectorSize", ">= 8", "MaxVectorSize", "<= 32"}, applyIfCPUFeature = {"avx512", "true"}) // CPU: asimd -> vector_width: 32 -> elements in vector: 8 - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.MUL_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_F, "> 0", IRNode.MUL_VF, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIfAnd = {"AlignVector", "false", "MaxVectorSize", ">= 8"}, applyIfCPUFeature = {"asimd", "true"}) // Vectorize when strict alignment guaranteed. - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.MUL_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_F, "> 0", IRNode.MUL_VF, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIfAnd = {"AlignVector", "true", "MaxVectorSize", ">= 8"}, applyIfCPUFeature = {"asimd", "true"}) public static void testFloatP8(float[] data) { @@ -8942,19 +8942,19 @@ public static void runFloatP8() { @Test // CPU: sse4.1 -> vector_width: 16 -> elements in vector: 4 - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.MUL_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_F, "> 0", IRNode.MUL_VF, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIfAnd = {"AlignVector", "false", "MaxVectorSize", ">= 8"}, applyIfCPUFeatureAnd = {"sse4.1", "true", "avx", "false"}) // CPU: avx and avx2 -> vector_width: 32 -> elements in vector: 8 - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.MUL_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_F, "> 0", IRNode.MUL_VF, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIfAnd = {"AlignVector", "false", "MaxVectorSize", ">= 8"}, applyIfCPUFeatureAnd = {"avx", "true", "avx512", "false"}) // CPU: avx512 -> vector_width: 64 -> elements in vector: 16 - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.MUL_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_F, "> 0", IRNode.MUL_VF, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIfAnd = {"AlignVector", "false", "MaxVectorSize", ">= 8"}, applyIfCPUFeature = {"avx512", "true"}) // CPU: asimd -> vector_width: 32 -> elements in vector: 8 - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.MUL_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_F, "> 0", IRNode.MUL_VF, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIfAnd = {"AlignVector", "false", "MaxVectorSize", ">= 8"}, applyIfCPUFeature = {"asimd", "true"}) public static void testFloatM14(float[] data) { @@ -8974,20 +8974,20 @@ public static void runFloatM14() { @Test // CPU: sse4.1 -> vector_width: 16 -> elements in vector: 4 - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.MUL_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_F, "> 0", IRNode.MUL_VF, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIfAnd = {"AlignVector", "false", "MaxVectorSize", ">= 8"}, applyIfCPUFeatureAnd = {"sse4.1", "true", "avx", "false"}) // CPU: avx and avx2 -> vector_width: 32 -> elements in vector: 8 - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.MUL_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_F, "> 0", IRNode.MUL_VF, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIfAnd = {"AlignVector", "false", "MaxVectorSize", ">= 8"}, applyIfCPUFeatureAnd = {"avx", "true", "avx512", "false"}) // CPU: avx512 -> vector_width: 64 -> elements in vector: 16 // positive byte_offset 56 can lead to cyclic dependency - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.MUL_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_F, "> 0", IRNode.MUL_VF, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIfAnd = {"AlignVector", "false", "MaxVectorSize", ">= 8", "MaxVectorSize", "<= 56"}, applyIfCPUFeature = {"avx512", "true"}) // CPU: asimd -> vector_width: 32 -> elements in vector: 8 - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.MUL_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_F, "> 0", IRNode.MUL_VF, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIfAnd = {"AlignVector", "false", "MaxVectorSize", ">= 8"}, applyIfCPUFeature = {"asimd", "true"}) public static void testFloatP14(float[] data) { @@ -9007,19 +9007,19 @@ public static void runFloatP14() { @Test // CPU: sse4.1 -> vector_width: 16 -> elements in vector: 4 - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.MUL_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_F, "> 0", IRNode.MUL_VF, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIfAnd = {"AlignVector", "false", "MaxVectorSize", ">= 8"}, applyIfCPUFeatureAnd = {"sse4.1", "true", "avx", "false"}) // CPU: avx and avx2 -> vector_width: 32 -> elements in vector: 8 - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.MUL_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_F, "> 0", IRNode.MUL_VF, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIfAnd = {"AlignVector", "false", "MaxVectorSize", ">= 8"}, applyIfCPUFeatureAnd = {"avx", "true", "avx512", "false"}) // CPU: avx512 -> vector_width: 64 -> elements in vector: 16 - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.MUL_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_F, "> 0", IRNode.MUL_VF, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIfAnd = {"AlignVector", "false", "MaxVectorSize", ">= 8"}, applyIfCPUFeature = {"avx512", "true"}) // CPU: asimd -> vector_width: 32 -> elements in vector: 8 - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.MUL_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_F, "> 0", IRNode.MUL_VF, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIfAnd = {"AlignVector", "false", "MaxVectorSize", ">= 8"}, applyIfCPUFeature = {"asimd", "true"}) public static void testFloatM16(float[] data) { @@ -9039,35 +9039,35 @@ public static void runFloatM16() { @Test // CPU: sse4.1 -> vector_width: 16 -> elements in vector: 4 - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.MUL_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_F, "> 0", IRNode.MUL_VF, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIfAnd = {"AlignVector", "false", "MaxVectorSize", ">= 8"}, applyIfCPUFeatureAnd = {"sse4.1", "true", "avx", "false"}) // Vectorize when strict alignment guaranteed. - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.MUL_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_F, "> 0", IRNode.MUL_VF, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIfAnd = {"AlignVector", "true", "MaxVectorSize", ">= 8"}, applyIfCPUFeatureAnd = {"sse4.1", "true", "avx", "false"}) // CPU: avx and avx2 -> vector_width: 32 -> elements in vector: 8 - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.MUL_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_F, "> 0", IRNode.MUL_VF, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIfAnd = {"AlignVector", "false", "MaxVectorSize", ">= 8"}, applyIfCPUFeatureAnd = {"avx", "true", "avx512", "false"}) // Vectorize when strict alignment guaranteed. - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.MUL_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_F, "> 0", IRNode.MUL_VF, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIfAnd = {"AlignVector", "true", "MaxVectorSize", ">= 8"}, applyIfCPUFeatureAnd = {"avx", "true", "avx512", "false"}) // CPU: avx512 -> vector_width: 64 -> elements in vector: 16 - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.MUL_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_F, "> 0", IRNode.MUL_VF, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIfAnd = {"AlignVector", "false", "MaxVectorSize", ">= 8"}, applyIfCPUFeature = {"avx512", "true"}) // Vectorize when strict alignment guaranteed. - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.MUL_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_F, "> 0", IRNode.MUL_VF, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIfAnd = {"AlignVector", "true", "MaxVectorSize", ">= 8"}, applyIfCPUFeature = {"avx512", "true"}) // CPU: asimd -> vector_width: 32 -> elements in vector: 8 - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.MUL_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_F, "> 0", IRNode.MUL_VF, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIfAnd = {"AlignVector", "false", "MaxVectorSize", ">= 8"}, applyIfCPUFeature = {"asimd", "true"}) // Vectorize when strict alignment guaranteed. - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.MUL_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_F, "> 0", IRNode.MUL_VF, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIfAnd = {"AlignVector", "true", "MaxVectorSize", ">= 8"}, applyIfCPUFeature = {"asimd", "true"}) public static void testFloatP16(float[] data) { @@ -9087,19 +9087,19 @@ public static void runFloatP16() { @Test // CPU: sse4.1 -> vector_width: 16 -> elements in vector: 4 - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.MUL_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_F, "> 0", IRNode.MUL_VF, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIfAnd = {"AlignVector", "false", "MaxVectorSize", ">= 8"}, applyIfCPUFeatureAnd = {"sse4.1", "true", "avx", "false"}) // CPU: avx and avx2 -> vector_width: 32 -> elements in vector: 8 - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.MUL_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_F, "> 0", IRNode.MUL_VF, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIfAnd = {"AlignVector", "false", "MaxVectorSize", ">= 8"}, applyIfCPUFeatureAnd = {"avx", "true", "avx512", "false"}) // CPU: avx512 -> vector_width: 64 -> elements in vector: 16 - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.MUL_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_F, "> 0", IRNode.MUL_VF, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIfAnd = {"AlignVector", "false", "MaxVectorSize", ">= 8"}, applyIfCPUFeature = {"avx512", "true"}) // CPU: asimd -> vector_width: 32 -> elements in vector: 8 - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.MUL_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_F, "> 0", IRNode.MUL_VF, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIfAnd = {"AlignVector", "false", "MaxVectorSize", ">= 8"}, applyIfCPUFeature = {"asimd", "true"}) public static void testFloatM18(float[] data) { @@ -9119,19 +9119,19 @@ public static void runFloatM18() { @Test // CPU: sse4.1 -> vector_width: 16 -> elements in vector: 4 - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.MUL_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_F, "> 0", IRNode.MUL_VF, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIfAnd = {"AlignVector", "false", "MaxVectorSize", ">= 8"}, applyIfCPUFeatureAnd = {"sse4.1", "true", "avx", "false"}) // CPU: avx and avx2 -> vector_width: 32 -> elements in vector: 8 - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.MUL_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_F, "> 0", IRNode.MUL_VF, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIfAnd = {"AlignVector", "false", "MaxVectorSize", ">= 8"}, applyIfCPUFeatureAnd = {"avx", "true", "avx512", "false"}) // CPU: avx512 -> vector_width: 64 -> elements in vector: 16 - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.MUL_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_F, "> 0", IRNode.MUL_VF, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIfAnd = {"AlignVector", "false", "MaxVectorSize", ">= 8"}, applyIfCPUFeature = {"avx512", "true"}) // CPU: asimd -> vector_width: 32 -> elements in vector: 8 - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.MUL_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_F, "> 0", IRNode.MUL_VF, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIfAnd = {"AlignVector", "false", "MaxVectorSize", ">= 8"}, applyIfCPUFeature = {"asimd", "true"}) public static void testFloatP18(float[] data) { @@ -9151,19 +9151,19 @@ public static void runFloatP18() { @Test // CPU: sse4.1 -> vector_width: 16 -> elements in vector: 4 - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.MUL_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_F, "> 0", IRNode.MUL_VF, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIfAnd = {"AlignVector", "false", "MaxVectorSize", ">= 8"}, applyIfCPUFeatureAnd = {"sse4.1", "true", "avx", "false"}) // CPU: avx and avx2 -> vector_width: 32 -> elements in vector: 8 - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.MUL_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_F, "> 0", IRNode.MUL_VF, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIfAnd = {"AlignVector", "false", "MaxVectorSize", ">= 8"}, applyIfCPUFeatureAnd = {"avx", "true", "avx512", "false"}) // CPU: avx512 -> vector_width: 64 -> elements in vector: 16 - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.MUL_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_F, "> 0", IRNode.MUL_VF, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIfAnd = {"AlignVector", "false", "MaxVectorSize", ">= 8"}, applyIfCPUFeature = {"avx512", "true"}) // CPU: asimd -> vector_width: 32 -> elements in vector: 8 - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.MUL_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_F, "> 0", IRNode.MUL_VF, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIfAnd = {"AlignVector", "false", "MaxVectorSize", ">= 8"}, applyIfCPUFeature = {"asimd", "true"}) public static void testFloatM20(float[] data) { @@ -9183,23 +9183,23 @@ public static void runFloatM20() { @Test // CPU: sse4.1 -> vector_width: 16 -> elements in vector: 4 - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.MUL_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_F, "> 0", IRNode.MUL_VF, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIfAnd = {"AlignVector", "false", "MaxVectorSize", ">= 8"}, applyIfCPUFeatureAnd = {"sse4.1", "true", "avx", "false"}) // Vectorize when strict alignment guaranteed. - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.MUL_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_F, "> 0", IRNode.MUL_VF, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIfAnd = {"AlignVector", "true", "MaxVectorSize", ">= 8"}, applyIfCPUFeatureAnd = {"sse4.1", "true", "avx", "false"}) // CPU: avx and avx2 -> vector_width: 32 -> elements in vector: 8 - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.MUL_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_F, "> 0", IRNode.MUL_VF, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIfAnd = {"AlignVector", "false", "MaxVectorSize", ">= 8"}, applyIfCPUFeatureAnd = {"avx", "true", "avx512", "false"}) // CPU: avx512 -> vector_width: 64 -> elements in vector: 16 - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.MUL_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_F, "> 0", IRNode.MUL_VF, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIfAnd = {"AlignVector", "false", "MaxVectorSize", ">= 8"}, applyIfCPUFeature = {"avx512", "true"}) // CPU: asimd -> vector_width: 32 -> elements in vector: 8 - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.MUL_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_F, "> 0", IRNode.MUL_VF, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIfAnd = {"AlignVector", "false", "MaxVectorSize", ">= 8"}, applyIfCPUFeature = {"asimd", "true"}) public static void testFloatP20(float[] data) { @@ -9219,35 +9219,35 @@ public static void runFloatP20() { @Test // CPU: sse4.1 -> vector_width: 16 -> elements in vector: 4 - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.MUL_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_F, "> 0", IRNode.MUL_VF, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIfAnd = {"AlignVector", "false", "MaxVectorSize", ">= 8"}, applyIfCPUFeatureAnd = {"sse4.1", "true", "avx", "false"}) // Strict alignment not possible. - @IR(failOn = {IRNode.LOAD_VECTOR, IRNode.MUL_V, IRNode.STORE_VECTOR}, + @IR(failOn = {IRNode.LOAD_VECTOR_F, IRNode.MUL_VF, IRNode.STORE_VECTOR}, applyIf = {"AlignVector", "true"}, applyIfCPUFeatureAnd = {"sse4.1", "true", "avx", "false"}) // CPU: avx and avx2 -> vector_width: 32 -> elements in vector: 8 - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.MUL_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_F, "> 0", IRNode.MUL_VF, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIfAnd = {"AlignVector", "false", "MaxVectorSize", ">= 8"}, applyIfCPUFeatureAnd = {"avx", "true", "avx512", "false"}) // Strict alignment not possible. - @IR(failOn = {IRNode.LOAD_VECTOR, IRNode.MUL_V, IRNode.STORE_VECTOR}, + @IR(failOn = {IRNode.LOAD_VECTOR_F, IRNode.MUL_VF, IRNode.STORE_VECTOR}, applyIf = {"AlignVector", "true"}, applyIfCPUFeatureAnd = {"avx", "true", "avx512", "false"}) // CPU: avx512 -> vector_width: 64 -> elements in vector: 16 - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.MUL_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_F, "> 0", IRNode.MUL_VF, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIfAnd = {"AlignVector", "false", "MaxVectorSize", ">= 8"}, applyIfCPUFeature = {"avx512", "true"}) // Strict alignment not possible. - @IR(failOn = {IRNode.LOAD_VECTOR, IRNode.MUL_V, IRNode.STORE_VECTOR}, + @IR(failOn = {IRNode.LOAD_VECTOR_F, IRNode.MUL_VF, IRNode.STORE_VECTOR}, applyIf = {"AlignVector", "true"}, applyIfCPUFeature = {"avx512", "true"}) // CPU: asimd -> vector_width: 32 -> elements in vector: 8 - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.MUL_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_F, "> 0", IRNode.MUL_VF, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIfAnd = {"AlignVector", "false", "MaxVectorSize", ">= 8"}, applyIfCPUFeature = {"asimd", "true"}) // Strict alignment not possible. - @IR(failOn = {IRNode.LOAD_VECTOR, IRNode.MUL_V, IRNode.STORE_VECTOR}, + @IR(failOn = {IRNode.LOAD_VECTOR_F, IRNode.MUL_VF, IRNode.STORE_VECTOR}, applyIf = {"AlignVector", "true"}, applyIfCPUFeature = {"asimd", "true"}) public static void testFloatM31(float[] data) { @@ -9267,19 +9267,19 @@ public static void runFloatM31() { @Test // CPU: sse4.1 -> vector_width: 16 -> elements in vector: 4 - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.MUL_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_F, "> 0", IRNode.MUL_VF, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIfAnd = {"AlignVector", "false", "MaxVectorSize", ">= 8"}, applyIfCPUFeatureAnd = {"sse4.1", "true", "avx", "false"}) // CPU: avx and avx2 -> vector_width: 32 -> elements in vector: 8 - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.MUL_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_F, "> 0", IRNode.MUL_VF, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIfAnd = {"AlignVector", "false", "MaxVectorSize", ">= 8"}, applyIfCPUFeatureAnd = {"avx", "true", "avx512", "false"}) // CPU: avx512 -> vector_width: 64 -> elements in vector: 16 - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.MUL_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_F, "> 0", IRNode.MUL_VF, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIfAnd = {"AlignVector", "false", "MaxVectorSize", ">= 8"}, applyIfCPUFeature = {"avx512", "true"}) // CPU: asimd -> vector_width: 32 -> elements in vector: 8 - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.MUL_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_F, "> 0", IRNode.MUL_VF, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIfAnd = {"AlignVector", "false", "MaxVectorSize", ">= 8"}, applyIfCPUFeature = {"asimd", "true"}) public static void testFloatP31(float[] data) { @@ -9299,19 +9299,19 @@ public static void runFloatP31() { @Test // CPU: sse4.1 -> vector_width: 16 -> elements in vector: 4 - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.MUL_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_F, "> 0", IRNode.MUL_VF, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIfAnd = {"AlignVector", "false", "MaxVectorSize", ">= 8"}, applyIfCPUFeatureAnd = {"sse4.1", "true", "avx", "false"}) // CPU: avx and avx2 -> vector_width: 32 -> elements in vector: 8 - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.MUL_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_F, "> 0", IRNode.MUL_VF, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIfAnd = {"AlignVector", "false", "MaxVectorSize", ">= 8"}, applyIfCPUFeatureAnd = {"avx", "true", "avx512", "false"}) // CPU: avx512 -> vector_width: 64 -> elements in vector: 16 - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.MUL_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_F, "> 0", IRNode.MUL_VF, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIfAnd = {"AlignVector", "false", "MaxVectorSize", ">= 8"}, applyIfCPUFeature = {"avx512", "true"}) // CPU: asimd -> vector_width: 32 -> elements in vector: 8 - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.MUL_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_F, "> 0", IRNode.MUL_VF, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIfAnd = {"AlignVector", "false", "MaxVectorSize", ">= 8"}, applyIfCPUFeature = {"asimd", "true"}) public static void testFloatM32(float[] data) { @@ -9331,35 +9331,35 @@ public static void runFloatM32() { @Test // CPU: sse4.1 -> vector_width: 16 -> elements in vector: 4 - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.MUL_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_F, "> 0", IRNode.MUL_VF, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIfAnd = {"AlignVector", "false", "MaxVectorSize", ">= 8"}, applyIfCPUFeatureAnd = {"sse4.1", "true", "avx", "false"}) // Vectorize when strict alignment guaranteed. - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.MUL_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_F, "> 0", IRNode.MUL_VF, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIfAnd = {"AlignVector", "true", "MaxVectorSize", ">= 8"}, applyIfCPUFeatureAnd = {"sse4.1", "true", "avx", "false"}) // CPU: avx and avx2 -> vector_width: 32 -> elements in vector: 8 - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.MUL_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_F, "> 0", IRNode.MUL_VF, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIfAnd = {"AlignVector", "false", "MaxVectorSize", ">= 8"}, applyIfCPUFeatureAnd = {"avx", "true", "avx512", "false"}) // Vectorize when strict alignment guaranteed. - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.MUL_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_F, "> 0", IRNode.MUL_VF, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIfAnd = {"AlignVector", "true", "MaxVectorSize", ">= 8"}, applyIfCPUFeatureAnd = {"avx", "true", "avx512", "false"}) // CPU: avx512 -> vector_width: 64 -> elements in vector: 16 - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.MUL_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_F, "> 0", IRNode.MUL_VF, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIfAnd = {"AlignVector", "false", "MaxVectorSize", ">= 8"}, applyIfCPUFeature = {"avx512", "true"}) // Vectorize when strict alignment guaranteed. - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.MUL_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_F, "> 0", IRNode.MUL_VF, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIfAnd = {"AlignVector", "true", "MaxVectorSize", ">= 8"}, applyIfCPUFeature = {"avx512", "true"}) // CPU: asimd -> vector_width: 32 -> elements in vector: 8 - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.MUL_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_F, "> 0", IRNode.MUL_VF, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIfAnd = {"AlignVector", "false", "MaxVectorSize", ">= 8"}, applyIfCPUFeature = {"asimd", "true"}) // Vectorize when strict alignment guaranteed. - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.MUL_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_F, "> 0", IRNode.MUL_VF, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIfAnd = {"AlignVector", "true", "MaxVectorSize", ">= 8"}, applyIfCPUFeature = {"asimd", "true"}) public static void testFloatP32(float[] data) { @@ -9379,35 +9379,35 @@ public static void runFloatP32() { @Test // CPU: sse4.1 -> vector_width: 16 -> elements in vector: 4 - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.MUL_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_F, "> 0", IRNode.MUL_VF, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIfAnd = {"AlignVector", "false", "MaxVectorSize", ">= 8"}, applyIfCPUFeatureAnd = {"sse4.1", "true", "avx", "false"}) // Strict alignment not possible. - @IR(failOn = {IRNode.LOAD_VECTOR, IRNode.MUL_V, IRNode.STORE_VECTOR}, + @IR(failOn = {IRNode.LOAD_VECTOR_F, IRNode.MUL_VF, IRNode.STORE_VECTOR}, applyIf = {"AlignVector", "true"}, applyIfCPUFeatureAnd = {"sse4.1", "true", "avx", "false"}) // CPU: avx and avx2 -> vector_width: 32 -> elements in vector: 8 - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.MUL_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_F, "> 0", IRNode.MUL_VF, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIfAnd = {"AlignVector", "false", "MaxVectorSize", ">= 8"}, applyIfCPUFeatureAnd = {"avx", "true", "avx512", "false"}) // Strict alignment not possible. - @IR(failOn = {IRNode.LOAD_VECTOR, IRNode.MUL_V, IRNode.STORE_VECTOR}, + @IR(failOn = {IRNode.LOAD_VECTOR_F, IRNode.MUL_VF, IRNode.STORE_VECTOR}, applyIf = {"AlignVector", "true"}, applyIfCPUFeatureAnd = {"avx", "true", "avx512", "false"}) // CPU: avx512 -> vector_width: 64 -> elements in vector: 16 - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.MUL_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_F, "> 0", IRNode.MUL_VF, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIfAnd = {"AlignVector", "false", "MaxVectorSize", ">= 8"}, applyIfCPUFeature = {"avx512", "true"}) // Strict alignment not possible. - @IR(failOn = {IRNode.LOAD_VECTOR, IRNode.MUL_V, IRNode.STORE_VECTOR}, + @IR(failOn = {IRNode.LOAD_VECTOR_F, IRNode.MUL_VF, IRNode.STORE_VECTOR}, applyIf = {"AlignVector", "true"}, applyIfCPUFeature = {"avx512", "true"}) // CPU: asimd -> vector_width: 32 -> elements in vector: 8 - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.MUL_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_F, "> 0", IRNode.MUL_VF, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIfAnd = {"AlignVector", "false", "MaxVectorSize", ">= 8"}, applyIfCPUFeature = {"asimd", "true"}) // Strict alignment not possible. - @IR(failOn = {IRNode.LOAD_VECTOR, IRNode.MUL_V, IRNode.STORE_VECTOR}, + @IR(failOn = {IRNode.LOAD_VECTOR_F, IRNode.MUL_VF, IRNode.STORE_VECTOR}, applyIf = {"AlignVector", "true"}, applyIfCPUFeature = {"asimd", "true"}) public static void testFloatM63(float[] data) { @@ -9427,19 +9427,19 @@ public static void runFloatM63() { @Test // CPU: sse4.1 -> vector_width: 16 -> elements in vector: 4 - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.MUL_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_F, "> 0", IRNode.MUL_VF, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIfAnd = {"AlignVector", "false", "MaxVectorSize", ">= 8"}, applyIfCPUFeatureAnd = {"sse4.1", "true", "avx", "false"}) // CPU: avx and avx2 -> vector_width: 32 -> elements in vector: 8 - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.MUL_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_F, "> 0", IRNode.MUL_VF, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIfAnd = {"AlignVector", "false", "MaxVectorSize", ">= 8"}, applyIfCPUFeatureAnd = {"avx", "true", "avx512", "false"}) // CPU: avx512 -> vector_width: 64 -> elements in vector: 16 - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.MUL_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_F, "> 0", IRNode.MUL_VF, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIfAnd = {"AlignVector", "false", "MaxVectorSize", ">= 8"}, applyIfCPUFeature = {"avx512", "true"}) // CPU: asimd -> vector_width: 32 -> elements in vector: 8 - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.MUL_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_F, "> 0", IRNode.MUL_VF, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIfAnd = {"AlignVector", "false", "MaxVectorSize", ">= 8"}, applyIfCPUFeature = {"asimd", "true"}) public static void testFloatP63(float[] data) { @@ -9459,19 +9459,19 @@ public static void runFloatP63() { @Test // CPU: sse4.1 -> vector_width: 16 -> elements in vector: 4 - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.MUL_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_F, "> 0", IRNode.MUL_VF, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIfAnd = {"AlignVector", "false", "MaxVectorSize", ">= 8"}, applyIfCPUFeatureAnd = {"sse4.1", "true", "avx", "false"}) // CPU: avx and avx2 -> vector_width: 32 -> elements in vector: 8 - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.MUL_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_F, "> 0", IRNode.MUL_VF, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIfAnd = {"AlignVector", "false", "MaxVectorSize", ">= 8"}, applyIfCPUFeatureAnd = {"avx", "true", "avx512", "false"}) // CPU: avx512 -> vector_width: 64 -> elements in vector: 16 - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.MUL_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_F, "> 0", IRNode.MUL_VF, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIfAnd = {"AlignVector", "false", "MaxVectorSize", ">= 8"}, applyIfCPUFeature = {"avx512", "true"}) // CPU: asimd -> vector_width: 32 -> elements in vector: 8 - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.MUL_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_F, "> 0", IRNode.MUL_VF, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIfAnd = {"AlignVector", "false", "MaxVectorSize", ">= 8"}, applyIfCPUFeature = {"asimd", "true"}) public static void testFloatM64(float[] data) { @@ -9491,35 +9491,35 @@ public static void runFloatM64() { @Test // CPU: sse4.1 -> vector_width: 16 -> elements in vector: 4 - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.MUL_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_F, "> 0", IRNode.MUL_VF, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIfAnd = {"AlignVector", "false", "MaxVectorSize", ">= 8"}, applyIfCPUFeatureAnd = {"sse4.1", "true", "avx", "false"}) // Vectorize when strict alignment guaranteed. - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.MUL_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_F, "> 0", IRNode.MUL_VF, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIfAnd = {"AlignVector", "true", "MaxVectorSize", ">= 8"}, applyIfCPUFeatureAnd = {"sse4.1", "true", "avx", "false"}) // CPU: avx and avx2 -> vector_width: 32 -> elements in vector: 8 - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.MUL_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_F, "> 0", IRNode.MUL_VF, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIfAnd = {"AlignVector", "false", "MaxVectorSize", ">= 8"}, applyIfCPUFeatureAnd = {"avx", "true", "avx512", "false"}) // Vectorize when strict alignment guaranteed. - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.MUL_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_F, "> 0", IRNode.MUL_VF, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIfAnd = {"AlignVector", "true", "MaxVectorSize", ">= 8"}, applyIfCPUFeatureAnd = {"avx", "true", "avx512", "false"}) // CPU: avx512 -> vector_width: 64 -> elements in vector: 16 - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.MUL_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_F, "> 0", IRNode.MUL_VF, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIfAnd = {"AlignVector", "false", "MaxVectorSize", ">= 8"}, applyIfCPUFeature = {"avx512", "true"}) // Vectorize when strict alignment guaranteed. - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.MUL_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_F, "> 0", IRNode.MUL_VF, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIfAnd = {"AlignVector", "true", "MaxVectorSize", ">= 8"}, applyIfCPUFeature = {"avx512", "true"}) // CPU: asimd -> vector_width: 32 -> elements in vector: 8 - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.MUL_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_F, "> 0", IRNode.MUL_VF, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIfAnd = {"AlignVector", "false", "MaxVectorSize", ">= 8"}, applyIfCPUFeature = {"asimd", "true"}) // Vectorize when strict alignment guaranteed. - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.MUL_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_F, "> 0", IRNode.MUL_VF, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIfAnd = {"AlignVector", "true", "MaxVectorSize", ">= 8"}, applyIfCPUFeature = {"asimd", "true"}) public static void testFloatP64(float[] data) { @@ -9539,35 +9539,35 @@ public static void runFloatP64() { @Test // CPU: sse4.1 -> vector_width: 16 -> elements in vector: 4 - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.MUL_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_F, "> 0", IRNode.MUL_VF, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIfAnd = {"AlignVector", "false", "MaxVectorSize", ">= 8"}, applyIfCPUFeatureAnd = {"sse4.1", "true", "avx", "false"}) // Strict alignment not possible. - @IR(failOn = {IRNode.LOAD_VECTOR, IRNode.MUL_V, IRNode.STORE_VECTOR}, + @IR(failOn = {IRNode.LOAD_VECTOR_F, IRNode.MUL_VF, IRNode.STORE_VECTOR}, applyIf = {"AlignVector", "true"}, applyIfCPUFeatureAnd = {"sse4.1", "true", "avx", "false"}) // CPU: avx and avx2 -> vector_width: 32 -> elements in vector: 8 - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.MUL_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_F, "> 0", IRNode.MUL_VF, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIfAnd = {"AlignVector", "false", "MaxVectorSize", ">= 8"}, applyIfCPUFeatureAnd = {"avx", "true", "avx512", "false"}) // Strict alignment not possible. - @IR(failOn = {IRNode.LOAD_VECTOR, IRNode.MUL_V, IRNode.STORE_VECTOR}, + @IR(failOn = {IRNode.LOAD_VECTOR_F, IRNode.MUL_VF, IRNode.STORE_VECTOR}, applyIf = {"AlignVector", "true"}, applyIfCPUFeatureAnd = {"avx", "true", "avx512", "false"}) // CPU: avx512 -> vector_width: 64 -> elements in vector: 16 - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.MUL_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_F, "> 0", IRNode.MUL_VF, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIfAnd = {"AlignVector", "false", "MaxVectorSize", ">= 8"}, applyIfCPUFeature = {"avx512", "true"}) // Strict alignment not possible. - @IR(failOn = {IRNode.LOAD_VECTOR, IRNode.MUL_V, IRNode.STORE_VECTOR}, + @IR(failOn = {IRNode.LOAD_VECTOR_F, IRNode.MUL_VF, IRNode.STORE_VECTOR}, applyIf = {"AlignVector", "true"}, applyIfCPUFeature = {"avx512", "true"}) // CPU: asimd -> vector_width: 32 -> elements in vector: 8 - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.MUL_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_F, "> 0", IRNode.MUL_VF, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIfAnd = {"AlignVector", "false", "MaxVectorSize", ">= 8"}, applyIfCPUFeature = {"asimd", "true"}) // Strict alignment not possible. - @IR(failOn = {IRNode.LOAD_VECTOR, IRNode.MUL_V, IRNode.STORE_VECTOR}, + @IR(failOn = {IRNode.LOAD_VECTOR_F, IRNode.MUL_VF, IRNode.STORE_VECTOR}, applyIf = {"AlignVector", "true"}, applyIfCPUFeature = {"asimd", "true"}) public static void testFloatM65(float[] data) { @@ -9587,19 +9587,19 @@ public static void runFloatM65() { @Test // CPU: sse4.1 -> vector_width: 16 -> elements in vector: 4 - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.MUL_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_F, "> 0", IRNode.MUL_VF, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIfAnd = {"AlignVector", "false", "MaxVectorSize", ">= 8"}, applyIfCPUFeatureAnd = {"sse4.1", "true", "avx", "false"}) // CPU: avx and avx2 -> vector_width: 32 -> elements in vector: 8 - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.MUL_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_F, "> 0", IRNode.MUL_VF, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIfAnd = {"AlignVector", "false", "MaxVectorSize", ">= 8"}, applyIfCPUFeatureAnd = {"avx", "true", "avx512", "false"}) // CPU: avx512 -> vector_width: 64 -> elements in vector: 16 - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.MUL_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_F, "> 0", IRNode.MUL_VF, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIfAnd = {"AlignVector", "false", "MaxVectorSize", ">= 8"}, applyIfCPUFeature = {"avx512", "true"}) // CPU: asimd -> vector_width: 32 -> elements in vector: 8 - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.MUL_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_F, "> 0", IRNode.MUL_VF, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIfAnd = {"AlignVector", "false", "MaxVectorSize", ">= 8"}, applyIfCPUFeature = {"asimd", "true"}) public static void testFloatP65(float[] data) { @@ -9619,19 +9619,19 @@ public static void runFloatP65() { @Test // CPU: sse4.1 -> vector_width: 16 -> elements in vector: 4 - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.MUL_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_F, "> 0", IRNode.MUL_VF, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIfAnd = {"AlignVector", "false", "MaxVectorSize", ">= 8"}, applyIfCPUFeatureAnd = {"sse4.1", "true", "avx", "false"}) // CPU: avx and avx2 -> vector_width: 32 -> elements in vector: 8 - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.MUL_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_F, "> 0", IRNode.MUL_VF, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIfAnd = {"AlignVector", "false", "MaxVectorSize", ">= 8"}, applyIfCPUFeatureAnd = {"avx", "true", "avx512", "false"}) // CPU: avx512 -> vector_width: 64 -> elements in vector: 16 - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.MUL_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_F, "> 0", IRNode.MUL_VF, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIfAnd = {"AlignVector", "false", "MaxVectorSize", ">= 8"}, applyIfCPUFeature = {"avx512", "true"}) // CPU: asimd -> vector_width: 32 -> elements in vector: 8 - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.MUL_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_F, "> 0", IRNode.MUL_VF, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIfAnd = {"AlignVector", "false", "MaxVectorSize", ">= 8"}, applyIfCPUFeature = {"asimd", "true"}) public static void testFloatM128(float[] data) { @@ -9651,35 +9651,35 @@ public static void runFloatM128() { @Test // CPU: sse4.1 -> vector_width: 16 -> elements in vector: 4 - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.MUL_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_F, "> 0", IRNode.MUL_VF, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIfAnd = {"AlignVector", "false", "MaxVectorSize", ">= 8"}, applyIfCPUFeatureAnd = {"sse4.1", "true", "avx", "false"}) // Vectorize when strict alignment guaranteed. - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.MUL_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_F, "> 0", IRNode.MUL_VF, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIfAnd = {"AlignVector", "true", "MaxVectorSize", ">= 8"}, applyIfCPUFeatureAnd = {"sse4.1", "true", "avx", "false"}) // CPU: avx and avx2 -> vector_width: 32 -> elements in vector: 8 - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.MUL_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_F, "> 0", IRNode.MUL_VF, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIfAnd = {"AlignVector", "false", "MaxVectorSize", ">= 8"}, applyIfCPUFeatureAnd = {"avx", "true", "avx512", "false"}) // Vectorize when strict alignment guaranteed. - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.MUL_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_F, "> 0", IRNode.MUL_VF, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIfAnd = {"AlignVector", "true", "MaxVectorSize", ">= 8"}, applyIfCPUFeatureAnd = {"avx", "true", "avx512", "false"}) // CPU: avx512 -> vector_width: 64 -> elements in vector: 16 - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.MUL_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_F, "> 0", IRNode.MUL_VF, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIfAnd = {"AlignVector", "false", "MaxVectorSize", ">= 8"}, applyIfCPUFeature = {"avx512", "true"}) // Vectorize when strict alignment guaranteed. - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.MUL_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_F, "> 0", IRNode.MUL_VF, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIfAnd = {"AlignVector", "true", "MaxVectorSize", ">= 8"}, applyIfCPUFeature = {"avx512", "true"}) // CPU: asimd -> vector_width: 32 -> elements in vector: 8 - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.MUL_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_F, "> 0", IRNode.MUL_VF, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIfAnd = {"AlignVector", "false", "MaxVectorSize", ">= 8"}, applyIfCPUFeature = {"asimd", "true"}) // Vectorize when strict alignment guaranteed. - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.MUL_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_F, "> 0", IRNode.MUL_VF, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIfAnd = {"AlignVector", "true", "MaxVectorSize", ">= 8"}, applyIfCPUFeature = {"asimd", "true"}) public static void testFloatP128(float[] data) { @@ -9699,35 +9699,35 @@ public static void runFloatP128() { @Test // CPU: sse4.1 -> vector_width: 16 -> elements in vector: 4 - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.MUL_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_F, "> 0", IRNode.MUL_VF, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIfAnd = {"AlignVector", "false", "MaxVectorSize", ">= 8"}, applyIfCPUFeatureAnd = {"sse4.1", "true", "avx", "false"}) // Strict alignment not possible. - @IR(failOn = {IRNode.LOAD_VECTOR, IRNode.MUL_V, IRNode.STORE_VECTOR}, + @IR(failOn = {IRNode.LOAD_VECTOR_F, IRNode.MUL_VF, IRNode.STORE_VECTOR}, applyIf = {"AlignVector", "true"}, applyIfCPUFeatureAnd = {"sse4.1", "true", "avx", "false"}) // CPU: avx and avx2 -> vector_width: 32 -> elements in vector: 8 - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.MUL_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_F, "> 0", IRNode.MUL_VF, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIfAnd = {"AlignVector", "false", "MaxVectorSize", ">= 8"}, applyIfCPUFeatureAnd = {"avx", "true", "avx512", "false"}) // Strict alignment not possible. - @IR(failOn = {IRNode.LOAD_VECTOR, IRNode.MUL_V, IRNode.STORE_VECTOR}, + @IR(failOn = {IRNode.LOAD_VECTOR_F, IRNode.MUL_VF, IRNode.STORE_VECTOR}, applyIf = {"AlignVector", "true"}, applyIfCPUFeatureAnd = {"avx", "true", "avx512", "false"}) // CPU: avx512 -> vector_width: 64 -> elements in vector: 16 - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.MUL_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_F, "> 0", IRNode.MUL_VF, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIfAnd = {"AlignVector", "false", "MaxVectorSize", ">= 8"}, applyIfCPUFeature = {"avx512", "true"}) // Strict alignment not possible. - @IR(failOn = {IRNode.LOAD_VECTOR, IRNode.MUL_V, IRNode.STORE_VECTOR}, + @IR(failOn = {IRNode.LOAD_VECTOR_F, IRNode.MUL_VF, IRNode.STORE_VECTOR}, applyIf = {"AlignVector", "true"}, applyIfCPUFeature = {"avx512", "true"}) // CPU: asimd -> vector_width: 32 -> elements in vector: 8 - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.MUL_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_F, "> 0", IRNode.MUL_VF, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIfAnd = {"AlignVector", "false", "MaxVectorSize", ">= 8"}, applyIfCPUFeature = {"asimd", "true"}) // Strict alignment not possible. - @IR(failOn = {IRNode.LOAD_VECTOR, IRNode.MUL_V, IRNode.STORE_VECTOR}, + @IR(failOn = {IRNode.LOAD_VECTOR_F, IRNode.MUL_VF, IRNode.STORE_VECTOR}, applyIf = {"AlignVector", "true"}, applyIfCPUFeature = {"asimd", "true"}) public static void testFloatM129(float[] data) { @@ -9747,19 +9747,19 @@ public static void runFloatM129() { @Test // CPU: sse4.1 -> vector_width: 16 -> elements in vector: 4 - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.MUL_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_F, "> 0", IRNode.MUL_VF, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIfAnd = {"AlignVector", "false", "MaxVectorSize", ">= 8"}, applyIfCPUFeatureAnd = {"sse4.1", "true", "avx", "false"}) // CPU: avx and avx2 -> vector_width: 32 -> elements in vector: 8 - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.MUL_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_F, "> 0", IRNode.MUL_VF, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIfAnd = {"AlignVector", "false", "MaxVectorSize", ">= 8"}, applyIfCPUFeatureAnd = {"avx", "true", "avx512", "false"}) // CPU: avx512 -> vector_width: 64 -> elements in vector: 16 - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.MUL_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_F, "> 0", IRNode.MUL_VF, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIfAnd = {"AlignVector", "false", "MaxVectorSize", ">= 8"}, applyIfCPUFeature = {"avx512", "true"}) // CPU: asimd -> vector_width: 32 -> elements in vector: 8 - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.MUL_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_F, "> 0", IRNode.MUL_VF, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIfAnd = {"AlignVector", "false", "MaxVectorSize", ">= 8"}, applyIfCPUFeature = {"asimd", "true"}) public static void testFloatP129(float[] data) { @@ -9779,19 +9779,19 @@ public static void runFloatP129() { @Test // CPU: sse4.1 -> vector_width: 16 -> elements in vector: 4 - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.MUL_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_F, "> 0", IRNode.MUL_VF, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIfAnd = {"AlignVector", "false", "MaxVectorSize", ">= 8"}, applyIfCPUFeatureAnd = {"sse4.1", "true", "avx", "false"}) // CPU: avx and avx2 -> vector_width: 32 -> elements in vector: 8 - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.MUL_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_F, "> 0", IRNode.MUL_VF, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIfAnd = {"AlignVector", "false", "MaxVectorSize", ">= 8"}, applyIfCPUFeatureAnd = {"avx", "true", "avx512", "false"}) // CPU: avx512 -> vector_width: 64 -> elements in vector: 16 - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.MUL_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_F, "> 0", IRNode.MUL_VF, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIfAnd = {"AlignVector", "false", "MaxVectorSize", ">= 8"}, applyIfCPUFeature = {"avx512", "true"}) // CPU: asimd -> vector_width: 32 -> elements in vector: 8 - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.MUL_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_F, "> 0", IRNode.MUL_VF, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIfAnd = {"AlignVector", "false", "MaxVectorSize", ">= 8"}, applyIfCPUFeature = {"asimd", "true"}) public static void testFloatM192(float[] data) { @@ -9811,35 +9811,35 @@ public static void runFloatM192() { @Test // CPU: sse4.1 -> vector_width: 16 -> elements in vector: 4 - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.MUL_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_F, "> 0", IRNode.MUL_VF, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIfAnd = {"AlignVector", "false", "MaxVectorSize", ">= 8"}, applyIfCPUFeatureAnd = {"sse4.1", "true", "avx", "false"}) // Vectorize when strict alignment guaranteed. - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.MUL_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_F, "> 0", IRNode.MUL_VF, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIfAnd = {"AlignVector", "true", "MaxVectorSize", ">= 8"}, applyIfCPUFeatureAnd = {"sse4.1", "true", "avx", "false"}) // CPU: avx and avx2 -> vector_width: 32 -> elements in vector: 8 - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.MUL_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_F, "> 0", IRNode.MUL_VF, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIfAnd = {"AlignVector", "false", "MaxVectorSize", ">= 8"}, applyIfCPUFeatureAnd = {"avx", "true", "avx512", "false"}) // Vectorize when strict alignment guaranteed. - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.MUL_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_F, "> 0", IRNode.MUL_VF, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIfAnd = {"AlignVector", "true", "MaxVectorSize", ">= 8"}, applyIfCPUFeatureAnd = {"avx", "true", "avx512", "false"}) // CPU: avx512 -> vector_width: 64 -> elements in vector: 16 - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.MUL_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_F, "> 0", IRNode.MUL_VF, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIfAnd = {"AlignVector", "false", "MaxVectorSize", ">= 8"}, applyIfCPUFeature = {"avx512", "true"}) // Vectorize when strict alignment guaranteed. - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.MUL_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_F, "> 0", IRNode.MUL_VF, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIfAnd = {"AlignVector", "true", "MaxVectorSize", ">= 8"}, applyIfCPUFeature = {"avx512", "true"}) // CPU: asimd -> vector_width: 32 -> elements in vector: 8 - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.MUL_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_F, "> 0", IRNode.MUL_VF, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIfAnd = {"AlignVector", "false", "MaxVectorSize", ">= 8"}, applyIfCPUFeature = {"asimd", "true"}) // Vectorize when strict alignment guaranteed. - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.MUL_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_F, "> 0", IRNode.MUL_VF, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIfAnd = {"AlignVector", "true", "MaxVectorSize", ">= 8"}, applyIfCPUFeature = {"asimd", "true"}) public static void testFloatP192(float[] data) { @@ -9859,19 +9859,19 @@ public static void runFloatP192() { @Test // CPU: sse4.1 -> vector_width: 16 -> elements in vector: 2 - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.MUL_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_D, "> 0", IRNode.MUL_VD, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIfAnd = {"AlignVector", "false", "MaxVectorSize", ">= 16"}, applyIfCPUFeatureAnd = {"sse4.1", "true", "avx", "false"}) // CPU: avx and avx2 -> vector_width: 32 -> elements in vector: 4 - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.MUL_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_D, "> 0", IRNode.MUL_VD, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIfAnd = {"AlignVector", "false", "MaxVectorSize", ">= 16"}, applyIfCPUFeatureAnd = {"avx", "true", "avx512", "false"}) // CPU: avx512 -> vector_width: 64 -> elements in vector: 8 - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.MUL_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_D, "> 0", IRNode.MUL_VD, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIfAnd = {"AlignVector", "false", "MaxVectorSize", ">= 16"}, applyIfCPUFeature = {"avx512", "true"}) // CPU: asimd -> vector_width: 32 -> elements in vector: 4 - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.MUL_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_D, "> 0", IRNode.MUL_VD, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIfAnd = {"AlignVector", "false", "MaxVectorSize", ">= 16"}, applyIfCPUFeature = {"asimd", "true"}) public static void testDoubleP0(double[] data) { @@ -9891,35 +9891,35 @@ public static void runDoubleP0() { @Test // CPU: sse4.1 -> vector_width: 16 -> elements in vector: 2 - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.MUL_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_D, "> 0", IRNode.MUL_VD, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIfAnd = {"AlignVector", "false", "MaxVectorSize", ">= 16"}, applyIfCPUFeatureAnd = {"sse4.1", "true", "avx", "false"}) // Strict alignment not possible. - @IR(failOn = {IRNode.LOAD_VECTOR, IRNode.MUL_V, IRNode.STORE_VECTOR}, + @IR(failOn = {IRNode.LOAD_VECTOR_D, IRNode.MUL_VD, IRNode.STORE_VECTOR}, applyIf = {"AlignVector", "true"}, applyIfCPUFeatureAnd = {"sse4.1", "true", "avx", "false"}) // CPU: avx and avx2 -> vector_width: 32 -> elements in vector: 4 - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.MUL_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_D, "> 0", IRNode.MUL_VD, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIfAnd = {"AlignVector", "false", "MaxVectorSize", ">= 16"}, applyIfCPUFeatureAnd = {"avx", "true", "avx512", "false"}) // Strict alignment not possible. - @IR(failOn = {IRNode.LOAD_VECTOR, IRNode.MUL_V, IRNode.STORE_VECTOR}, + @IR(failOn = {IRNode.LOAD_VECTOR_D, IRNode.MUL_VD, IRNode.STORE_VECTOR}, applyIf = {"AlignVector", "true"}, applyIfCPUFeatureAnd = {"avx", "true", "avx512", "false"}) // CPU: avx512 -> vector_width: 64 -> elements in vector: 8 - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.MUL_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_D, "> 0", IRNode.MUL_VD, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIfAnd = {"AlignVector", "false", "MaxVectorSize", ">= 16"}, applyIfCPUFeature = {"avx512", "true"}) // Strict alignment not possible. - @IR(failOn = {IRNode.LOAD_VECTOR, IRNode.MUL_V, IRNode.STORE_VECTOR}, + @IR(failOn = {IRNode.LOAD_VECTOR_D, IRNode.MUL_VD, IRNode.STORE_VECTOR}, applyIf = {"AlignVector", "true"}, applyIfCPUFeature = {"avx512", "true"}) // CPU: asimd -> vector_width: 32 -> elements in vector: 4 - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.MUL_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_D, "> 0", IRNode.MUL_VD, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIfAnd = {"AlignVector", "false", "MaxVectorSize", ">= 16"}, applyIfCPUFeature = {"asimd", "true"}) // Strict alignment not possible. - @IR(failOn = {IRNode.LOAD_VECTOR, IRNode.MUL_V, IRNode.STORE_VECTOR}, + @IR(failOn = {IRNode.LOAD_VECTOR_D, IRNode.MUL_VD, IRNode.STORE_VECTOR}, applyIf = {"AlignVector", "true"}, applyIfCPUFeature = {"asimd", "true"}) public static void testDoubleM1(double[] data) { @@ -9967,19 +9967,19 @@ public static void runDoubleP1() { @Test // CPU: sse4.1 -> vector_width: 16 -> elements in vector: 2 - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.MUL_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_D, "> 0", IRNode.MUL_VD, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIfAnd = {"AlignVector", "false", "MaxVectorSize", ">= 16"}, applyIfCPUFeatureAnd = {"sse4.1", "true", "avx", "false"}) // CPU: avx and avx2 -> vector_width: 32 -> elements in vector: 4 - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.MUL_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_D, "> 0", IRNode.MUL_VD, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIfAnd = {"AlignVector", "false", "MaxVectorSize", ">= 16"}, applyIfCPUFeatureAnd = {"avx", "true", "avx512", "false"}) // CPU: avx512 -> vector_width: 64 -> elements in vector: 8 - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.MUL_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_D, "> 0", IRNode.MUL_VD, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIfAnd = {"AlignVector", "false", "MaxVectorSize", ">= 16"}, applyIfCPUFeature = {"avx512", "true"}) // CPU: asimd -> vector_width: 32 -> elements in vector: 4 - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.MUL_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_D, "> 0", IRNode.MUL_VD, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIfAnd = {"AlignVector", "false", "MaxVectorSize", ">= 16"}, applyIfCPUFeature = {"asimd", "true"}) public static void testDoubleM2(double[] data) { @@ -9999,26 +9999,26 @@ public static void runDoubleM2() { @Test // CPU: sse4.1 -> vector_width: 16 -> elements in vector: 2 - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.MUL_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_D, "> 0", IRNode.MUL_VD, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIfAnd = {"AlignVector", "false", "MaxVectorSize", ">= 16"}, applyIfCPUFeatureAnd = {"sse4.1", "true", "avx", "false"}) // Vectorize when strict alignment guaranteed. - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.MUL_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_D, "> 0", IRNode.MUL_VD, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIfAnd = {"AlignVector", "true", "MaxVectorSize", ">= 16"}, applyIfCPUFeatureAnd = {"sse4.1", "true", "avx", "false"}) // CPU: avx and avx2 -> vector_width: 32 -> elements in vector: 4 // positive byte_offset 16 can lead to cyclic dependency - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.MUL_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_D, "> 0", IRNode.MUL_VD, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIfAnd = {"AlignVector", "false", "MaxVectorSize", ">= 16", "MaxVectorSize", "<= 16"}, applyIfCPUFeatureAnd = {"avx", "true", "avx512", "false"}) // CPU: avx512 -> vector_width: 64 -> elements in vector: 8 // positive byte_offset 16 can lead to cyclic dependency - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.MUL_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_D, "> 0", IRNode.MUL_VD, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIfAnd = {"AlignVector", "false", "MaxVectorSize", ">= 16", "MaxVectorSize", "<= 16"}, applyIfCPUFeature = {"avx512", "true"}) // CPU: asimd -> vector_width: 32 -> elements in vector: 4 // positive byte_offset 16 can lead to cyclic dependency - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.MUL_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_D, "> 0", IRNode.MUL_VD, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIfAnd = {"AlignVector", "false", "MaxVectorSize", ">= 16", "MaxVectorSize", "<= 16"}, applyIfCPUFeature = {"asimd", "true"}) public static void testDoubleP2(double[] data) { @@ -10038,35 +10038,35 @@ public static void runDoubleP2() { @Test // CPU: sse4.1 -> vector_width: 16 -> elements in vector: 2 - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.MUL_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_D, "> 0", IRNode.MUL_VD, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIfAnd = {"AlignVector", "false", "MaxVectorSize", ">= 16"}, applyIfCPUFeatureAnd = {"sse4.1", "true", "avx", "false"}) // Strict alignment not possible. - @IR(failOn = {IRNode.LOAD_VECTOR, IRNode.MUL_V, IRNode.STORE_VECTOR}, + @IR(failOn = {IRNode.LOAD_VECTOR_D, IRNode.MUL_VD, IRNode.STORE_VECTOR}, applyIf = {"AlignVector", "true"}, applyIfCPUFeatureAnd = {"sse4.1", "true", "avx", "false"}) // CPU: avx and avx2 -> vector_width: 32 -> elements in vector: 4 - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.MUL_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_D, "> 0", IRNode.MUL_VD, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIfAnd = {"AlignVector", "false", "MaxVectorSize", ">= 16"}, applyIfCPUFeatureAnd = {"avx", "true", "avx512", "false"}) // Strict alignment not possible. - @IR(failOn = {IRNode.LOAD_VECTOR, IRNode.MUL_V, IRNode.STORE_VECTOR}, + @IR(failOn = {IRNode.LOAD_VECTOR_D, IRNode.MUL_VD, IRNode.STORE_VECTOR}, applyIf = {"AlignVector", "true"}, applyIfCPUFeatureAnd = {"avx", "true", "avx512", "false"}) // CPU: avx512 -> vector_width: 64 -> elements in vector: 8 - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.MUL_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_D, "> 0", IRNode.MUL_VD, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIfAnd = {"AlignVector", "false", "MaxVectorSize", ">= 16"}, applyIfCPUFeature = {"avx512", "true"}) // Strict alignment not possible. - @IR(failOn = {IRNode.LOAD_VECTOR, IRNode.MUL_V, IRNode.STORE_VECTOR}, + @IR(failOn = {IRNode.LOAD_VECTOR_D, IRNode.MUL_VD, IRNode.STORE_VECTOR}, applyIf = {"AlignVector", "true"}, applyIfCPUFeature = {"avx512", "true"}) // CPU: asimd -> vector_width: 32 -> elements in vector: 4 - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.MUL_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_D, "> 0", IRNode.MUL_VD, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIfAnd = {"AlignVector", "false", "MaxVectorSize", ">= 16"}, applyIfCPUFeature = {"asimd", "true"}) // Strict alignment not possible. - @IR(failOn = {IRNode.LOAD_VECTOR, IRNode.MUL_V, IRNode.STORE_VECTOR}, + @IR(failOn = {IRNode.LOAD_VECTOR_D, IRNode.MUL_VD, IRNode.STORE_VECTOR}, applyIf = {"AlignVector", "true"}, applyIfCPUFeature = {"asimd", "true"}) public static void testDoubleM3(double[] data) { @@ -10086,22 +10086,22 @@ public static void runDoubleM3() { @Test // CPU: sse4.1 -> vector_width: 16 -> elements in vector: 2 - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.MUL_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_D, "> 0", IRNode.MUL_VD, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIfAnd = {"AlignVector", "false", "MaxVectorSize", ">= 16"}, applyIfCPUFeatureAnd = {"sse4.1", "true", "avx", "false"}) // CPU: avx and avx2 -> vector_width: 32 -> elements in vector: 4 // positive byte_offset 24 can lead to cyclic dependency - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.MUL_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_D, "> 0", IRNode.MUL_VD, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIfAnd = {"AlignVector", "false", "MaxVectorSize", ">= 16", "MaxVectorSize", "<= 24"}, applyIfCPUFeatureAnd = {"avx", "true", "avx512", "false"}) // CPU: avx512 -> vector_width: 64 -> elements in vector: 8 // positive byte_offset 24 can lead to cyclic dependency - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.MUL_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_D, "> 0", IRNode.MUL_VD, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIfAnd = {"AlignVector", "false", "MaxVectorSize", ">= 16", "MaxVectorSize", "<= 24"}, applyIfCPUFeature = {"avx512", "true"}) // CPU: asimd -> vector_width: 32 -> elements in vector: 4 // positive byte_offset 24 can lead to cyclic dependency - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.MUL_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_D, "> 0", IRNode.MUL_VD, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIfAnd = {"AlignVector", "false", "MaxVectorSize", ">= 16", "MaxVectorSize", "<= 24"}, applyIfCPUFeature = {"asimd", "true"}) public static void testDoubleP3(double[] data) { @@ -10121,19 +10121,19 @@ public static void runDoubleP3() { @Test // CPU: sse4.1 -> vector_width: 16 -> elements in vector: 2 - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.MUL_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_D, "> 0", IRNode.MUL_VD, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIfAnd = {"AlignVector", "false", "MaxVectorSize", ">= 16"}, applyIfCPUFeatureAnd = {"sse4.1", "true", "avx", "false"}) // CPU: avx and avx2 -> vector_width: 32 -> elements in vector: 4 - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.MUL_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_D, "> 0", IRNode.MUL_VD, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIfAnd = {"AlignVector", "false", "MaxVectorSize", ">= 16"}, applyIfCPUFeatureAnd = {"avx", "true", "avx512", "false"}) // CPU: avx512 -> vector_width: 64 -> elements in vector: 8 - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.MUL_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_D, "> 0", IRNode.MUL_VD, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIfAnd = {"AlignVector", "false", "MaxVectorSize", ">= 16"}, applyIfCPUFeature = {"avx512", "true"}) // CPU: asimd -> vector_width: 32 -> elements in vector: 4 - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.MUL_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_D, "> 0", IRNode.MUL_VD, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIfAnd = {"AlignVector", "false", "MaxVectorSize", ">= 16"}, applyIfCPUFeature = {"asimd", "true"}) public static void testDoubleM4(double[] data) { @@ -10153,32 +10153,32 @@ public static void runDoubleM4() { @Test // CPU: sse4.1 -> vector_width: 16 -> elements in vector: 2 - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.MUL_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_D, "> 0", IRNode.MUL_VD, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIfAnd = {"AlignVector", "false", "MaxVectorSize", ">= 16"}, applyIfCPUFeatureAnd = {"sse4.1", "true", "avx", "false"}) // Vectorize when strict alignment guaranteed. - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.MUL_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_D, "> 0", IRNode.MUL_VD, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIfAnd = {"AlignVector", "true", "MaxVectorSize", ">= 16"}, applyIfCPUFeatureAnd = {"sse4.1", "true", "avx", "false"}) // CPU: avx and avx2 -> vector_width: 32 -> elements in vector: 4 - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.MUL_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_D, "> 0", IRNode.MUL_VD, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIfAnd = {"AlignVector", "false", "MaxVectorSize", ">= 16"}, applyIfCPUFeatureAnd = {"avx", "true", "avx512", "false"}) // Vectorize when strict alignment guaranteed. - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.MUL_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_D, "> 0", IRNode.MUL_VD, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIfAnd = {"AlignVector", "true", "MaxVectorSize", ">= 16"}, applyIfCPUFeatureAnd = {"avx", "true", "avx512", "false"}) // CPU: avx512 -> vector_width: 64 -> elements in vector: 8 // positive byte_offset 32 can lead to cyclic dependency - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.MUL_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_D, "> 0", IRNode.MUL_VD, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIfAnd = {"AlignVector", "false", "MaxVectorSize", ">= 16", "MaxVectorSize", "<= 32"}, applyIfCPUFeature = {"avx512", "true"}) // CPU: asimd -> vector_width: 32 -> elements in vector: 4 - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.MUL_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_D, "> 0", IRNode.MUL_VD, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIfAnd = {"AlignVector", "false", "MaxVectorSize", ">= 16"}, applyIfCPUFeature = {"asimd", "true"}) // Vectorize when strict alignment guaranteed. - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.MUL_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_D, "> 0", IRNode.MUL_VD, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIfAnd = {"AlignVector", "true", "MaxVectorSize", ">= 16"}, applyIfCPUFeature = {"asimd", "true"}) public static void testDoubleP4(double[] data) { @@ -10198,35 +10198,35 @@ public static void runDoubleP4() { @Test // CPU: sse4.1 -> vector_width: 16 -> elements in vector: 2 - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.MUL_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_D, "> 0", IRNode.MUL_VD, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIfAnd = {"AlignVector", "false", "MaxVectorSize", ">= 16"}, applyIfCPUFeatureAnd = {"sse4.1", "true", "avx", "false"}) // Strict alignment not possible. - @IR(failOn = {IRNode.LOAD_VECTOR, IRNode.MUL_V, IRNode.STORE_VECTOR}, + @IR(failOn = {IRNode.LOAD_VECTOR_D, IRNode.MUL_VD, IRNode.STORE_VECTOR}, applyIf = {"AlignVector", "true"}, applyIfCPUFeatureAnd = {"sse4.1", "true", "avx", "false"}) // CPU: avx and avx2 -> vector_width: 32 -> elements in vector: 4 - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.MUL_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_D, "> 0", IRNode.MUL_VD, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIfAnd = {"AlignVector", "false", "MaxVectorSize", ">= 16"}, applyIfCPUFeatureAnd = {"avx", "true", "avx512", "false"}) // Strict alignment not possible. - @IR(failOn = {IRNode.LOAD_VECTOR, IRNode.MUL_V, IRNode.STORE_VECTOR}, + @IR(failOn = {IRNode.LOAD_VECTOR_D, IRNode.MUL_VD, IRNode.STORE_VECTOR}, applyIf = {"AlignVector", "true"}, applyIfCPUFeatureAnd = {"avx", "true", "avx512", "false"}) // CPU: avx512 -> vector_width: 64 -> elements in vector: 8 - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.MUL_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_D, "> 0", IRNode.MUL_VD, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIfAnd = {"AlignVector", "false", "MaxVectorSize", ">= 16"}, applyIfCPUFeature = {"avx512", "true"}) // Strict alignment not possible. - @IR(failOn = {IRNode.LOAD_VECTOR, IRNode.MUL_V, IRNode.STORE_VECTOR}, + @IR(failOn = {IRNode.LOAD_VECTOR_D, IRNode.MUL_VD, IRNode.STORE_VECTOR}, applyIf = {"AlignVector", "true"}, applyIfCPUFeature = {"avx512", "true"}) // CPU: asimd -> vector_width: 32 -> elements in vector: 4 - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.MUL_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_D, "> 0", IRNode.MUL_VD, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIfAnd = {"AlignVector", "false", "MaxVectorSize", ">= 16"}, applyIfCPUFeature = {"asimd", "true"}) // Strict alignment not possible. - @IR(failOn = {IRNode.LOAD_VECTOR, IRNode.MUL_V, IRNode.STORE_VECTOR}, + @IR(failOn = {IRNode.LOAD_VECTOR_D, IRNode.MUL_VD, IRNode.STORE_VECTOR}, applyIf = {"AlignVector", "true"}, applyIfCPUFeature = {"asimd", "true"}) public static void testDoubleM7(double[] data) { @@ -10246,20 +10246,20 @@ public static void runDoubleM7() { @Test // CPU: sse4.1 -> vector_width: 16 -> elements in vector: 2 - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.MUL_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_D, "> 0", IRNode.MUL_VD, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIfAnd = {"AlignVector", "false", "MaxVectorSize", ">= 16"}, applyIfCPUFeatureAnd = {"sse4.1", "true", "avx", "false"}) // CPU: avx and avx2 -> vector_width: 32 -> elements in vector: 4 - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.MUL_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_D, "> 0", IRNode.MUL_VD, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIfAnd = {"AlignVector", "false", "MaxVectorSize", ">= 16"}, applyIfCPUFeatureAnd = {"avx", "true", "avx512", "false"}) // CPU: avx512 -> vector_width: 64 -> elements in vector: 8 // positive byte_offset 56 can lead to cyclic dependency - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.MUL_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_D, "> 0", IRNode.MUL_VD, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIfAnd = {"AlignVector", "false", "MaxVectorSize", ">= 16", "MaxVectorSize", "<= 56"}, applyIfCPUFeature = {"avx512", "true"}) // CPU: asimd -> vector_width: 32 -> elements in vector: 4 - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.MUL_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_D, "> 0", IRNode.MUL_VD, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIfAnd = {"AlignVector", "false", "MaxVectorSize", ">= 16"}, applyIfCPUFeature = {"asimd", "true"}) public static void testDoubleP7(double[] data) { @@ -10279,19 +10279,19 @@ public static void runDoubleP7() { @Test // CPU: sse4.1 -> vector_width: 16 -> elements in vector: 2 - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.MUL_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_D, "> 0", IRNode.MUL_VD, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIfAnd = {"AlignVector", "false", "MaxVectorSize", ">= 16"}, applyIfCPUFeatureAnd = {"sse4.1", "true", "avx", "false"}) // CPU: avx and avx2 -> vector_width: 32 -> elements in vector: 4 - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.MUL_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_D, "> 0", IRNode.MUL_VD, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIfAnd = {"AlignVector", "false", "MaxVectorSize", ">= 16"}, applyIfCPUFeatureAnd = {"avx", "true", "avx512", "false"}) // CPU: avx512 -> vector_width: 64 -> elements in vector: 8 - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.MUL_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_D, "> 0", IRNode.MUL_VD, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIfAnd = {"AlignVector", "false", "MaxVectorSize", ">= 16"}, applyIfCPUFeature = {"avx512", "true"}) // CPU: asimd -> vector_width: 32 -> elements in vector: 4 - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.MUL_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_D, "> 0", IRNode.MUL_VD, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIfAnd = {"AlignVector", "false", "MaxVectorSize", ">= 16"}, applyIfCPUFeature = {"asimd", "true"}) public static void testDoubleM8(double[] data) { @@ -10311,35 +10311,35 @@ public static void runDoubleM8() { @Test // CPU: sse4.1 -> vector_width: 16 -> elements in vector: 2 - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.MUL_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_D, "> 0", IRNode.MUL_VD, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIfAnd = {"AlignVector", "false", "MaxVectorSize", ">= 16"}, applyIfCPUFeatureAnd = {"sse4.1", "true", "avx", "false"}) // Vectorize when strict alignment guaranteed. - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.MUL_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_D, "> 0", IRNode.MUL_VD, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIfAnd = {"AlignVector", "true", "MaxVectorSize", ">= 16"}, applyIfCPUFeatureAnd = {"sse4.1", "true", "avx", "false"}) // CPU: avx and avx2 -> vector_width: 32 -> elements in vector: 4 - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.MUL_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_D, "> 0", IRNode.MUL_VD, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIfAnd = {"AlignVector", "false", "MaxVectorSize", ">= 16"}, applyIfCPUFeatureAnd = {"avx", "true", "avx512", "false"}) // Vectorize when strict alignment guaranteed. - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.MUL_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_D, "> 0", IRNode.MUL_VD, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIfAnd = {"AlignVector", "true", "MaxVectorSize", ">= 16"}, applyIfCPUFeatureAnd = {"avx", "true", "avx512", "false"}) // CPU: avx512 -> vector_width: 64 -> elements in vector: 8 - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.MUL_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_D, "> 0", IRNode.MUL_VD, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIfAnd = {"AlignVector", "false", "MaxVectorSize", ">= 16"}, applyIfCPUFeature = {"avx512", "true"}) // Vectorize when strict alignment guaranteed. - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.MUL_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_D, "> 0", IRNode.MUL_VD, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIfAnd = {"AlignVector", "true", "MaxVectorSize", ">= 16"}, applyIfCPUFeature = {"avx512", "true"}) // CPU: asimd -> vector_width: 32 -> elements in vector: 4 - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.MUL_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_D, "> 0", IRNode.MUL_VD, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIfAnd = {"AlignVector", "false", "MaxVectorSize", ">= 16"}, applyIfCPUFeature = {"asimd", "true"}) // Vectorize when strict alignment guaranteed. - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.MUL_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_D, "> 0", IRNode.MUL_VD, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIfAnd = {"AlignVector", "true", "MaxVectorSize", ">= 16"}, applyIfCPUFeature = {"asimd", "true"}) public static void testDoubleP8(double[] data) { @@ -10359,19 +10359,19 @@ public static void runDoubleP8() { @Test // CPU: sse4.1 -> vector_width: 16 -> elements in vector: 2 - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.MUL_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_D, "> 0", IRNode.MUL_VD, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIfAnd = {"AlignVector", "false", "MaxVectorSize", ">= 16"}, applyIfCPUFeatureAnd = {"sse4.1", "true", "avx", "false"}) // CPU: avx and avx2 -> vector_width: 32 -> elements in vector: 4 - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.MUL_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_D, "> 0", IRNode.MUL_VD, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIfAnd = {"AlignVector", "false", "MaxVectorSize", ">= 16"}, applyIfCPUFeatureAnd = {"avx", "true", "avx512", "false"}) // CPU: avx512 -> vector_width: 64 -> elements in vector: 8 - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.MUL_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_D, "> 0", IRNode.MUL_VD, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIfAnd = {"AlignVector", "false", "MaxVectorSize", ">= 16"}, applyIfCPUFeature = {"avx512", "true"}) // CPU: asimd -> vector_width: 32 -> elements in vector: 4 - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.MUL_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_D, "> 0", IRNode.MUL_VD, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIfAnd = {"AlignVector", "false", "MaxVectorSize", ">= 16"}, applyIfCPUFeature = {"asimd", "true"}) public static void testDoubleM14(double[] data) { @@ -10391,23 +10391,23 @@ public static void runDoubleM14() { @Test // CPU: sse4.1 -> vector_width: 16 -> elements in vector: 2 - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.MUL_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_D, "> 0", IRNode.MUL_VD, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIfAnd = {"AlignVector", "false", "MaxVectorSize", ">= 16"}, applyIfCPUFeatureAnd = {"sse4.1", "true", "avx", "false"}) // Vectorize when strict alignment guaranteed. - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.MUL_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_D, "> 0", IRNode.MUL_VD, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIfAnd = {"AlignVector", "true", "MaxVectorSize", ">= 16"}, applyIfCPUFeatureAnd = {"sse4.1", "true", "avx", "false"}) // CPU: avx and avx2 -> vector_width: 32 -> elements in vector: 4 - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.MUL_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_D, "> 0", IRNode.MUL_VD, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIfAnd = {"AlignVector", "false", "MaxVectorSize", ">= 16"}, applyIfCPUFeatureAnd = {"avx", "true", "avx512", "false"}) // CPU: avx512 -> vector_width: 64 -> elements in vector: 8 - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.MUL_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_D, "> 0", IRNode.MUL_VD, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIfAnd = {"AlignVector", "false", "MaxVectorSize", ">= 16"}, applyIfCPUFeature = {"avx512", "true"}) // CPU: asimd -> vector_width: 32 -> elements in vector: 4 - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.MUL_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_D, "> 0", IRNode.MUL_VD, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIfAnd = {"AlignVector", "false", "MaxVectorSize", ">= 16"}, applyIfCPUFeature = {"asimd", "true"}) public static void testDoubleP14(double[] data) { @@ -10427,19 +10427,19 @@ public static void runDoubleP14() { @Test // CPU: sse4.1 -> vector_width: 16 -> elements in vector: 2 - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.MUL_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_D, "> 0", IRNode.MUL_VD, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIfAnd = {"AlignVector", "false", "MaxVectorSize", ">= 16"}, applyIfCPUFeatureAnd = {"sse4.1", "true", "avx", "false"}) // CPU: avx and avx2 -> vector_width: 32 -> elements in vector: 4 - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.MUL_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_D, "> 0", IRNode.MUL_VD, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIfAnd = {"AlignVector", "false", "MaxVectorSize", ">= 16"}, applyIfCPUFeatureAnd = {"avx", "true", "avx512", "false"}) // CPU: avx512 -> vector_width: 64 -> elements in vector: 8 - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.MUL_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_D, "> 0", IRNode.MUL_VD, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIfAnd = {"AlignVector", "false", "MaxVectorSize", ">= 16"}, applyIfCPUFeature = {"avx512", "true"}) // CPU: asimd -> vector_width: 32 -> elements in vector: 4 - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.MUL_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_D, "> 0", IRNode.MUL_VD, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIfAnd = {"AlignVector", "false", "MaxVectorSize", ">= 16"}, applyIfCPUFeature = {"asimd", "true"}) public static void testDoubleM16(double[] data) { @@ -10459,35 +10459,35 @@ public static void runDoubleM16() { @Test // CPU: sse4.1 -> vector_width: 16 -> elements in vector: 2 - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.MUL_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_D, "> 0", IRNode.MUL_VD, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIfAnd = {"AlignVector", "false", "MaxVectorSize", ">= 16"}, applyIfCPUFeatureAnd = {"sse4.1", "true", "avx", "false"}) // Vectorize when strict alignment guaranteed. - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.MUL_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_D, "> 0", IRNode.MUL_VD, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIfAnd = {"AlignVector", "true", "MaxVectorSize", ">= 16"}, applyIfCPUFeatureAnd = {"sse4.1", "true", "avx", "false"}) // CPU: avx and avx2 -> vector_width: 32 -> elements in vector: 4 - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.MUL_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_D, "> 0", IRNode.MUL_VD, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIfAnd = {"AlignVector", "false", "MaxVectorSize", ">= 16"}, applyIfCPUFeatureAnd = {"avx", "true", "avx512", "false"}) // Vectorize when strict alignment guaranteed. - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.MUL_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_D, "> 0", IRNode.MUL_VD, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIfAnd = {"AlignVector", "true", "MaxVectorSize", ">= 16"}, applyIfCPUFeatureAnd = {"avx", "true", "avx512", "false"}) // CPU: avx512 -> vector_width: 64 -> elements in vector: 8 - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.MUL_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_D, "> 0", IRNode.MUL_VD, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIfAnd = {"AlignVector", "false", "MaxVectorSize", ">= 16"}, applyIfCPUFeature = {"avx512", "true"}) // Vectorize when strict alignment guaranteed. - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.MUL_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_D, "> 0", IRNode.MUL_VD, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIfAnd = {"AlignVector", "true", "MaxVectorSize", ">= 16"}, applyIfCPUFeature = {"avx512", "true"}) // CPU: asimd -> vector_width: 32 -> elements in vector: 4 - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.MUL_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_D, "> 0", IRNode.MUL_VD, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIfAnd = {"AlignVector", "false", "MaxVectorSize", ">= 16"}, applyIfCPUFeature = {"asimd", "true"}) // Vectorize when strict alignment guaranteed. - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.MUL_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_D, "> 0", IRNode.MUL_VD, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIfAnd = {"AlignVector", "true", "MaxVectorSize", ">= 16"}, applyIfCPUFeature = {"asimd", "true"}) public static void testDoubleP16(double[] data) { @@ -10507,19 +10507,19 @@ public static void runDoubleP16() { @Test // CPU: sse4.1 -> vector_width: 16 -> elements in vector: 2 - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.MUL_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_D, "> 0", IRNode.MUL_VD, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIfAnd = {"AlignVector", "false", "MaxVectorSize", ">= 16"}, applyIfCPUFeatureAnd = {"sse4.1", "true", "avx", "false"}) // CPU: avx and avx2 -> vector_width: 32 -> elements in vector: 4 - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.MUL_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_D, "> 0", IRNode.MUL_VD, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIfAnd = {"AlignVector", "false", "MaxVectorSize", ">= 16"}, applyIfCPUFeatureAnd = {"avx", "true", "avx512", "false"}) // CPU: avx512 -> vector_width: 64 -> elements in vector: 8 - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.MUL_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_D, "> 0", IRNode.MUL_VD, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIfAnd = {"AlignVector", "false", "MaxVectorSize", ">= 16"}, applyIfCPUFeature = {"avx512", "true"}) // CPU: asimd -> vector_width: 32 -> elements in vector: 4 - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.MUL_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_D, "> 0", IRNode.MUL_VD, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIfAnd = {"AlignVector", "false", "MaxVectorSize", ">= 16"}, applyIfCPUFeature = {"asimd", "true"}) public static void testDoubleM18(double[] data) { @@ -10539,23 +10539,23 @@ public static void runDoubleM18() { @Test // CPU: sse4.1 -> vector_width: 16 -> elements in vector: 2 - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.MUL_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_D, "> 0", IRNode.MUL_VD, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIfAnd = {"AlignVector", "false", "MaxVectorSize", ">= 16"}, applyIfCPUFeatureAnd = {"sse4.1", "true", "avx", "false"}) // Vectorize when strict alignment guaranteed. - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.MUL_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_D, "> 0", IRNode.MUL_VD, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIfAnd = {"AlignVector", "true", "MaxVectorSize", ">= 16"}, applyIfCPUFeatureAnd = {"sse4.1", "true", "avx", "false"}) // CPU: avx and avx2 -> vector_width: 32 -> elements in vector: 4 - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.MUL_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_D, "> 0", IRNode.MUL_VD, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIfAnd = {"AlignVector", "false", "MaxVectorSize", ">= 16"}, applyIfCPUFeatureAnd = {"avx", "true", "avx512", "false"}) // CPU: avx512 -> vector_width: 64 -> elements in vector: 8 - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.MUL_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_D, "> 0", IRNode.MUL_VD, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIfAnd = {"AlignVector", "false", "MaxVectorSize", ">= 16"}, applyIfCPUFeature = {"avx512", "true"}) // CPU: asimd -> vector_width: 32 -> elements in vector: 4 - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.MUL_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_D, "> 0", IRNode.MUL_VD, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIfAnd = {"AlignVector", "false", "MaxVectorSize", ">= 16"}, applyIfCPUFeature = {"asimd", "true"}) public static void testDoubleP18(double[] data) { @@ -10575,19 +10575,19 @@ public static void runDoubleP18() { @Test // CPU: sse4.1 -> vector_width: 16 -> elements in vector: 2 - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.MUL_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_D, "> 0", IRNode.MUL_VD, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIfAnd = {"AlignVector", "false", "MaxVectorSize", ">= 16"}, applyIfCPUFeatureAnd = {"sse4.1", "true", "avx", "false"}) // CPU: avx and avx2 -> vector_width: 32 -> elements in vector: 4 - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.MUL_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_D, "> 0", IRNode.MUL_VD, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIfAnd = {"AlignVector", "false", "MaxVectorSize", ">= 16"}, applyIfCPUFeatureAnd = {"avx", "true", "avx512", "false"}) // CPU: avx512 -> vector_width: 64 -> elements in vector: 8 - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.MUL_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_D, "> 0", IRNode.MUL_VD, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIfAnd = {"AlignVector", "false", "MaxVectorSize", ">= 16"}, applyIfCPUFeature = {"avx512", "true"}) // CPU: asimd -> vector_width: 32 -> elements in vector: 4 - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.MUL_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_D, "> 0", IRNode.MUL_VD, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIfAnd = {"AlignVector", "false", "MaxVectorSize", ">= 16"}, applyIfCPUFeature = {"asimd", "true"}) public static void testDoubleM20(double[] data) { @@ -10607,31 +10607,31 @@ public static void runDoubleM20() { @Test // CPU: sse4.1 -> vector_width: 16 -> elements in vector: 2 - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.MUL_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_D, "> 0", IRNode.MUL_VD, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIfAnd = {"AlignVector", "false", "MaxVectorSize", ">= 16"}, applyIfCPUFeatureAnd = {"sse4.1", "true", "avx", "false"}) // Vectorize when strict alignment guaranteed. - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.MUL_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_D, "> 0", IRNode.MUL_VD, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIfAnd = {"AlignVector", "true", "MaxVectorSize", ">= 16"}, applyIfCPUFeatureAnd = {"sse4.1", "true", "avx", "false"}) // CPU: avx and avx2 -> vector_width: 32 -> elements in vector: 4 - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.MUL_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_D, "> 0", IRNode.MUL_VD, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIfAnd = {"AlignVector", "false", "MaxVectorSize", ">= 16"}, applyIfCPUFeatureAnd = {"avx", "true", "avx512", "false"}) // Vectorize when strict alignment guaranteed. - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.MUL_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_D, "> 0", IRNode.MUL_VD, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIfAnd = {"AlignVector", "true", "MaxVectorSize", ">= 16"}, applyIfCPUFeatureAnd = {"avx", "true", "avx512", "false"}) // CPU: avx512 -> vector_width: 64 -> elements in vector: 8 - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.MUL_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_D, "> 0", IRNode.MUL_VD, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIfAnd = {"AlignVector", "false", "MaxVectorSize", ">= 16"}, applyIfCPUFeature = {"avx512", "true"}) // CPU: asimd -> vector_width: 32 -> elements in vector: 4 - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.MUL_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_D, "> 0", IRNode.MUL_VD, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIfAnd = {"AlignVector", "false", "MaxVectorSize", ">= 16"}, applyIfCPUFeature = {"asimd", "true"}) // Vectorize when strict alignment guaranteed. - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.MUL_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_D, "> 0", IRNode.MUL_VD, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIfAnd = {"AlignVector", "true", "MaxVectorSize", ">= 16"}, applyIfCPUFeature = {"asimd", "true"}) public static void testDoubleP20(double[] data) { @@ -10651,35 +10651,35 @@ public static void runDoubleP20() { @Test // CPU: sse4.1 -> vector_width: 16 -> elements in vector: 2 - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.MUL_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_D, "> 0", IRNode.MUL_VD, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIfAnd = {"AlignVector", "false", "MaxVectorSize", ">= 16"}, applyIfCPUFeatureAnd = {"sse4.1", "true", "avx", "false"}) // Strict alignment not possible. - @IR(failOn = {IRNode.LOAD_VECTOR, IRNode.MUL_V, IRNode.STORE_VECTOR}, + @IR(failOn = {IRNode.LOAD_VECTOR_D, IRNode.MUL_VD, IRNode.STORE_VECTOR}, applyIf = {"AlignVector", "true"}, applyIfCPUFeatureAnd = {"sse4.1", "true", "avx", "false"}) // CPU: avx and avx2 -> vector_width: 32 -> elements in vector: 4 - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.MUL_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_D, "> 0", IRNode.MUL_VD, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIfAnd = {"AlignVector", "false", "MaxVectorSize", ">= 16"}, applyIfCPUFeatureAnd = {"avx", "true", "avx512", "false"}) // Strict alignment not possible. - @IR(failOn = {IRNode.LOAD_VECTOR, IRNode.MUL_V, IRNode.STORE_VECTOR}, + @IR(failOn = {IRNode.LOAD_VECTOR_D, IRNode.MUL_VD, IRNode.STORE_VECTOR}, applyIf = {"AlignVector", "true"}, applyIfCPUFeatureAnd = {"avx", "true", "avx512", "false"}) // CPU: avx512 -> vector_width: 64 -> elements in vector: 8 - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.MUL_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_D, "> 0", IRNode.MUL_VD, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIfAnd = {"AlignVector", "false", "MaxVectorSize", ">= 16"}, applyIfCPUFeature = {"avx512", "true"}) // Strict alignment not possible. - @IR(failOn = {IRNode.LOAD_VECTOR, IRNode.MUL_V, IRNode.STORE_VECTOR}, + @IR(failOn = {IRNode.LOAD_VECTOR_D, IRNode.MUL_VD, IRNode.STORE_VECTOR}, applyIf = {"AlignVector", "true"}, applyIfCPUFeature = {"avx512", "true"}) // CPU: asimd -> vector_width: 32 -> elements in vector: 4 - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.MUL_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_D, "> 0", IRNode.MUL_VD, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIfAnd = {"AlignVector", "false", "MaxVectorSize", ">= 16"}, applyIfCPUFeature = {"asimd", "true"}) // Strict alignment not possible. - @IR(failOn = {IRNode.LOAD_VECTOR, IRNode.MUL_V, IRNode.STORE_VECTOR}, + @IR(failOn = {IRNode.LOAD_VECTOR_D, IRNode.MUL_VD, IRNode.STORE_VECTOR}, applyIf = {"AlignVector", "true"}, applyIfCPUFeature = {"asimd", "true"}) public static void testDoubleM31(double[] data) { @@ -10699,19 +10699,19 @@ public static void runDoubleM31() { @Test // CPU: sse4.1 -> vector_width: 16 -> elements in vector: 2 - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.MUL_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_D, "> 0", IRNode.MUL_VD, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIfAnd = {"AlignVector", "false", "MaxVectorSize", ">= 16"}, applyIfCPUFeatureAnd = {"sse4.1", "true", "avx", "false"}) // CPU: avx and avx2 -> vector_width: 32 -> elements in vector: 4 - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.MUL_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_D, "> 0", IRNode.MUL_VD, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIfAnd = {"AlignVector", "false", "MaxVectorSize", ">= 16"}, applyIfCPUFeatureAnd = {"avx", "true", "avx512", "false"}) // CPU: avx512 -> vector_width: 64 -> elements in vector: 8 - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.MUL_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_D, "> 0", IRNode.MUL_VD, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIfAnd = {"AlignVector", "false", "MaxVectorSize", ">= 16"}, applyIfCPUFeature = {"avx512", "true"}) // CPU: asimd -> vector_width: 32 -> elements in vector: 4 - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.MUL_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_D, "> 0", IRNode.MUL_VD, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIfAnd = {"AlignVector", "false", "MaxVectorSize", ">= 16"}, applyIfCPUFeature = {"asimd", "true"}) public static void testDoubleP31(double[] data) { @@ -10731,19 +10731,19 @@ public static void runDoubleP31() { @Test // CPU: sse4.1 -> vector_width: 16 -> elements in vector: 2 - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.MUL_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_D, "> 0", IRNode.MUL_VD, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIfAnd = {"AlignVector", "false", "MaxVectorSize", ">= 16"}, applyIfCPUFeatureAnd = {"sse4.1", "true", "avx", "false"}) // CPU: avx and avx2 -> vector_width: 32 -> elements in vector: 4 - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.MUL_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_D, "> 0", IRNode.MUL_VD, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIfAnd = {"AlignVector", "false", "MaxVectorSize", ">= 16"}, applyIfCPUFeatureAnd = {"avx", "true", "avx512", "false"}) // CPU: avx512 -> vector_width: 64 -> elements in vector: 8 - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.MUL_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_D, "> 0", IRNode.MUL_VD, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIfAnd = {"AlignVector", "false", "MaxVectorSize", ">= 16"}, applyIfCPUFeature = {"avx512", "true"}) // CPU: asimd -> vector_width: 32 -> elements in vector: 4 - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.MUL_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_D, "> 0", IRNode.MUL_VD, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIfAnd = {"AlignVector", "false", "MaxVectorSize", ">= 16"}, applyIfCPUFeature = {"asimd", "true"}) public static void testDoubleM32(double[] data) { @@ -10763,35 +10763,35 @@ public static void runDoubleM32() { @Test // CPU: sse4.1 -> vector_width: 16 -> elements in vector: 2 - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.MUL_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_D, "> 0", IRNode.MUL_VD, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIfAnd = {"AlignVector", "false", "MaxVectorSize", ">= 16"}, applyIfCPUFeatureAnd = {"sse4.1", "true", "avx", "false"}) // Vectorize when strict alignment guaranteed. - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.MUL_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_D, "> 0", IRNode.MUL_VD, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIfAnd = {"AlignVector", "true", "MaxVectorSize", ">= 16"}, applyIfCPUFeatureAnd = {"sse4.1", "true", "avx", "false"}) // CPU: avx and avx2 -> vector_width: 32 -> elements in vector: 4 - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.MUL_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_D, "> 0", IRNode.MUL_VD, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIfAnd = {"AlignVector", "false", "MaxVectorSize", ">= 16"}, applyIfCPUFeatureAnd = {"avx", "true", "avx512", "false"}) // Vectorize when strict alignment guaranteed. - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.MUL_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_D, "> 0", IRNode.MUL_VD, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIfAnd = {"AlignVector", "true", "MaxVectorSize", ">= 16"}, applyIfCPUFeatureAnd = {"avx", "true", "avx512", "false"}) // CPU: avx512 -> vector_width: 64 -> elements in vector: 8 - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.MUL_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_D, "> 0", IRNode.MUL_VD, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIfAnd = {"AlignVector", "false", "MaxVectorSize", ">= 16"}, applyIfCPUFeature = {"avx512", "true"}) // Vectorize when strict alignment guaranteed. - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.MUL_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_D, "> 0", IRNode.MUL_VD, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIfAnd = {"AlignVector", "true", "MaxVectorSize", ">= 16"}, applyIfCPUFeature = {"avx512", "true"}) // CPU: asimd -> vector_width: 32 -> elements in vector: 4 - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.MUL_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_D, "> 0", IRNode.MUL_VD, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIfAnd = {"AlignVector", "false", "MaxVectorSize", ">= 16"}, applyIfCPUFeature = {"asimd", "true"}) // Vectorize when strict alignment guaranteed. - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.MUL_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_D, "> 0", IRNode.MUL_VD, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIfAnd = {"AlignVector", "true", "MaxVectorSize", ">= 16"}, applyIfCPUFeature = {"asimd", "true"}) public static void testDoubleP32(double[] data) { @@ -10811,35 +10811,35 @@ public static void runDoubleP32() { @Test // CPU: sse4.1 -> vector_width: 16 -> elements in vector: 2 - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.MUL_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_D, "> 0", IRNode.MUL_VD, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIfAnd = {"AlignVector", "false", "MaxVectorSize", ">= 16"}, applyIfCPUFeatureAnd = {"sse4.1", "true", "avx", "false"}) // Strict alignment not possible. - @IR(failOn = {IRNode.LOAD_VECTOR, IRNode.MUL_V, IRNode.STORE_VECTOR}, + @IR(failOn = {IRNode.LOAD_VECTOR_D, IRNode.MUL_VD, IRNode.STORE_VECTOR}, applyIf = {"AlignVector", "true"}, applyIfCPUFeatureAnd = {"sse4.1", "true", "avx", "false"}) // CPU: avx and avx2 -> vector_width: 32 -> elements in vector: 4 - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.MUL_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_D, "> 0", IRNode.MUL_VD, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIfAnd = {"AlignVector", "false", "MaxVectorSize", ">= 16"}, applyIfCPUFeatureAnd = {"avx", "true", "avx512", "false"}) // Strict alignment not possible. - @IR(failOn = {IRNode.LOAD_VECTOR, IRNode.MUL_V, IRNode.STORE_VECTOR}, + @IR(failOn = {IRNode.LOAD_VECTOR_D, IRNode.MUL_VD, IRNode.STORE_VECTOR}, applyIf = {"AlignVector", "true"}, applyIfCPUFeatureAnd = {"avx", "true", "avx512", "false"}) // CPU: avx512 -> vector_width: 64 -> elements in vector: 8 - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.MUL_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_D, "> 0", IRNode.MUL_VD, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIfAnd = {"AlignVector", "false", "MaxVectorSize", ">= 16"}, applyIfCPUFeature = {"avx512", "true"}) // Strict alignment not possible. - @IR(failOn = {IRNode.LOAD_VECTOR, IRNode.MUL_V, IRNode.STORE_VECTOR}, + @IR(failOn = {IRNode.LOAD_VECTOR_D, IRNode.MUL_VD, IRNode.STORE_VECTOR}, applyIf = {"AlignVector", "true"}, applyIfCPUFeature = {"avx512", "true"}) // CPU: asimd -> vector_width: 32 -> elements in vector: 4 - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.MUL_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_D, "> 0", IRNode.MUL_VD, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIfAnd = {"AlignVector", "false", "MaxVectorSize", ">= 16"}, applyIfCPUFeature = {"asimd", "true"}) // Strict alignment not possible. - @IR(failOn = {IRNode.LOAD_VECTOR, IRNode.MUL_V, IRNode.STORE_VECTOR}, + @IR(failOn = {IRNode.LOAD_VECTOR_D, IRNode.MUL_VD, IRNode.STORE_VECTOR}, applyIf = {"AlignVector", "true"}, applyIfCPUFeature = {"asimd", "true"}) public static void testDoubleM63(double[] data) { @@ -10859,19 +10859,19 @@ public static void runDoubleM63() { @Test // CPU: sse4.1 -> vector_width: 16 -> elements in vector: 2 - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.MUL_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_D, "> 0", IRNode.MUL_VD, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIfAnd = {"AlignVector", "false", "MaxVectorSize", ">= 16"}, applyIfCPUFeatureAnd = {"sse4.1", "true", "avx", "false"}) // CPU: avx and avx2 -> vector_width: 32 -> elements in vector: 4 - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.MUL_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_D, "> 0", IRNode.MUL_VD, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIfAnd = {"AlignVector", "false", "MaxVectorSize", ">= 16"}, applyIfCPUFeatureAnd = {"avx", "true", "avx512", "false"}) // CPU: avx512 -> vector_width: 64 -> elements in vector: 8 - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.MUL_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_D, "> 0", IRNode.MUL_VD, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIfAnd = {"AlignVector", "false", "MaxVectorSize", ">= 16"}, applyIfCPUFeature = {"avx512", "true"}) // CPU: asimd -> vector_width: 32 -> elements in vector: 4 - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.MUL_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_D, "> 0", IRNode.MUL_VD, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIfAnd = {"AlignVector", "false", "MaxVectorSize", ">= 16"}, applyIfCPUFeature = {"asimd", "true"}) public static void testDoubleP63(double[] data) { @@ -10891,19 +10891,19 @@ public static void runDoubleP63() { @Test // CPU: sse4.1 -> vector_width: 16 -> elements in vector: 2 - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.MUL_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_D, "> 0", IRNode.MUL_VD, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIfAnd = {"AlignVector", "false", "MaxVectorSize", ">= 16"}, applyIfCPUFeatureAnd = {"sse4.1", "true", "avx", "false"}) // CPU: avx and avx2 -> vector_width: 32 -> elements in vector: 4 - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.MUL_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_D, "> 0", IRNode.MUL_VD, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIfAnd = {"AlignVector", "false", "MaxVectorSize", ">= 16"}, applyIfCPUFeatureAnd = {"avx", "true", "avx512", "false"}) // CPU: avx512 -> vector_width: 64 -> elements in vector: 8 - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.MUL_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_D, "> 0", IRNode.MUL_VD, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIfAnd = {"AlignVector", "false", "MaxVectorSize", ">= 16"}, applyIfCPUFeature = {"avx512", "true"}) // CPU: asimd -> vector_width: 32 -> elements in vector: 4 - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.MUL_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_D, "> 0", IRNode.MUL_VD, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIfAnd = {"AlignVector", "false", "MaxVectorSize", ">= 16"}, applyIfCPUFeature = {"asimd", "true"}) public static void testDoubleM64(double[] data) { @@ -10923,35 +10923,35 @@ public static void runDoubleM64() { @Test // CPU: sse4.1 -> vector_width: 16 -> elements in vector: 2 - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.MUL_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_D, "> 0", IRNode.MUL_VD, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIfAnd = {"AlignVector", "false", "MaxVectorSize", ">= 16"}, applyIfCPUFeatureAnd = {"sse4.1", "true", "avx", "false"}) // Vectorize when strict alignment guaranteed. - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.MUL_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_D, "> 0", IRNode.MUL_VD, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIfAnd = {"AlignVector", "true", "MaxVectorSize", ">= 16"}, applyIfCPUFeatureAnd = {"sse4.1", "true", "avx", "false"}) // CPU: avx and avx2 -> vector_width: 32 -> elements in vector: 4 - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.MUL_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_D, "> 0", IRNode.MUL_VD, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIfAnd = {"AlignVector", "false", "MaxVectorSize", ">= 16"}, applyIfCPUFeatureAnd = {"avx", "true", "avx512", "false"}) // Vectorize when strict alignment guaranteed. - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.MUL_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_D, "> 0", IRNode.MUL_VD, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIfAnd = {"AlignVector", "true", "MaxVectorSize", ">= 16"}, applyIfCPUFeatureAnd = {"avx", "true", "avx512", "false"}) // CPU: avx512 -> vector_width: 64 -> elements in vector: 8 - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.MUL_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_D, "> 0", IRNode.MUL_VD, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIfAnd = {"AlignVector", "false", "MaxVectorSize", ">= 16"}, applyIfCPUFeature = {"avx512", "true"}) // Vectorize when strict alignment guaranteed. - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.MUL_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_D, "> 0", IRNode.MUL_VD, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIfAnd = {"AlignVector", "true", "MaxVectorSize", ">= 16"}, applyIfCPUFeature = {"avx512", "true"}) // CPU: asimd -> vector_width: 32 -> elements in vector: 4 - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.MUL_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_D, "> 0", IRNode.MUL_VD, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIfAnd = {"AlignVector", "false", "MaxVectorSize", ">= 16"}, applyIfCPUFeature = {"asimd", "true"}) // Vectorize when strict alignment guaranteed. - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.MUL_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_D, "> 0", IRNode.MUL_VD, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIfAnd = {"AlignVector", "true", "MaxVectorSize", ">= 16"}, applyIfCPUFeature = {"asimd", "true"}) public static void testDoubleP64(double[] data) { @@ -10971,35 +10971,35 @@ public static void runDoubleP64() { @Test // CPU: sse4.1 -> vector_width: 16 -> elements in vector: 2 - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.MUL_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_D, "> 0", IRNode.MUL_VD, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIfAnd = {"AlignVector", "false", "MaxVectorSize", ">= 16"}, applyIfCPUFeatureAnd = {"sse4.1", "true", "avx", "false"}) // Strict alignment not possible. - @IR(failOn = {IRNode.LOAD_VECTOR, IRNode.MUL_V, IRNode.STORE_VECTOR}, + @IR(failOn = {IRNode.LOAD_VECTOR_D, IRNode.MUL_VD, IRNode.STORE_VECTOR}, applyIf = {"AlignVector", "true"}, applyIfCPUFeatureAnd = {"sse4.1", "true", "avx", "false"}) // CPU: avx and avx2 -> vector_width: 32 -> elements in vector: 4 - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.MUL_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_D, "> 0", IRNode.MUL_VD, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIfAnd = {"AlignVector", "false", "MaxVectorSize", ">= 16"}, applyIfCPUFeatureAnd = {"avx", "true", "avx512", "false"}) // Strict alignment not possible. - @IR(failOn = {IRNode.LOAD_VECTOR, IRNode.MUL_V, IRNode.STORE_VECTOR}, + @IR(failOn = {IRNode.LOAD_VECTOR_D, IRNode.MUL_VD, IRNode.STORE_VECTOR}, applyIf = {"AlignVector", "true"}, applyIfCPUFeatureAnd = {"avx", "true", "avx512", "false"}) // CPU: avx512 -> vector_width: 64 -> elements in vector: 8 - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.MUL_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_D, "> 0", IRNode.MUL_VD, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIfAnd = {"AlignVector", "false", "MaxVectorSize", ">= 16"}, applyIfCPUFeature = {"avx512", "true"}) // Strict alignment not possible. - @IR(failOn = {IRNode.LOAD_VECTOR, IRNode.MUL_V, IRNode.STORE_VECTOR}, + @IR(failOn = {IRNode.LOAD_VECTOR_D, IRNode.MUL_VD, IRNode.STORE_VECTOR}, applyIf = {"AlignVector", "true"}, applyIfCPUFeature = {"avx512", "true"}) // CPU: asimd -> vector_width: 32 -> elements in vector: 4 - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.MUL_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_D, "> 0", IRNode.MUL_VD, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIfAnd = {"AlignVector", "false", "MaxVectorSize", ">= 16"}, applyIfCPUFeature = {"asimd", "true"}) // Strict alignment not possible. - @IR(failOn = {IRNode.LOAD_VECTOR, IRNode.MUL_V, IRNode.STORE_VECTOR}, + @IR(failOn = {IRNode.LOAD_VECTOR_D, IRNode.MUL_VD, IRNode.STORE_VECTOR}, applyIf = {"AlignVector", "true"}, applyIfCPUFeature = {"asimd", "true"}) public static void testDoubleM65(double[] data) { @@ -11019,19 +11019,19 @@ public static void runDoubleM65() { @Test // CPU: sse4.1 -> vector_width: 16 -> elements in vector: 2 - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.MUL_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_D, "> 0", IRNode.MUL_VD, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIfAnd = {"AlignVector", "false", "MaxVectorSize", ">= 16"}, applyIfCPUFeatureAnd = {"sse4.1", "true", "avx", "false"}) // CPU: avx and avx2 -> vector_width: 32 -> elements in vector: 4 - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.MUL_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_D, "> 0", IRNode.MUL_VD, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIfAnd = {"AlignVector", "false", "MaxVectorSize", ">= 16"}, applyIfCPUFeatureAnd = {"avx", "true", "avx512", "false"}) // CPU: avx512 -> vector_width: 64 -> elements in vector: 8 - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.MUL_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_D, "> 0", IRNode.MUL_VD, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIfAnd = {"AlignVector", "false", "MaxVectorSize", ">= 16"}, applyIfCPUFeature = {"avx512", "true"}) // CPU: asimd -> vector_width: 32 -> elements in vector: 4 - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.MUL_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_D, "> 0", IRNode.MUL_VD, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIfAnd = {"AlignVector", "false", "MaxVectorSize", ">= 16"}, applyIfCPUFeature = {"asimd", "true"}) public static void testDoubleP65(double[] data) { @@ -11051,19 +11051,19 @@ public static void runDoubleP65() { @Test // CPU: sse4.1 -> vector_width: 16 -> elements in vector: 2 - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.MUL_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_D, "> 0", IRNode.MUL_VD, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIfAnd = {"AlignVector", "false", "MaxVectorSize", ">= 16"}, applyIfCPUFeatureAnd = {"sse4.1", "true", "avx", "false"}) // CPU: avx and avx2 -> vector_width: 32 -> elements in vector: 4 - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.MUL_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_D, "> 0", IRNode.MUL_VD, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIfAnd = {"AlignVector", "false", "MaxVectorSize", ">= 16"}, applyIfCPUFeatureAnd = {"avx", "true", "avx512", "false"}) // CPU: avx512 -> vector_width: 64 -> elements in vector: 8 - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.MUL_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_D, "> 0", IRNode.MUL_VD, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIfAnd = {"AlignVector", "false", "MaxVectorSize", ">= 16"}, applyIfCPUFeature = {"avx512", "true"}) // CPU: asimd -> vector_width: 32 -> elements in vector: 4 - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.MUL_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_D, "> 0", IRNode.MUL_VD, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIfAnd = {"AlignVector", "false", "MaxVectorSize", ">= 16"}, applyIfCPUFeature = {"asimd", "true"}) public static void testDoubleM128(double[] data) { @@ -11083,35 +11083,35 @@ public static void runDoubleM128() { @Test // CPU: sse4.1 -> vector_width: 16 -> elements in vector: 2 - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.MUL_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_D, "> 0", IRNode.MUL_VD, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIfAnd = {"AlignVector", "false", "MaxVectorSize", ">= 16"}, applyIfCPUFeatureAnd = {"sse4.1", "true", "avx", "false"}) // Vectorize when strict alignment guaranteed. - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.MUL_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_D, "> 0", IRNode.MUL_VD, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIfAnd = {"AlignVector", "true", "MaxVectorSize", ">= 16"}, applyIfCPUFeatureAnd = {"sse4.1", "true", "avx", "false"}) // CPU: avx and avx2 -> vector_width: 32 -> elements in vector: 4 - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.MUL_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_D, "> 0", IRNode.MUL_VD, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIfAnd = {"AlignVector", "false", "MaxVectorSize", ">= 16"}, applyIfCPUFeatureAnd = {"avx", "true", "avx512", "false"}) // Vectorize when strict alignment guaranteed. - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.MUL_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_D, "> 0", IRNode.MUL_VD, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIfAnd = {"AlignVector", "true", "MaxVectorSize", ">= 16"}, applyIfCPUFeatureAnd = {"avx", "true", "avx512", "false"}) // CPU: avx512 -> vector_width: 64 -> elements in vector: 8 - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.MUL_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_D, "> 0", IRNode.MUL_VD, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIfAnd = {"AlignVector", "false", "MaxVectorSize", ">= 16"}, applyIfCPUFeature = {"avx512", "true"}) // Vectorize when strict alignment guaranteed. - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.MUL_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_D, "> 0", IRNode.MUL_VD, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIfAnd = {"AlignVector", "true", "MaxVectorSize", ">= 16"}, applyIfCPUFeature = {"avx512", "true"}) // CPU: asimd -> vector_width: 32 -> elements in vector: 4 - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.MUL_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_D, "> 0", IRNode.MUL_VD, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIfAnd = {"AlignVector", "false", "MaxVectorSize", ">= 16"}, applyIfCPUFeature = {"asimd", "true"}) // Vectorize when strict alignment guaranteed. - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.MUL_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_D, "> 0", IRNode.MUL_VD, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIfAnd = {"AlignVector", "true", "MaxVectorSize", ">= 16"}, applyIfCPUFeature = {"asimd", "true"}) public static void testDoubleP128(double[] data) { @@ -11131,35 +11131,35 @@ public static void runDoubleP128() { @Test // CPU: sse4.1 -> vector_width: 16 -> elements in vector: 2 - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.MUL_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_D, "> 0", IRNode.MUL_VD, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIfAnd = {"AlignVector", "false", "MaxVectorSize", ">= 16"}, applyIfCPUFeatureAnd = {"sse4.1", "true", "avx", "false"}) // Strict alignment not possible. - @IR(failOn = {IRNode.LOAD_VECTOR, IRNode.MUL_V, IRNode.STORE_VECTOR}, + @IR(failOn = {IRNode.LOAD_VECTOR_D, IRNode.MUL_VD, IRNode.STORE_VECTOR}, applyIf = {"AlignVector", "true"}, applyIfCPUFeatureAnd = {"sse4.1", "true", "avx", "false"}) // CPU: avx and avx2 -> vector_width: 32 -> elements in vector: 4 - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.MUL_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_D, "> 0", IRNode.MUL_VD, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIfAnd = {"AlignVector", "false", "MaxVectorSize", ">= 16"}, applyIfCPUFeatureAnd = {"avx", "true", "avx512", "false"}) // Strict alignment not possible. - @IR(failOn = {IRNode.LOAD_VECTOR, IRNode.MUL_V, IRNode.STORE_VECTOR}, + @IR(failOn = {IRNode.LOAD_VECTOR_D, IRNode.MUL_VD, IRNode.STORE_VECTOR}, applyIf = {"AlignVector", "true"}, applyIfCPUFeatureAnd = {"avx", "true", "avx512", "false"}) // CPU: avx512 -> vector_width: 64 -> elements in vector: 8 - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.MUL_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_D, "> 0", IRNode.MUL_VD, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIfAnd = {"AlignVector", "false", "MaxVectorSize", ">= 16"}, applyIfCPUFeature = {"avx512", "true"}) // Strict alignment not possible. - @IR(failOn = {IRNode.LOAD_VECTOR, IRNode.MUL_V, IRNode.STORE_VECTOR}, + @IR(failOn = {IRNode.LOAD_VECTOR_D, IRNode.MUL_VD, IRNode.STORE_VECTOR}, applyIf = {"AlignVector", "true"}, applyIfCPUFeature = {"avx512", "true"}) // CPU: asimd -> vector_width: 32 -> elements in vector: 4 - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.MUL_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_D, "> 0", IRNode.MUL_VD, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIfAnd = {"AlignVector", "false", "MaxVectorSize", ">= 16"}, applyIfCPUFeature = {"asimd", "true"}) // Strict alignment not possible. - @IR(failOn = {IRNode.LOAD_VECTOR, IRNode.MUL_V, IRNode.STORE_VECTOR}, + @IR(failOn = {IRNode.LOAD_VECTOR_D, IRNode.MUL_VD, IRNode.STORE_VECTOR}, applyIf = {"AlignVector", "true"}, applyIfCPUFeature = {"asimd", "true"}) public static void testDoubleM129(double[] data) { @@ -11179,19 +11179,19 @@ public static void runDoubleM129() { @Test // CPU: sse4.1 -> vector_width: 16 -> elements in vector: 2 - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.MUL_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_D, "> 0", IRNode.MUL_VD, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIfAnd = {"AlignVector", "false", "MaxVectorSize", ">= 16"}, applyIfCPUFeatureAnd = {"sse4.1", "true", "avx", "false"}) // CPU: avx and avx2 -> vector_width: 32 -> elements in vector: 4 - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.MUL_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_D, "> 0", IRNode.MUL_VD, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIfAnd = {"AlignVector", "false", "MaxVectorSize", ">= 16"}, applyIfCPUFeatureAnd = {"avx", "true", "avx512", "false"}) // CPU: avx512 -> vector_width: 64 -> elements in vector: 8 - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.MUL_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_D, "> 0", IRNode.MUL_VD, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIfAnd = {"AlignVector", "false", "MaxVectorSize", ">= 16"}, applyIfCPUFeature = {"avx512", "true"}) // CPU: asimd -> vector_width: 32 -> elements in vector: 4 - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.MUL_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_D, "> 0", IRNode.MUL_VD, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIfAnd = {"AlignVector", "false", "MaxVectorSize", ">= 16"}, applyIfCPUFeature = {"asimd", "true"}) public static void testDoubleP129(double[] data) { @@ -11211,19 +11211,19 @@ public static void runDoubleP129() { @Test // CPU: sse4.1 -> vector_width: 16 -> elements in vector: 2 - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.MUL_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_D, "> 0", IRNode.MUL_VD, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIfAnd = {"AlignVector", "false", "MaxVectorSize", ">= 16"}, applyIfCPUFeatureAnd = {"sse4.1", "true", "avx", "false"}) // CPU: avx and avx2 -> vector_width: 32 -> elements in vector: 4 - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.MUL_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_D, "> 0", IRNode.MUL_VD, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIfAnd = {"AlignVector", "false", "MaxVectorSize", ">= 16"}, applyIfCPUFeatureAnd = {"avx", "true", "avx512", "false"}) // CPU: avx512 -> vector_width: 64 -> elements in vector: 8 - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.MUL_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_D, "> 0", IRNode.MUL_VD, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIfAnd = {"AlignVector", "false", "MaxVectorSize", ">= 16"}, applyIfCPUFeature = {"avx512", "true"}) // CPU: asimd -> vector_width: 32 -> elements in vector: 4 - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.MUL_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_D, "> 0", IRNode.MUL_VD, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIfAnd = {"AlignVector", "false", "MaxVectorSize", ">= 16"}, applyIfCPUFeature = {"asimd", "true"}) public static void testDoubleM192(double[] data) { @@ -11243,35 +11243,35 @@ public static void runDoubleM192() { @Test // CPU: sse4.1 -> vector_width: 16 -> elements in vector: 2 - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.MUL_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_D, "> 0", IRNode.MUL_VD, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIfAnd = {"AlignVector", "false", "MaxVectorSize", ">= 16"}, applyIfCPUFeatureAnd = {"sse4.1", "true", "avx", "false"}) // Vectorize when strict alignment guaranteed. - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.MUL_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_D, "> 0", IRNode.MUL_VD, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIfAnd = {"AlignVector", "true", "MaxVectorSize", ">= 16"}, applyIfCPUFeatureAnd = {"sse4.1", "true", "avx", "false"}) // CPU: avx and avx2 -> vector_width: 32 -> elements in vector: 4 - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.MUL_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_D, "> 0", IRNode.MUL_VD, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIfAnd = {"AlignVector", "false", "MaxVectorSize", ">= 16"}, applyIfCPUFeatureAnd = {"avx", "true", "avx512", "false"}) // Vectorize when strict alignment guaranteed. - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.MUL_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_D, "> 0", IRNode.MUL_VD, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIfAnd = {"AlignVector", "true", "MaxVectorSize", ">= 16"}, applyIfCPUFeatureAnd = {"avx", "true", "avx512", "false"}) // CPU: avx512 -> vector_width: 64 -> elements in vector: 8 - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.MUL_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_D, "> 0", IRNode.MUL_VD, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIfAnd = {"AlignVector", "false", "MaxVectorSize", ">= 16"}, applyIfCPUFeature = {"avx512", "true"}) // Vectorize when strict alignment guaranteed. - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.MUL_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_D, "> 0", IRNode.MUL_VD, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIfAnd = {"AlignVector", "true", "MaxVectorSize", ">= 16"}, applyIfCPUFeature = {"avx512", "true"}) // CPU: asimd -> vector_width: 32 -> elements in vector: 4 - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.MUL_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_D, "> 0", IRNode.MUL_VD, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIfAnd = {"AlignVector", "false", "MaxVectorSize", ">= 16"}, applyIfCPUFeature = {"asimd", "true"}) // Vectorize when strict alignment guaranteed. - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.MUL_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_D, "> 0", IRNode.MUL_VD, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIfAnd = {"AlignVector", "true", "MaxVectorSize", ">= 16"}, applyIfCPUFeature = {"asimd", "true"}) public static void testDoubleP192(double[] data) { diff --git a/test/hotspot/jtreg/compiler/loopopts/superword/TestIndependentPacksWithCyclicDependency.java b/test/hotspot/jtreg/compiler/loopopts/superword/TestIndependentPacksWithCyclicDependency.java index c384253d6e640..b27483480361e 100644 --- a/test/hotspot/jtreg/compiler/loopopts/superword/TestIndependentPacksWithCyclicDependency.java +++ b/test/hotspot/jtreg/compiler/loopopts/superword/TestIndependentPacksWithCyclicDependency.java @@ -143,7 +143,7 @@ public void runTest1() { } @Test - @IR(counts = {IRNode.ADD_VI, "> 0", IRNode.MUL_VF, "> 0", IRNode.VECTOR_CAST_F2X, "> 0", IRNode.VECTOR_CAST_I2X, "> 0"}, + @IR(counts = {IRNode.ADD_VI, "> 0", IRNode.MUL_VF, "> 0", IRNode.VECTOR_CAST_F2I, "> 0", IRNode.VECTOR_CAST_I2F, "> 0"}, applyIfCPUFeatureOr = {"avx2", "true", "asimd", "true"}) static void test1(int[] dataIa, int[] dataIb, float[] dataFa, float[] dataFb) { for (int i = 0; i < RANGE; i+=2) { diff --git a/test/hotspot/jtreg/compiler/loopopts/superword/TestUnorderedReduction.java b/test/hotspot/jtreg/compiler/loopopts/superword/TestUnorderedReduction.java index 7fb11d1f808e1..18f3b6930ea07 100644 --- a/test/hotspot/jtreg/compiler/loopopts/superword/TestUnorderedReduction.java +++ b/test/hotspot/jtreg/compiler/loopopts/superword/TestUnorderedReduction.java @@ -75,7 +75,7 @@ public void runTests() throws Exception { } @Test - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", + @IR(counts = {IRNode.LOAD_VECTOR_I, "> 0", IRNode.ADD_VI, "= 0", IRNode.ADD_REDUCTION_VI, "> 0"}, // count can be high applyIfCPUFeatureOr = {"sse4.1", "true", "asimd", "true"}) @@ -114,7 +114,7 @@ static int ref1(int[] data, int sum) { } @Test - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", + @IR(counts = {IRNode.LOAD_VECTOR_I, "> 0", IRNode.ADD_VI, "> 0", IRNode.ADD_REDUCTION_VI, "> 0", IRNode.ADD_REDUCTION_VI, "<= 2"}, // count must be low @@ -149,7 +149,7 @@ static int ref2(int[] data, int sum) { } @Test - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", + @IR(counts = {IRNode.LOAD_VECTOR_I, "> 0", IRNode.MUL_VI, "> 0", IRNode.ADD_VI, "= 0", // reduction not moved out of loop IRNode.ADD_REDUCTION_VI, "> 0",}, diff --git a/test/hotspot/jtreg/compiler/loopopts/superword/TestUnorderedReductionPartialVectorization.java b/test/hotspot/jtreg/compiler/loopopts/superword/TestUnorderedReductionPartialVectorization.java index 9d851a3688bcd..431bbe9ac4f49 100644 --- a/test/hotspot/jtreg/compiler/loopopts/superword/TestUnorderedReductionPartialVectorization.java +++ b/test/hotspot/jtreg/compiler/loopopts/superword/TestUnorderedReductionPartialVectorization.java @@ -59,8 +59,9 @@ public void runTests() throws Exception { } @Test - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", - IRNode.OR_REDUCTION_V, "> 0",}, + @IR(counts = {IRNode.LOAD_VECTOR_I, IRNode.VECTOR_SIZE + "min(max_int, max_long)", "> 0", + IRNode.VECTOR_CAST_I2L, IRNode.VECTOR_SIZE + "min(max_int, max_long)", "> 0", + IRNode.OR_REDUCTION_V, "> 0",}, applyIfCPUFeatureOr = {"avx2", "true"}) static long test1(int[] data, long sum) { for (int i = 0; i < data.length; i++) { @@ -75,7 +76,7 @@ static long test1(int[] data, long sum) { // PhaseIdealLoop::move_unordered_reduction_out_of_loop int v = data[i]; // int read data[0] = 0; // ruin the first pack - sum |= v; // long reduction + sum |= v; // long reduction (and implicit cast from int to long) } return sum; } diff --git a/test/hotspot/jtreg/compiler/vectorapi/TestMaskedMacroLogicVector.java b/test/hotspot/jtreg/compiler/vectorapi/TestMaskedMacroLogicVector.java index a213d48179991..69473ff72b3ed 100644 --- a/test/hotspot/jtreg/compiler/vectorapi/TestMaskedMacroLogicVector.java +++ b/test/hotspot/jtreg/compiler/vectorapi/TestMaskedMacroLogicVector.java @@ -280,17 +280,23 @@ public void testInt4Kernel(VectorSpecies SPECIES, int[] r, int[] a, int[] b, int } @Test - @IR(applyIfAnd = {"UseAVX", "3", "UseSSE", " > 3 "}, counts = {IRNode.AND_V, " > 0 ", IRNode.XOR_V, " > 0 "}) + @IR(applyIfAnd = {"UseAVX", "3", "UseSSE", " > 3 "}, + counts = {IRNode.AND_VI, IRNode.VECTOR_SIZE_4, " > 0 ", + IRNode.XOR_VI, IRNode.VECTOR_SIZE_4, " > 0 "}) public void testInt4_Int128(int[] r, int[] a, int[] b, int[] c, boolean [] mask) { testInt4Kernel(IntVector.SPECIES_128, r, a, b, c, mask); } @Test - @IR(applyIfAnd = {"UseAVX", "3", "UseSSE", " > 3 "}, counts = {IRNode.AND_V, " > 0 ", IRNode.XOR_V, " > 0 "}) + @IR(applyIfAnd = {"UseAVX", "3", "UseSSE", " > 3 "}, + counts = {IRNode.AND_VI, IRNode.VECTOR_SIZE_8, " > 0 ", + IRNode.XOR_VI, IRNode.VECTOR_SIZE_8, " > 0 "}) public void testInt4_Int256(int[] r, int[] a, int[] b, int[] c, boolean [] mask) { testInt4Kernel(IntVector.SPECIES_256, r, a, b, c, mask); } @Test - @IR(applyIfAnd = {"UseAVX", "3", "UseSSE", " > 3 "}, counts = {IRNode.AND_V, " > 0 ", IRNode.XOR_V, " > 0 "}) + @IR(applyIfAnd = {"UseAVX", "3", "UseSSE", " > 3 "}, + counts = {IRNode.AND_VI, IRNode.VECTOR_SIZE_16, " > 0 ", + IRNode.XOR_VI, IRNode.VECTOR_SIZE_16, " > 0 "}) public void testInt4_Int512(int[] r, int[] a, int[] b, int[] c, boolean [] mask) { testInt4Kernel(IntVector.SPECIES_512, r, a, b, c, mask); } diff --git a/test/hotspot/jtreg/compiler/vectorapi/TestReverseByteTransforms.java b/test/hotspot/jtreg/compiler/vectorapi/TestReverseByteTransforms.java index d9d282c52d469..ad5dd8aa3e7c0 100644 --- a/test/hotspot/jtreg/compiler/vectorapi/TestReverseByteTransforms.java +++ b/test/hotspot/jtreg/compiler/vectorapi/TestReverseByteTransforms.java @@ -81,7 +81,7 @@ public static void main(String args[]) { } @Test - @IR(applyIfCPUFeatureOr = {"asimd", "true", "avx2", "true"}, counts = {IRNode.REVERSE_BYTES_V , " > 0 "}) + @IR(applyIfCPUFeatureOr = {"asimd", "true", "avx2", "true"}, counts = {IRNode.REVERSE_BYTES_VL, " > 0 "}) public void test_reversebytes_long_transform1(long[] lout, long[] linp) { VectorMask mask = VectorMask.fromLong(LSPECIES, 3); for (int i = 0; i < LSPECIES.loopBound(linp.length); i+=LSPECIES.length()) { @@ -100,7 +100,7 @@ public void kernel_test_reversebytes_long_transform1() { } @Test - @IR(applyIfCPUFeatureOr = {"asimd", "true", "avx2", "true"}, counts = {IRNode.REVERSE_BYTES_V , " > 0 "}) + @IR(applyIfCPUFeatureOr = {"asimd", "true", "avx2", "true"}, counts = {IRNode.REVERSE_BYTES_VL, " > 0 "}) public void test_reversebytes_long_transform2(long[] lout, long[] linp) { VectorMask mask1 = VectorMask.fromLong(LSPECIES, 3); VectorMask mask2 = VectorMask.fromLong(LSPECIES, 3); @@ -120,7 +120,7 @@ public void kernel_test_reversebytes_long_transform2() { } @Test - @IR(applyIfCPUFeatureOr = {"asimd", "true", "avx2", "true"}, failOn = {IRNode.REVERSE_BYTES_V}) + @IR(applyIfCPUFeatureOr = {"asimd", "true", "avx2", "true"}, failOn = {IRNode.REVERSE_BYTES_VL}) public void test_reversebytes_long_transform3(long[] lout, long[] linp) { for (int i = 0; i < LSPECIES.loopBound(linp.length); i+=LSPECIES.length()) { LongVector.fromArray(LSPECIES, linp, i) @@ -138,7 +138,7 @@ public void kernel_test_reversebytes_long_transform3() { } @Test - @IR(applyIfCPUFeatureOr = {"asimd", "true", "avx2", "true"}, counts = {IRNode.REVERSE_BYTES_V , " > 0 "}) + @IR(applyIfCPUFeatureOr = {"asimd", "true", "avx2", "true"}, counts = {IRNode.REVERSE_BYTES_VI, " > 0 "}) public void test_reversebytes_int_transform1(int[] iout, int[] iinp) { VectorMask mask = VectorMask.fromLong(ISPECIES, 3); for (int i = 0; i < ISPECIES.loopBound(iinp.length); i+=ISPECIES.length()) { @@ -157,7 +157,7 @@ public void kernel_test_reversebytes_int_transform1() { } @Test - @IR(applyIfCPUFeatureOr = {"asimd", "true", "avx2", "true"}, counts = {IRNode.REVERSE_BYTES_V , " > 0 "}) + @IR(applyIfCPUFeatureOr = {"asimd", "true", "avx2", "true"}, counts = {IRNode.REVERSE_BYTES_VI, " > 0 "}) public void test_reversebytes_int_transform2(int[] iout, int[] iinp) { VectorMask mask1 = VectorMask.fromLong(ISPECIES, 3); VectorMask mask2 = VectorMask.fromLong(ISPECIES, 3); @@ -177,7 +177,7 @@ public void kernel_test_reversebytes_int_transform2() { } @Test - @IR(applyIfCPUFeatureOr = {"asimd", "true", "avx2", "true"}, failOn = {IRNode.REVERSE_BYTES_V}) + @IR(applyIfCPUFeatureOr = {"asimd", "true", "avx2", "true"}, failOn = {IRNode.REVERSE_BYTES_VI}) public void test_reversebytes_int_transform3(int[] iout, int[] iinp) { for (int i = 0; i < ISPECIES.loopBound(iinp.length); i+=ISPECIES.length()) { IntVector.fromArray(ISPECIES, iinp, i) @@ -195,7 +195,7 @@ public void kernel_test_reversebytes_int_transform3() { } @Test - @IR(applyIfCPUFeatureOr = {"asimd", "true", "avx2", "true"}, counts = {IRNode.REVERSE_BYTES_V , " > 0 "}) + @IR(applyIfCPUFeatureOr = {"asimd", "true", "avx2", "true"}, counts = {IRNode.REVERSE_BYTES_VS, " > 0 "}) public void test_reversebytes_short_transform1(short[] sout, short[] sinp) { VectorMask mask = VectorMask.fromLong(SSPECIES, 3); for (int i = 0; i < SSPECIES.loopBound(sinp.length); i+=SSPECIES.length()) { @@ -214,7 +214,7 @@ public void kernel_test_reversebytes_short_transform1() { } @Test - @IR(applyIfCPUFeatureOr = {"asimd", "true", "avx2", "true"}, counts = {IRNode.REVERSE_BYTES_V , " > 0 "}) + @IR(applyIfCPUFeatureOr = {"asimd", "true", "avx2", "true"}, counts = {IRNode.REVERSE_BYTES_VS, " > 0 "}) public void test_reversebytes_short_transform2(short[] sout, short[] sinp) { VectorMask mask1 = VectorMask.fromLong(SSPECIES, 3); VectorMask mask2 = VectorMask.fromLong(SSPECIES, 3); @@ -234,7 +234,7 @@ public void kernel_test_reversebytes_short_transform2() { } @Test - @IR(applyIfCPUFeatureOr = {"asimd", "true", "avx2", "true"}, failOn = {IRNode.REVERSE_BYTES_V}) + @IR(applyIfCPUFeatureOr = {"asimd", "true", "avx2", "true"}, failOn = {IRNode.REVERSE_BYTES_VS}) public void test_reversebytes_short_transform3(short[] sout, short[] sinp) { for (int i = 0; i < SSPECIES.loopBound(sinp.length); i+=SSPECIES.length()) { ShortVector.fromArray(SSPECIES, sinp, i) diff --git a/test/hotspot/jtreg/compiler/vectorapi/TestReverseByteTransformsSVE.java b/test/hotspot/jtreg/compiler/vectorapi/TestReverseByteTransformsSVE.java index 1774162b16368..13c5c4d6fdf28 100644 --- a/test/hotspot/jtreg/compiler/vectorapi/TestReverseByteTransformsSVE.java +++ b/test/hotspot/jtreg/compiler/vectorapi/TestReverseByteTransformsSVE.java @@ -78,7 +78,7 @@ public static void main(String args[]) { } @Test - @IR(applyIf = {"UseSVE", " > 0"}, failOn = {IRNode.REVERSE_BYTES_V}) + @IR(applyIf = {"UseSVE", " > 0"}, failOn = {IRNode.REVERSE_BYTES_VL}) public void test_reversebytes_long_transform(long[] lout, long[] linp) { VectorMask mask = VectorMask.fromLong(LSPECIES, 3); for (int i = 0; i < LSPECIES.loopBound(linp.length); i+=LSPECIES.length()) { @@ -97,7 +97,7 @@ public void kernel_test_reversebytes_long_transform() { } @Test - @IR(applyIf = {"UseSVE", " > 0"}, failOn = {IRNode.REVERSE_BYTES_V}) + @IR(applyIf = {"UseSVE", " > 0"}, failOn = {IRNode.REVERSE_BYTES_VI}) public void test_reversebytes_int_transform(int[] iout, int[] iinp) { VectorMask mask = VectorMask.fromLong(ISPECIES, 3); for (int i = 0; i < ISPECIES.loopBound(iinp.length); i+=ISPECIES.length()) { @@ -116,7 +116,7 @@ public void kernel_test_reversebytes_int_transform() { } @Test - @IR(applyIf = {"UseSVE", " > 0"}, failOn = {IRNode.REVERSE_BYTES_V}) + @IR(applyIf = {"UseSVE", " > 0"}, failOn = {IRNode.REVERSE_BYTES_VS}) public void test_reversebytes_short_transform(short[] sout, short[] sinp) { VectorMask mask = VectorMask.fromLong(SSPECIES, 3); for (int i = 0; i < SSPECIES.loopBound(sinp.length); i+=SSPECIES.length()) { diff --git a/test/hotspot/jtreg/compiler/vectorapi/TestVectorCompressExpandBits.java b/test/hotspot/jtreg/compiler/vectorapi/TestVectorCompressExpandBits.java index 3b92960c18164..f5174b7e6dcd8 100644 --- a/test/hotspot/jtreg/compiler/vectorapi/TestVectorCompressExpandBits.java +++ b/test/hotspot/jtreg/compiler/vectorapi/TestVectorCompressExpandBits.java @@ -77,7 +77,7 @@ public class TestVectorCompressExpandBits { // Test for vectorized Integer.compress operation in SVE2 @Test - @IR(counts = {IRNode.COMPRESS_BITSV, "> 0"}) + @IR(counts = {IRNode.COMPRESS_BITS_VI, "> 0"}) public static void testIntCompress() { for (int i = 0; i < LENGTH; i += I_SPECIES.length()) { IntVector av = IntVector.fromArray(I_SPECIES, ia, i); @@ -96,7 +96,7 @@ public static void testIntCompress_runner() { // Test for vectorized Integer.expand operation in SVE2 @Test - @IR(counts = {IRNode.EXPAND_BITSV, "> 0"}) + @IR(counts = {IRNode.EXPAND_BITS_VI, "> 0"}) public static void testIntExpand() { for (int i = 0; i < LENGTH; i += I_SPECIES.length()) { IntVector av = IntVector.fromArray(I_SPECIES, ia, i); @@ -115,7 +115,7 @@ public static void testIntExpand_runner() { // Test for vectorized Long.compress operation in SVE2 @Test - @IR(counts = {IRNode.COMPRESS_BITSV, "> 0"}) + @IR(counts = {IRNode.COMPRESS_BITS_VL, "> 0"}) public static void testLongCompress() { for (int i = 0; i < LENGTH; i += L_SPECIES.length()) { LongVector av = LongVector.fromArray(L_SPECIES, la, i); @@ -134,7 +134,7 @@ public static void testLongCompress_runner() { // Test for vectorized Long.expand operation in SVE2 @Test - @IR(counts = {IRNode.EXPAND_BITSV, "> 0"}) + @IR(counts = {IRNode.EXPAND_BITS_VL, "> 0"}) public static void testLongExpand() { for (int i = 0; i < LENGTH; i += L_SPECIES.length()) { LongVector av = LongVector.fromArray(L_SPECIES, la, i); diff --git a/test/hotspot/jtreg/compiler/vectorapi/VectorFPtoIntCastTest.java b/test/hotspot/jtreg/compiler/vectorapi/VectorFPtoIntCastTest.java index ddc543e4a33a6..8d5d872375ff2 100644 --- a/test/hotspot/jtreg/compiler/vectorapi/VectorFPtoIntCastTest.java +++ b/test/hotspot/jtreg/compiler/vectorapi/VectorFPtoIntCastTest.java @@ -86,7 +86,8 @@ public VectorFPtoIntCastTest() { } @Test - @IR(counts = {IRNode.VECTOR_CAST_F2X, "> 0"}, applyIfCPUFeature = {"avx512f", "true"}) + @IR(counts = {IRNode.VECTOR_CAST_F2I, IRNode.VECTOR_SIZE_16, "> 0"}, + applyIfCPUFeature = {"avx512f", "true"}) public void float2int() { var cvec = (IntVector)fvec512.convertShape(VectorOperators.F2I, ispec512, 0); cvec.intoArray(int_arr, 0); @@ -103,7 +104,8 @@ public void checkf2int(int len) { } @Test - @IR(counts = {IRNode.VECTOR_CAST_F2X, "> 0"}, applyIfCPUFeature = {"avx512dq", "true"}) + @IR(counts = {IRNode.VECTOR_CAST_F2L, IRNode.VECTOR_SIZE_8, "> 0"}, + applyIfCPUFeature = {"avx512dq", "true"}) public void float2long() { var cvec = (LongVector)fvec512.convertShape(VectorOperators.F2L, lspec512, 0); cvec.intoArray(long_arr, 0); @@ -120,7 +122,8 @@ public void checkf2long(int len) { } @Test - @IR(counts = {IRNode.VECTOR_CAST_F2X, "> 0"}, applyIfCPUFeature = {"avx512f", "true"}) + @IR(counts = {IRNode.VECTOR_CAST_F2S, IRNode.VECTOR_SIZE_16, "> 0"}, + applyIfCPUFeature = {"avx512f", "true"}) public void float2short() { var cvec = (ShortVector)fvec512.convertShape(VectorOperators.F2S, sspec256, 0); cvec.intoArray(short_arr, 0); @@ -137,7 +140,8 @@ public void checkf2short(int len) { } @Test - @IR(counts = {IRNode.VECTOR_CAST_F2X, "> 0"}, applyIfCPUFeature = {"avx512f", "true"}) + @IR(counts = {IRNode.VECTOR_CAST_F2B, IRNode.VECTOR_SIZE_16, "> 0"}, + applyIfCPUFeature = {"avx512f", "true"}) public void float2byte() { var cvec = (ByteVector)fvec512.convertShape(VectorOperators.F2B, bspec128, 0); cvec.intoArray(byte_arr, 0); @@ -154,7 +158,8 @@ public void checkf2byte(int len) { } @Test - @IR(counts = {IRNode.VECTOR_CAST_D2X, "> 0"}, applyIfCPUFeature = {"avx512f", "true"}) + @IR(counts = {IRNode.VECTOR_CAST_D2I, IRNode.VECTOR_SIZE_8, "> 0"}, + applyIfCPUFeature = {"avx512f", "true"}) public void double2int() { var cvec = (IntVector)dvec512.convertShape(VectorOperators.D2I, ispec256, 0); cvec.intoArray(int_arr, 0); @@ -171,7 +176,8 @@ public void checkd2int(int len) { } @Test - @IR(counts = {IRNode.VECTOR_CAST_D2X, "> 0"}, applyIfCPUFeature = {"avx512dq", "true"}) + @IR(counts = {IRNode.VECTOR_CAST_D2L, IRNode.VECTOR_SIZE_8, "> 0"}, + applyIfCPUFeature = {"avx512dq", "true"}) public void double2long() { var cvec = (LongVector)dvec512.convertShape(VectorOperators.D2L, lspec512, 0); cvec.intoArray(long_arr, 0); @@ -188,7 +194,8 @@ public void checkd2long(int len) { } @Test - @IR(counts = {IRNode.VECTOR_CAST_D2X, "> 0"}, applyIfCPUFeature = {"avx512f", "true"}) + @IR(counts = {IRNode.VECTOR_CAST_D2S, IRNode.VECTOR_SIZE_8, "> 0"}, + applyIfCPUFeature = {"avx512f", "true"}) public void double2short() { var cvec = (ShortVector)dvec512.convertShape(VectorOperators.D2S, sspec128, 0); cvec.intoArray(short_arr, 0); @@ -205,7 +212,8 @@ public void checkd2short(int len) { } @Test - @IR(counts = {IRNode.VECTOR_CAST_D2X, "> 0"}, applyIfCPUFeature = {"avx512f", "true"}) + @IR(counts = {IRNode.VECTOR_CAST_D2B, IRNode.VECTOR_SIZE_8, "> 0"}, + applyIfCPUFeature = {"avx512f", "true"}) public void double2byte() { var cvec = (ByteVector)dvec512.convertShape(VectorOperators.D2B, bspec64, 0); cvec.intoArray(byte_arr, 0); diff --git a/test/hotspot/jtreg/compiler/vectorapi/VectorLogicalOpIdentityTest.java b/test/hotspot/jtreg/compiler/vectorapi/VectorLogicalOpIdentityTest.java index 0ed3d5638a956..426dec6701933 100644 --- a/test/hotspot/jtreg/compiler/vectorapi/VectorLogicalOpIdentityTest.java +++ b/test/hotspot/jtreg/compiler/vectorapi/VectorLogicalOpIdentityTest.java @@ -104,7 +104,7 @@ private static long and(long a, long b) { @Test @Warmup(10000) - @IR(failOn = IRNode.AND_V, counts = {IRNode.LOAD_VECTOR, ">=1"}) + @IR(failOn = IRNode.AND_VB, counts = {IRNode.LOAD_VECTOR_B, ">=1"}) public static void testAndMinusOne() { ByteVector av = ByteVector.fromArray(B_SPECIES, ba, 0); av.and((byte) -1).intoArray(br, 0); @@ -117,7 +117,7 @@ public static void testAndMinusOne() { @Test @Warmup(10000) - @IR(failOn = IRNode.AND_V, counts = {IRNode.STORE_VECTOR, ">=1"}) + @IR(failOn = IRNode.AND_VS, counts = {IRNode.STORE_VECTOR, ">=1"}) public static void testAndZero() { ShortVector av = ShortVector.fromArray(S_SPECIES, sa, 0); av.and((short) 0).intoArray(sr, 0); @@ -130,7 +130,7 @@ public static void testAndZero() { @Test @Warmup(10000) - @IR(failOn = IRNode.AND_V, counts = {IRNode.LOAD_VECTOR, ">=1"}) + @IR(failOn = IRNode.AND_VI, counts = {IRNode.LOAD_VECTOR_I, ">=1"}) public static void testAndSame() { IntVector av = IntVector.fromArray(I_SPECIES, ia, 0); av.and(av).intoArray(ir, 0); @@ -143,7 +143,7 @@ public static void testAndSame() { @Test @Warmup(10000) - @IR(failOn = IRNode.AND_V, counts = {IRNode.LOAD_VECTOR, ">=1"}) + @IR(failOn = IRNode.AND_VL, counts = {IRNode.LOAD_VECTOR_L, ">=1"}) public static void testMaskedAndMinusOne1() { VectorMask mask = VectorMask.fromArray(L_SPECIES, m, 0); LongVector av = LongVector.fromArray(L_SPECIES, la, 0); @@ -163,8 +163,8 @@ public static void testMaskedAndMinusOne1() { // Masked AndV in this test should not be optimized out on SVE. @Test @Warmup(10000) - @IR(counts = {IRNode.LOAD_VECTOR, ">=1"}) - @IR(failOn = IRNode.AND_V, applyIfCPUFeatureAnd = {"asimd", "true", "sve", "false"}) + @IR(counts = {IRNode.LOAD_VECTOR_B, ">=1"}) + @IR(failOn = IRNode.AND_VB, applyIfCPUFeatureAnd = {"asimd", "true", "sve", "false"}) public static void testMaskedAndMinusOne2() { VectorMask mask = VectorMask.fromArray(B_SPECIES, m, 0); ByteVector av = ByteVector.fromArray(B_SPECIES, ba, 0); @@ -185,7 +185,7 @@ public static void testMaskedAndMinusOne2() { @Test @Warmup(10000) @IR(counts = {IRNode.STORE_VECTOR, ">=1"}) - @IR(failOn = IRNode.AND_V, applyIfCPUFeatureAnd = {"asimd", "true", "sve", "false"}) + @IR(failOn = IRNode.AND_VS, applyIfCPUFeatureAnd = {"asimd", "true", "sve", "false"}) public static void testMaskedAndZero1() { VectorMask mask = VectorMask.fromArray(S_SPECIES, m, 0); ShortVector av = ShortVector.fromArray(S_SPECIES, sa, 0); @@ -204,7 +204,7 @@ public static void testMaskedAndZero1() { @Test @Warmup(10000) - @IR(failOn = IRNode.AND_V, counts = {IRNode.STORE_VECTOR, ">=1"}) + @IR(failOn = IRNode.AND_VI, counts = {IRNode.STORE_VECTOR, ">=1"}) public static void testMaskedAndZero2() { VectorMask mask = VectorMask.fromArray(I_SPECIES, m, 0); IntVector av = IntVector.fromArray(I_SPECIES, ia, 0); @@ -223,7 +223,7 @@ public static void testMaskedAndZero2() { @Test @Warmup(10000) - @IR(failOn = IRNode.AND_V, counts = {IRNode.LOAD_VECTOR, ">=1"}) + @IR(failOn = IRNode.AND_VL, counts = {IRNode.LOAD_VECTOR_L, ">=1"}) public static void testMaskedAndSame() { VectorMask mask = VectorMask.fromArray(L_SPECIES, m, 0); LongVector av = LongVector.fromArray(L_SPECIES, la, 0); @@ -242,7 +242,7 @@ public static void testMaskedAndSame() { // Transform AndV(AndV(a, b), b) ==> AndV(a, b) @Test @Warmup(10000) - @IR(counts = {IRNode.AND_V, "1"}) + @IR(counts = {IRNode.AND_VI, "1"}) public static void testAndSameValue1() { IntVector av = IntVector.fromArray(I_SPECIES, ia, 0); IntVector bv = IntVector.fromArray(I_SPECIES, ib, 0); @@ -257,7 +257,7 @@ public static void testAndSameValue1() { // Transform AndV(AndV(a, b), a) ==> AndV(a, b) @Test @Warmup(10000) - @IR(counts = {IRNode.AND_V, "1"}) + @IR(counts = {IRNode.AND_VL, "1"}) public static void testAndSameValue2() { LongVector av = LongVector.fromArray(L_SPECIES, la, 0); LongVector bv = LongVector.fromArray(L_SPECIES, lb, 0); @@ -272,7 +272,7 @@ public static void testAndSameValue2() { // Transform AndV(b, AndV(a, b)) ==> AndV(a, b) @Test @Warmup(10000) - @IR(counts = {IRNode.AND_V, "1"}) + @IR(counts = {IRNode.AND_VI, "1"}) public static void testAndSameValue3() { IntVector av = IntVector.fromArray(I_SPECIES, ia, 0); IntVector bv = IntVector.fromArray(I_SPECIES, ib, 0); @@ -287,7 +287,7 @@ public static void testAndSameValue3() { // Transform AndV(a, AndV(a, b)) ==> AndV(a, b) @Test @Warmup(10000) - @IR(counts = {IRNode.AND_V, "1"}) + @IR(counts = {IRNode.AND_VL, "1"}) public static void testAndSameValue4() { LongVector av = LongVector.fromArray(L_SPECIES, la, 0); LongVector bv = LongVector.fromArray(L_SPECIES, lb, 0); @@ -302,7 +302,7 @@ public static void testAndSameValue4() { // Transform AndV(AndV(a, b, m), b, m) ==> AndV(a, b, m) @Test @Warmup(10000) - @IR(counts = {IRNode.AND_V, "1"}, applyIfCPUFeatureOr = {"sve", "true", "avx512", "true"}) + @IR(counts = {IRNode.AND_VI, "1"}, applyIfCPUFeatureOr = {"sve", "true", "avx512", "true"}) public static void testAndMaskSameValue1() { VectorMask mask = VectorMask.fromArray(I_SPECIES, m, 0); IntVector av = IntVector.fromArray(I_SPECIES, ia, 0); @@ -323,7 +323,7 @@ public static void testAndMaskSameValue1() { // Transform AndV(AndV(a, b, m), a, m) ==> AndV(a, b, m) @Test @Warmup(10000) - @IR(counts = {IRNode.AND_V, "1"}, applyIfCPUFeatureOr = {"sve", "true", "avx512", "true"}) + @IR(counts = {IRNode.AND_VL, "1"}, applyIfCPUFeatureOr = {"sve", "true", "avx512", "true"}) public static void testAndMaskSameValue2() { VectorMask mask = VectorMask.fromArray(L_SPECIES, m, 0); LongVector av = LongVector.fromArray(L_SPECIES, la, 0); @@ -344,7 +344,7 @@ public static void testAndMaskSameValue2() { // Transform AndV(a, AndV(a, b, m), m) ==> AndV(a, b, m) @Test @Warmup(10000) - @IR(counts = {IRNode.AND_V, "1"}, applyIfCPUFeatureOr = {"sve", "true", "avx512", "true"}) + @IR(counts = {IRNode.AND_VI, "1"}, applyIfCPUFeatureOr = {"sve", "true", "avx512", "true"}) public static void testAndMaskSameValue3() { VectorMask mask = VectorMask.fromArray(I_SPECIES, m, 0); IntVector av = IntVector.fromArray(I_SPECIES, ia, 0); @@ -368,7 +368,7 @@ private static long or(long a, long b) { @Test @Warmup(10000) - @IR(failOn = IRNode.OR_V, counts = {IRNode.STORE_VECTOR, ">=1"}) + @IR(failOn = IRNode.OR_VB, counts = {IRNode.STORE_VECTOR, ">=1"}) public static void testOrMinusOne() { ByteVector av = ByteVector.fromArray(B_SPECIES, ba, 0); av.or((byte) -1).intoArray(br, 0); @@ -381,7 +381,7 @@ public static void testOrMinusOne() { @Test @Warmup(10000) - @IR(failOn = IRNode.OR_V, counts = {IRNode.LOAD_VECTOR, ">=1"}) + @IR(failOn = IRNode.OR_VS, counts = {IRNode.LOAD_VECTOR_S, ">=1"}) public static void testOrZero() { ShortVector av = ShortVector.fromArray(S_SPECIES, sa, 0); av.or((short) 0).intoArray(sr, 0); @@ -394,7 +394,7 @@ public static void testOrZero() { @Test @Warmup(10000) - @IR(failOn = IRNode.OR_V, counts = {IRNode.LOAD_VECTOR, ">=1"}) + @IR(failOn = IRNode.OR_VI, counts = {IRNode.LOAD_VECTOR_I, ">=1"}) public static void testOrSame() { IntVector av = IntVector.fromArray(I_SPECIES, ia, 0); av.or(av).intoArray(ir, 0); @@ -409,7 +409,7 @@ public static void testOrSame() { @Test @Warmup(10000) @IR(counts = {IRNode.STORE_VECTOR, ">=1"}) - @IR(failOn = IRNode.OR_V, applyIfCPUFeatureAnd = {"asimd", "true", "sve", "false"}) + @IR(failOn = IRNode.OR_VB, applyIfCPUFeatureAnd = {"asimd", "true", "sve", "false"}) public static void testMaskedOrMinusOne1() { VectorMask mask = VectorMask.fromArray(B_SPECIES, m, 0); ByteVector av = ByteVector.fromArray(B_SPECIES, ba, 0); @@ -428,7 +428,7 @@ public static void testMaskedOrMinusOne1() { @Test @Warmup(10000) - @IR(failOn = IRNode.OR_V, counts = {IRNode.STORE_VECTOR, ">=1"}) + @IR(failOn = IRNode.OR_VB, counts = {IRNode.STORE_VECTOR, ">=1"}) public static void testMaskedOrMinusOne2() { VectorMask mask = VectorMask.fromArray(B_SPECIES, m, 0); ByteVector av = ByteVector.fromArray(B_SPECIES, ba, 0); @@ -447,7 +447,7 @@ public static void testMaskedOrMinusOne2() { @Test @Warmup(10000) - @IR(failOn = IRNode.OR_V, counts = {IRNode.LOAD_VECTOR, ">=1"}) + @IR(failOn = IRNode.OR_VS, counts = {IRNode.LOAD_VECTOR_S, ">=1"}) public static void testMaskedOrZero1() { VectorMask mask = VectorMask.fromArray(S_SPECIES, m, 0); ShortVector av = ShortVector.fromArray(S_SPECIES, sa, 0); @@ -467,8 +467,8 @@ public static void testMaskedOrZero1() { // Masked OrV in this test should not be optimized out on SVE. @Test @Warmup(10000) - @IR(counts = {IRNode.LOAD_VECTOR, ">=1"}) - @IR(failOn = IRNode.OR_V, applyIfCPUFeatureAnd = {"asimd", "true", "sve", "false"}) + @IR(counts = {IRNode.LOAD_VECTOR_B, ">=1"}) + @IR(failOn = IRNode.OR_VB, applyIfCPUFeatureAnd = {"asimd", "true", "sve", "false"}) public static void testMaskedOrZero2() { VectorMask mask = VectorMask.fromArray(B_SPECIES, m, 0); ByteVector av = ByteVector.fromArray(B_SPECIES, ba, 0); @@ -487,7 +487,7 @@ public static void testMaskedOrZero2() { @Test @Warmup(10000) - @IR(failOn = IRNode.OR_V, counts = {IRNode.LOAD_VECTOR, ">=1"}) + @IR(failOn = IRNode.OR_VL, counts = {IRNode.LOAD_VECTOR_L, ">=1"}) public static void testMaskedOrSame() { VectorMask mask = VectorMask.fromArray(L_SPECIES, m, 0); LongVector av = LongVector.fromArray(L_SPECIES, la, 0); @@ -506,7 +506,7 @@ public static void testMaskedOrSame() { // Transform OrV(OrV(a, b), b) ==> OrV(a, b) @Test @Warmup(10000) - @IR(counts = {IRNode.OR_V, "1"}) + @IR(counts = {IRNode.OR_VI, "1"}) public static void testOrSameValue1() { IntVector av = IntVector.fromArray(I_SPECIES, ia, 0); IntVector bv = IntVector.fromArray(I_SPECIES, ib, 0); @@ -521,7 +521,7 @@ public static void testOrSameValue1() { // Transform OrV(OrV(a, b), a) ==> OrV(a, b) @Test @Warmup(10000) - @IR(counts = {IRNode.OR_V, "1"}) + @IR(counts = {IRNode.OR_VL, "1"}) public static void testOrSameValue2() { LongVector av = LongVector.fromArray(L_SPECIES, la, 0); LongVector bv = LongVector.fromArray(L_SPECIES, lb, 0); @@ -536,7 +536,7 @@ public static void testOrSameValue2() { // Transform OrV(b, OrV(a, b)) ==> OrV(a, b) @Test @Warmup(10000) - @IR(counts = {IRNode.OR_V, "1"}) + @IR(counts = {IRNode.OR_VI, "1"}) public static void testOrSameValue3() { IntVector av = IntVector.fromArray(I_SPECIES, ia, 0); IntVector bv = IntVector.fromArray(I_SPECIES, ib, 0); @@ -551,7 +551,7 @@ public static void testOrSameValue3() { // Transform OrV(a, OrV(a, b)) ==> OrV(a, b) @Test @Warmup(10000) - @IR(counts = {IRNode.OR_V, "1"}) + @IR(counts = {IRNode.OR_VL, "1"}) public static void testOrSameValue4() { LongVector av = LongVector.fromArray(L_SPECIES, la, 0); LongVector bv = LongVector.fromArray(L_SPECIES, lb, 0); @@ -566,7 +566,7 @@ public static void testOrSameValue4() { // Transform OrV(OrV(a, b, m), b, m) ==> OrV(a, b, m) @Test @Warmup(10000) - @IR(counts = {IRNode.OR_V, "1"}, applyIfCPUFeatureOr = {"sve", "true", "avx512", "true"}) + @IR(counts = {IRNode.OR_VI, "1"}, applyIfCPUFeatureOr = {"sve", "true", "avx512", "true"}) public static void testOrMaskSameValue1() { VectorMask mask = VectorMask.fromArray(I_SPECIES, m, 0); IntVector av = IntVector.fromArray(I_SPECIES, ia, 0); @@ -587,7 +587,7 @@ public static void testOrMaskSameValue1() { // Transform OrV(OrV(a, b, m), a, m) ==> OrV(a, b, m) @Test @Warmup(10000) - @IR(counts = {IRNode.OR_V, "1"}, applyIfCPUFeatureOr = {"sve", "true", "avx512", "true"}) + @IR(counts = {IRNode.OR_VL, "1"}, applyIfCPUFeatureOr = {"sve", "true", "avx512", "true"}) public static void testOrMaskSameValue2() { VectorMask mask = VectorMask.fromArray(L_SPECIES, m, 0); LongVector av = LongVector.fromArray(L_SPECIES, la, 0); @@ -608,7 +608,7 @@ public static void testOrMaskSameValue2() { // Transform OrV(a, OrV(a, b, m), m) ==> OrV(a, b, m) @Test @Warmup(10000) - @IR(counts = {IRNode.OR_V, "1"}, applyIfCPUFeatureOr = {"sve", "true", "avx512", "true"}) + @IR(counts = {IRNode.OR_VI, "1"}, applyIfCPUFeatureOr = {"sve", "true", "avx512", "true"}) public static void testOrMaskSameValue3() { VectorMask mask = VectorMask.fromArray(I_SPECIES, m, 0); IntVector av = IntVector.fromArray(I_SPECIES, ia, 0); @@ -632,7 +632,7 @@ private static long xor(long a, long b) { @Test @Warmup(10000) - @IR(failOn = IRNode.XOR_V, counts = {IRNode.STORE_VECTOR, ">=1"}) + @IR(failOn = IRNode.XOR_VB, counts = {IRNode.STORE_VECTOR, ">=1"}) public static void testXorSame() { ByteVector av = ByteVector.fromArray(B_SPECIES, ba, 0); av.lanewise(VectorOperators.XOR, av).intoArray(br, 0); @@ -647,7 +647,7 @@ public static void testXorSame() { @Test @Warmup(10000) @IR(counts = {IRNode.STORE_VECTOR, ">=1"}) - @IR(failOn = IRNode.XOR_V, applyIfCPUFeatureAnd = {"asimd", "true", "sve", "false"}) + @IR(failOn = IRNode.XOR_VS, applyIfCPUFeatureAnd = {"asimd", "true", "sve", "false"}) public static void testMaskedXorSame() { VectorMask mask = VectorMask.fromArray(S_SPECIES, m, 0); ShortVector av = ShortVector.fromArray(S_SPECIES, sa, 0); @@ -666,7 +666,7 @@ public static void testMaskedXorSame() { // Following are the vector mask logic operations tests @Test @Warmup(10000) - @IR(failOn = {IRNode.AND_V, IRNode.AND_V_MASK}, counts = {IRNode.STORE_VECTOR, ">=1"}) + @IR(failOn = {IRNode.AND_VI, IRNode.AND_V_MASK}, counts = {IRNode.STORE_VECTOR, ">=1"}) public static void testMaskAndMinusOne() { VectorMask ma = VectorMask.fromArray(I_SPECIES, m, 0); VectorMask mb = I_SPECIES.maskAll(true); @@ -680,7 +680,7 @@ public static void testMaskAndMinusOne() { @Test @Warmup(10000) - @IR(failOn = {IRNode.AND_V, IRNode.AND_V_MASK}, counts = {IRNode.STORE_VECTOR, ">=1"}) + @IR(failOn = {IRNode.AND_VS, IRNode.AND_V_MASK}, counts = {IRNode.STORE_VECTOR, ">=1"}) public static void testMaskAndZero() { VectorMask ma = VectorMask.fromArray(S_SPECIES, m, 0); VectorMask mb = S_SPECIES.maskAll(false); @@ -694,7 +694,7 @@ public static void testMaskAndZero() { @Test @Warmup(10000) - @IR(failOn = {IRNode.AND_V, IRNode.AND_V_MASK}, counts = {IRNode.STORE_VECTOR, ">=1"}) + @IR(failOn = {IRNode.AND_VB, IRNode.AND_V_MASK}, counts = {IRNode.STORE_VECTOR, ">=1"}) public static void testMaskAndSame() { VectorMask ma = VectorMask.fromArray(B_SPECIES, m, 0); ma.and(ma).intoArray(mr, 0); @@ -707,7 +707,7 @@ public static void testMaskAndSame() { @Test @Warmup(10000) - @IR(failOn = {IRNode.OR_V, IRNode.OR_V_MASK}, counts = {IRNode.STORE_VECTOR, ">=1"}) + @IR(failOn = {IRNode.OR_VS, IRNode.OR_V_MASK}, counts = {IRNode.STORE_VECTOR, ">=1"}) public static void testMaskOrMinusOne() { VectorMask ma = VectorMask.fromArray(S_SPECIES, m, 0); VectorMask mb = S_SPECIES.maskAll(true); @@ -721,7 +721,7 @@ public static void testMaskOrMinusOne() { @Test @Warmup(10000) - @IR(failOn = {IRNode.OR_V, IRNode.OR_V_MASK}, counts = {IRNode.STORE_VECTOR, ">=1"}) + @IR(failOn = {IRNode.OR_VI, IRNode.OR_V_MASK}, counts = {IRNode.STORE_VECTOR, ">=1"}) public static void testMaskOrZero() { VectorMask ma = VectorMask.fromArray(I_SPECIES, m, 0); VectorMask mb = I_SPECIES.maskAll(false); @@ -735,7 +735,7 @@ public static void testMaskOrZero() { @Test @Warmup(10000) - @IR(failOn = {IRNode.OR_V, IRNode.OR_V_MASK}, counts = {IRNode.STORE_VECTOR, ">=1"}) + @IR(failOn = {IRNode.OR_VB, IRNode.OR_V_MASK}, counts = {IRNode.STORE_VECTOR, ">=1"}) public static void testMaskOrSame() { VectorMask ma = VectorMask.fromArray(B_SPECIES, m, 0); ma.or(ma).intoArray(mr, 0); @@ -748,7 +748,7 @@ public static void testMaskOrSame() { @Test @Warmup(10000) - @IR(failOn = {IRNode.XOR_V, IRNode.XOR_V_MASK}, counts = {IRNode.STORE_VECTOR, ">=1"}) + @IR(failOn = {IRNode.XOR_VI, IRNode.XOR_V_MASK}, counts = {IRNode.STORE_VECTOR, ">=1"}) public static void testMaskXorSame() { VectorMask ma = I_SPECIES.maskAll(true); ma.not().intoArray(mr, 0); diff --git a/test/hotspot/jtreg/compiler/vectorapi/VectorReverseBytesTest.java b/test/hotspot/jtreg/compiler/vectorapi/VectorReverseBytesTest.java index 7205c262280d6..154567922bd03 100644 --- a/test/hotspot/jtreg/compiler/vectorapi/VectorReverseBytesTest.java +++ b/test/hotspot/jtreg/compiler/vectorapi/VectorReverseBytesTest.java @@ -70,7 +70,7 @@ public class VectorReverseBytesTest { } @Test - @IR(failOn = IRNode.REVERSE_BYTES_V) + @IR(failOn = IRNode.REVERSE_BYTES_VB) public static void testReverseBytesV() { for (int i = 0; i < LENGTH; i += B_SPECIES.length()) { ByteVector v = ByteVector.fromArray(B_SPECIES, input, i); @@ -84,8 +84,8 @@ public static void testReverseBytesV() { } @Test - @IR(failOn = IRNode.REVERSE_BYTES_V) - @IR(failOn = IRNode.VECTOR_BLEND) + @IR(failOn = IRNode.REVERSE_BYTES_VB) + @IR(failOn = IRNode.VECTOR_BLEND_B) public static void testReverseBytesVMasked() { VectorMask mask = VectorMask.fromArray(B_SPECIES, m, 0); for (int i = 0; i < LENGTH; i += B_SPECIES.length()) { diff --git a/test/hotspot/jtreg/compiler/vectorapi/reshape/tests/TestVectorCast.java b/test/hotspot/jtreg/compiler/vectorapi/reshape/tests/TestVectorCast.java index 47dcbab8f71f6..63058e6d45350 100644 --- a/test/hotspot/jtreg/compiler/vectorapi/reshape/tests/TestVectorCast.java +++ b/test/hotspot/jtreg/compiler/vectorapi/reshape/tests/TestVectorCast.java @@ -26,6 +26,7 @@ import compiler.lib.ir_framework.IR; import compiler.lib.ir_framework.Run; import compiler.lib.ir_framework.Test; +import compiler.lib.ir_framework.IRNode; import static compiler.vectorapi.reshape.utils.VectorReshapeHelper.*; import static jdk.incubator.vector.VectorOperators.*; @@ -44,7 +45,7 @@ */ public class TestVectorCast { @Test - @IR(counts = {B2X_NODE, "1"}) + @IR(counts = {IRNode.VECTOR_CAST_B2S, IRNode.VECTOR_SIZE_4, "1"}) public static void testB64toS64(byte[] input, short[] output) { vectorCast(B2S, BSPEC64, SSPEC64, input, output); } @@ -55,7 +56,7 @@ public static void runB64toS64() throws Throwable { } @Test - @IR(counts = {B2X_NODE, "1"}) + @IR(counts = {IRNode.VECTOR_CAST_B2S, IRNode.VECTOR_SIZE_8, "1"}) public static void testB64toS128(byte[] input, short[] output) { vectorCast(B2S, BSPEC64, SSPEC128, input, output); } @@ -66,7 +67,7 @@ public static void runB64toS128() throws Throwable { } @Test - @IR(counts = {B2X_NODE, "1"}) + @IR(counts = {IRNode.VECTOR_CAST_B2S, IRNode.VECTOR_SIZE_16, "1"}) public static void testB128toS256(byte[] input, short[] output) { vectorCast(B2S, BSPEC128, SSPEC256, input, output); } @@ -77,7 +78,7 @@ public static void runB128toS256() throws Throwable { } @Test - @IR(counts = {B2X_NODE, "1"}) + @IR(counts = {IRNode.VECTOR_CAST_B2S, IRNode.VECTOR_SIZE_32, "1"}) public static void testB256toS512(byte[] input, short[] output) { vectorCast(B2S, BSPEC256, SSPEC512, input, output); } @@ -88,7 +89,7 @@ public static void runB256toS512() throws Throwable { } @Test - @IR(counts = {B2X_NODE, "1"}) + @IR(counts = {IRNode.VECTOR_CAST_B2I, IRNode.VECTOR_SIZE_2, "1"}) public static void testB64toI64(byte[] input, int[] output) { vectorCast(B2I, BSPEC64, ISPEC64, input, output); } @@ -99,7 +100,7 @@ public static void runB64toI64() throws Throwable { } @Test - @IR(counts = {B2X_NODE, "1"}) + @IR(counts = {IRNode.VECTOR_CAST_B2I, IRNode.VECTOR_SIZE_4, "1"}) public static void testB64toI128(byte[] input, int[] output) { vectorCast(B2I, BSPEC64, ISPEC128, input, output); } @@ -110,7 +111,7 @@ public static void runB64toI128() throws Throwable { } @Test - @IR(counts = {B2X_NODE, "1"}) + @IR(counts = {IRNode.VECTOR_CAST_B2I, IRNode.VECTOR_SIZE_8, "1"}) public static void testB64toI256(byte[] input, int[] output) { vectorCast(B2I, BSPEC64, ISPEC256, input, output); } @@ -121,7 +122,7 @@ public static void runB64toI256() throws Throwable { } @Test - @IR(counts = {B2X_NODE, "1"}) + @IR(counts = {IRNode.VECTOR_CAST_B2I, IRNode.VECTOR_SIZE_16, "1"}) public static void testB128toI512(byte[] input, int[] output) { vectorCast(B2I, BSPEC128, ISPEC512, input, output); } @@ -132,7 +133,7 @@ public static void runB128toI512() throws Throwable { } @Test - @IR(counts = {B2X_NODE, "1"}) + @IR(counts = {IRNode.VECTOR_CAST_B2L, IRNode.VECTOR_SIZE_2, "1"}) public static void testB64toL64(byte[] input, long[] output) { vectorCast(B2L, BSPEC64, LSPEC64, input, output); } @@ -143,7 +144,7 @@ public static void runB64toL64() throws Throwable { } @Test - @IR(counts = {B2X_NODE, "1"}) + @IR(counts = {IRNode.VECTOR_CAST_B2L, IRNode.VECTOR_SIZE_2, "1"}) public static void testB64toL128(byte[] input, long[] output) { vectorCast(B2L, BSPEC64, LSPEC128, input, output); } @@ -154,7 +155,7 @@ public static void runB64toL128() throws Throwable { } @Test - @IR(counts = {B2X_NODE, "1"}) + @IR(counts = {IRNode.VECTOR_CAST_B2L, IRNode.VECTOR_SIZE_4, "1"}) public static void testB64toL256(byte[] input, long[] output) { vectorCast(B2L, BSPEC64, LSPEC256, input, output); } @@ -165,7 +166,7 @@ public static void runB64toL256() throws Throwable { } @Test - @IR(counts = {B2X_NODE, "1"}) + @IR(counts = {IRNode.VECTOR_CAST_B2L, IRNode.VECTOR_SIZE_8, "1"}) public static void testB64toL512(byte[] input, long[] output) { vectorCast(B2L, BSPEC64, LSPEC512, input, output); } @@ -176,7 +177,7 @@ public static void runB64toL512() throws Throwable { } @Test - @IR(counts = {B2X_NODE, "1"}) + @IR(counts = {IRNode.VECTOR_CAST_B2F, IRNode.VECTOR_SIZE_2, "1"}) public static void testB64toF64(byte[] input, float[] output) { vectorCast(B2F, BSPEC64, FSPEC64, input, output); } @@ -187,7 +188,7 @@ public static void runB64toF64() throws Throwable { } @Test - @IR(counts = {B2X_NODE, "1"}) + @IR(counts = {IRNode.VECTOR_CAST_B2F, IRNode.VECTOR_SIZE_4, "1"}) public static void testB64toF128(byte[] input, float[] output) { vectorCast(B2F, BSPEC64, FSPEC128, input, output); } @@ -198,7 +199,7 @@ public static void runB64toF128() throws Throwable { } @Test - @IR(counts = {B2X_NODE, "1"}) + @IR(counts = {IRNode.VECTOR_CAST_B2F, IRNode.VECTOR_SIZE_8, "1"}) public static void testB64toF256(byte[] input, float[] output) { vectorCast(B2F, BSPEC64, FSPEC256, input, output); } @@ -209,7 +210,7 @@ public static void runB64toF256() throws Throwable { } @Test - @IR(counts = {B2X_NODE, "1"}) + @IR(counts = {IRNode.VECTOR_CAST_B2F, IRNode.VECTOR_SIZE_16, "1"}) public static void testB128toF512(byte[] input, float[] output) { vectorCast(B2F, BSPEC128, FSPEC512, input, output); } @@ -220,7 +221,7 @@ public static void runB128toF512() throws Throwable { } @Test - @IR(counts = {B2X_NODE, "1"}) + @IR(counts = {IRNode.VECTOR_CAST_B2D, IRNode.VECTOR_SIZE_2, "1"}) public static void testB64toD64(byte[] input, double[] output) { vectorCast(B2D, BSPEC64, DSPEC64, input, output); } @@ -231,7 +232,7 @@ public static void runB64toD64() throws Throwable { } @Test - @IR(counts = {B2X_NODE, "1"}) + @IR(counts = {IRNode.VECTOR_CAST_B2D, IRNode.VECTOR_SIZE_2, "1"}) public static void testB64toD128(byte[] input, double[] output) { vectorCast(B2D, BSPEC64, DSPEC128, input, output); } @@ -242,7 +243,7 @@ public static void runB64toD128() throws Throwable { } @Test - @IR(counts = {B2X_NODE, "1"}) + @IR(counts = {IRNode.VECTOR_CAST_B2D, IRNode.VECTOR_SIZE_4, "1"}) public static void testB64toD256(byte[] input, double[] output) { vectorCast(B2D, BSPEC64, DSPEC256, input, output); } @@ -253,7 +254,7 @@ public static void runB64toD256() throws Throwable { } @Test - @IR(counts = {B2X_NODE, "1"}) + @IR(counts = {IRNode.VECTOR_CAST_B2D, IRNode.VECTOR_SIZE_8, "1"}) public static void testB64toD512(byte[] input, double[] output) { vectorCast(B2D, BSPEC64, DSPEC512, input, output); } @@ -264,7 +265,7 @@ public static void runB64toD512() throws Throwable { } @Test - @IR(counts = {S2X_NODE, "1"}) + @IR(counts = {IRNode.VECTOR_CAST_S2B, IRNode.VECTOR_SIZE_4, "1"}) public static void testS64toB64(short[] input, byte[] output) { vectorCast(S2B, SSPEC64, BSPEC64, input, output); } @@ -275,7 +276,7 @@ public static void runS64toB64() throws Throwable { } @Test - @IR(counts = {S2X_NODE, "1"}) + @IR(counts = {IRNode.VECTOR_CAST_S2B, IRNode.VECTOR_SIZE_8, "1"}) public static void testS128toB64(short[] input, byte[] output) { vectorCast(S2B, SSPEC128, BSPEC64, input, output); } @@ -286,7 +287,7 @@ public static void runS128toB64() throws Throwable { } @Test - @IR(counts = {S2X_NODE, "1"}) + @IR(counts = {IRNode.VECTOR_CAST_S2B, IRNode.VECTOR_SIZE_16, "1"}) public static void testS256toB128(short[] input, byte[] output) { vectorCast(S2B, SSPEC256, BSPEC128, input, output); } @@ -297,7 +298,7 @@ public static void runS256toB128() throws Throwable { } @Test - @IR(counts = {S2X_NODE, "1"}) + @IR(counts = {IRNode.VECTOR_CAST_S2B, IRNode.VECTOR_SIZE_32, "1"}) public static void testS512toB256(short[] input, byte[] output) { vectorCast(S2B, SSPEC512, BSPEC256, input, output); } @@ -308,7 +309,7 @@ public static void runS512toB256() throws Throwable { } @Test - @IR(counts = {S2X_NODE, "1"}) + @IR(counts = {IRNode.VECTOR_CAST_S2I, IRNode.VECTOR_SIZE_2, "1"}) public static void testS64toI64(short[] input, int[] output) { vectorCast(S2I, SSPEC64, ISPEC64, input, output); } @@ -319,7 +320,7 @@ public static void runS64toI64() throws Throwable { } @Test - @IR(counts = {S2X_NODE, "1"}) + @IR(counts = {IRNode.VECTOR_CAST_S2I, IRNode.VECTOR_SIZE_4, "1"}) public static void testS64toI128(short[] input, int[] output) { vectorCast(S2I, SSPEC64, ISPEC128, input, output); } @@ -330,7 +331,7 @@ public static void runS64toI128() throws Throwable { } @Test - @IR(counts = {S2X_NODE, "1"}) + @IR(counts = {IRNode.VECTOR_CAST_S2I, IRNode.VECTOR_SIZE_8, "1"}) public static void testS128toI256(short[] input, int[] output) { vectorCast(S2I, SSPEC128, ISPEC256, input, output); } @@ -341,7 +342,7 @@ public static void runS128toI256() throws Throwable { } @Test - @IR(counts = {S2X_NODE, "1"}) + @IR(counts = {IRNode.VECTOR_CAST_S2I, IRNode.VECTOR_SIZE_16, "1"}) public static void testS256toI512(short[] input, int[] output) { vectorCast(S2I, SSPEC256, ISPEC512, input, output); } @@ -352,7 +353,7 @@ public static void runS256toI512() throws Throwable { } @Test - @IR(counts = {S2X_NODE, "1"}) + @IR(counts = {IRNode.VECTOR_CAST_S2L, IRNode.VECTOR_SIZE_2, "1"}) public static void testS64toL64(short[] input, long[] output) { vectorCast(S2L, SSPEC64, LSPEC64, input, output); } @@ -363,7 +364,7 @@ public static void runS64toL64() throws Throwable { } @Test - @IR(counts = {S2X_NODE, "1"}) + @IR(counts = {IRNode.VECTOR_CAST_S2L, IRNode.VECTOR_SIZE_2, "1"}) public static void testS64toL128(short[] input, long[] output) { vectorCast(S2L, SSPEC64, LSPEC128, input, output); } @@ -374,7 +375,7 @@ public static void runS64toL128() throws Throwable { } @Test - @IR(counts = {S2X_NODE, "1"}) + @IR(counts = {IRNode.VECTOR_CAST_S2L, IRNode.VECTOR_SIZE_4, "1"}) public static void testS64toL256(short[] input, long[] output) { vectorCast(S2L, SSPEC64, LSPEC256, input, output); } @@ -385,7 +386,7 @@ public static void runS64toL256() throws Throwable { } @Test - @IR(counts = {S2X_NODE, "1"}) + @IR(counts = {IRNode.VECTOR_CAST_S2L, IRNode.VECTOR_SIZE_8, "1"}) public static void testS128toL512(short[] input, long[] output) { vectorCast(S2L, SSPEC128, LSPEC512, input, output); } @@ -396,7 +397,7 @@ public static void runS128toL512() throws Throwable { } @Test - @IR(counts = {S2X_NODE, "1"}) + @IR(counts = {IRNode.VECTOR_CAST_S2F, IRNode.VECTOR_SIZE_2, "1"}) public static void testS64toF64(short[] input, float[] output) { vectorCast(S2F, SSPEC64, FSPEC64, input, output); } @@ -407,7 +408,7 @@ public static void runS64toF64() throws Throwable { } @Test - @IR(counts = {S2X_NODE, "1"}) + @IR(counts = {IRNode.VECTOR_CAST_S2F, IRNode.VECTOR_SIZE_4, "1"}) public static void testS64toF128(short[] input, float[] output) { vectorCast(S2F, SSPEC64, FSPEC128, input, output); } @@ -418,7 +419,7 @@ public static void runS64toF128() throws Throwable { } @Test - @IR(counts = {S2X_NODE, "1"}) + @IR(counts = {IRNode.VECTOR_CAST_S2F, IRNode.VECTOR_SIZE_8, "1"}) public static void testS128toF256(short[] input, float[] output) { vectorCast(S2F, SSPEC128, FSPEC256, input, output); } @@ -429,7 +430,7 @@ public static void runS128toF256() throws Throwable { } @Test - @IR(counts = {S2X_NODE, "1"}) + @IR(counts = {IRNode.VECTOR_CAST_S2F, IRNode.VECTOR_SIZE_16, "1"}) public static void testS256toF512(short[] input, float[] output) { vectorCast(S2F, SSPEC256, FSPEC512, input, output); } @@ -440,7 +441,7 @@ public static void runS256toF512() throws Throwable { } @Test - @IR(counts = {S2X_NODE, "1"}) + @IR(counts = {IRNode.VECTOR_CAST_S2D, IRNode.VECTOR_SIZE_2, "1"}) public static void testS64toD64(short[] input, double[] output) { vectorCast(S2D, SSPEC64, DSPEC64, input, output); } @@ -451,7 +452,7 @@ public static void runS64toD64() throws Throwable { } @Test - @IR(counts = {S2X_NODE, "1"}) + @IR(counts = {IRNode.VECTOR_CAST_S2D, IRNode.VECTOR_SIZE_2, "1"}) public static void testS64toD128(short[] input, double[] output) { vectorCast(S2D, SSPEC64, DSPEC128, input, output); } @@ -462,7 +463,7 @@ public static void runS64toD128() throws Throwable { } @Test - @IR(counts = {S2X_NODE, "1"}) + @IR(counts = {IRNode.VECTOR_CAST_S2D, IRNode.VECTOR_SIZE_4, "1"}) public static void testS64toD256(short[] input, double[] output) { vectorCast(S2D, SSPEC64, DSPEC256, input, output); } @@ -473,7 +474,7 @@ public static void runS64toD256() throws Throwable { } @Test - @IR(counts = {S2X_NODE, "1"}) + @IR(counts = {IRNode.VECTOR_CAST_S2D, IRNode.VECTOR_SIZE_8, "1"}) public static void testS128toD512(short[] input, double[] output) { vectorCast(S2D, SSPEC128, DSPEC512, input, output); } @@ -484,7 +485,7 @@ public static void runS128toD512() throws Throwable { } @Test - @IR(counts = {I2X_NODE, "1"}) + @IR(counts = {IRNode.VECTOR_CAST_I2B, IRNode.VECTOR_SIZE_2, "1"}) public static void testI64toB64(int[] input, byte[] output) { vectorCast(I2B, ISPEC64, BSPEC64, input, output); } @@ -495,7 +496,7 @@ public static void runI64toB64() throws Throwable { } @Test - @IR(counts = {I2X_NODE, "1"}) + @IR(counts = {IRNode.VECTOR_CAST_I2B, IRNode.VECTOR_SIZE_4, "1"}) public static void testI128toB64(int[] input, byte[] output) { vectorCast(I2B, ISPEC128, BSPEC64, input, output); } @@ -506,7 +507,7 @@ public static void runI128toB64() throws Throwable { } @Test - @IR(counts = {I2X_NODE, "1"}) + @IR(counts = {IRNode.VECTOR_CAST_I2B, IRNode.VECTOR_SIZE_8, "1"}) public static void testI256toB64(int[] input, byte[] output) { vectorCast(I2B, ISPEC256, BSPEC64, input, output); } @@ -517,7 +518,7 @@ public static void runI256toB64() throws Throwable { } @Test - @IR(counts = {I2X_NODE, "1"}) + @IR(counts = {IRNode.VECTOR_CAST_I2B, IRNode.VECTOR_SIZE_16, "1"}) public static void testI512toB128(int[] input, byte[] output) { vectorCast(I2B, ISPEC512, BSPEC128, input, output); } @@ -528,7 +529,7 @@ public static void runI512toB128() throws Throwable { } @Test - @IR(counts = {I2X_NODE, "1"}) + @IR(counts = {IRNode.VECTOR_CAST_I2S, IRNode.VECTOR_SIZE_2, "1"}) public static void testI64toS64(int[] input, short[] output) { vectorCast(I2S, ISPEC64, SSPEC64, input, output); } @@ -539,7 +540,7 @@ public static void runI64toS64() throws Throwable { } @Test - @IR(counts = {I2X_NODE, "1"}) + @IR(counts = {IRNode.VECTOR_CAST_I2S, IRNode.VECTOR_SIZE_4, "1"}) public static void testI128toS64(int[] input, short[] output) { vectorCast(I2S, ISPEC128, SSPEC64, input, output); } @@ -550,7 +551,7 @@ public static void runI128toS64() throws Throwable { } @Test - @IR(counts = {I2X_NODE, "1"}) + @IR(counts = {IRNode.VECTOR_CAST_I2S, IRNode.VECTOR_SIZE_8, "1"}) public static void testI256toS128(int[] input, short[] output) { vectorCast(I2S, ISPEC256, SSPEC128, input, output); } @@ -561,7 +562,7 @@ public static void runI256toS128() throws Throwable { } @Test - @IR(counts = {I2X_NODE, "1"}) + @IR(counts = {IRNode.VECTOR_CAST_I2S, IRNode.VECTOR_SIZE_16, "1"}) public static void testI512toS256(int[] input, short[] output) { vectorCast(I2S, ISPEC512, SSPEC256, input, output); } @@ -572,7 +573,7 @@ public static void runI512toS256() throws Throwable { } @Test - @IR(counts = {I2X_NODE, "1"}) + @IR(counts = {IRNode.VECTOR_CAST_I2L, IRNode.VECTOR_SIZE_2, "1"}) public static void testI64toL64(int[] input, long[] output) { vectorCast(I2L, ISPEC64, LSPEC64, input, output); } @@ -583,7 +584,7 @@ public static void runI64toL64() throws Throwable { } @Test - @IR(counts = {I2X_NODE, "1"}) + @IR(counts = {IRNode.VECTOR_CAST_I2L, IRNode.VECTOR_SIZE_2, "1"}) public static void testI64toL128(int[] input, long[] output) { vectorCast(I2L, ISPEC64, LSPEC128, input, output); } @@ -594,7 +595,7 @@ public static void runI64toL128() throws Throwable { } @Test - @IR(counts = {I2X_NODE, "1"}) + @IR(counts = {IRNode.VECTOR_CAST_I2L, IRNode.VECTOR_SIZE_4, "1"}) public static void testI128toL256(int[] input, long[] output) { vectorCast(I2L, ISPEC128, LSPEC256, input, output); } @@ -605,7 +606,7 @@ public static void runI128toL256() throws Throwable { } @Test - @IR(counts = {I2X_NODE, "1"}) + @IR(counts = {IRNode.VECTOR_CAST_I2L, IRNode.VECTOR_SIZE_8, "1"}) public static void testI256toL512(int[] input, long[] output) { vectorCast(I2L, ISPEC256, LSPEC512, input, output); } @@ -616,7 +617,7 @@ public static void runI256toL512() throws Throwable { } @Test - @IR(counts = {I2X_NODE, "1"}) + @IR(counts = {IRNode.VECTOR_CAST_I2F, IRNode.VECTOR_SIZE_2, "1"}) public static void testI64toF64(int[] input, float[] output) { vectorCast(I2F, ISPEC64, FSPEC64, input, output); } @@ -627,7 +628,7 @@ public static void runI64toF64() throws Throwable { } @Test - @IR(counts = {I2X_NODE, "1"}) + @IR(counts = {IRNode.VECTOR_CAST_I2F, IRNode.VECTOR_SIZE_4, "1"}) public static void testI128toF128(int[] input, float[] output) { vectorCast(I2F, ISPEC128, FSPEC128, input, output); } @@ -638,7 +639,7 @@ public static void runI128toF128() throws Throwable { } @Test - @IR(counts = {I2X_NODE, "1"}) + @IR(counts = {IRNode.VECTOR_CAST_I2F, IRNode.VECTOR_SIZE_8, "1"}) public static void testI256toF256(int[] input, float[] output) { vectorCast(I2F, ISPEC256, FSPEC256, input, output); } @@ -649,7 +650,7 @@ public static void runI256toF256() throws Throwable { } @Test - @IR(counts = {I2X_NODE, "1"}) + @IR(counts = {IRNode.VECTOR_CAST_I2F, IRNode.VECTOR_SIZE_16, "1"}) public static void testI512toF512(int[] input, float[] output) { vectorCast(I2F, ISPEC512, FSPEC512, input, output); } @@ -660,7 +661,7 @@ public static void runI512toF512() throws Throwable { } @Test - @IR(counts = {I2X_NODE, "1"}) + @IR(counts = {IRNode.VECTOR_CAST_I2D, IRNode.VECTOR_SIZE_2, "1"}) public static void testI64toD64(int[] input, double[] output) { vectorCast(I2D, ISPEC64, DSPEC64, input, output); } @@ -671,7 +672,7 @@ public static void runI64toD64() throws Throwable { } @Test - @IR(counts = {I2X_NODE, "1"}) + @IR(counts = {IRNode.VECTOR_CAST_I2D, IRNode.VECTOR_SIZE_2, "1"}) public static void testI64toD128(int[] input, double[] output) { vectorCast(I2D, ISPEC64, DSPEC128, input, output); } @@ -682,7 +683,7 @@ public static void runI64toD128() throws Throwable { } @Test - @IR(counts = {I2X_NODE, "1"}) + @IR(counts = {IRNode.VECTOR_CAST_I2D, IRNode.VECTOR_SIZE_4, "1"}) public static void testI128toD256(int[] input, double[] output) { vectorCast(I2D, ISPEC128, DSPEC256, input, output); } @@ -693,7 +694,7 @@ public static void runI128toD256() throws Throwable { } @Test - @IR(counts = {I2X_NODE, "1"}) + @IR(counts = {IRNode.VECTOR_CAST_I2D, IRNode.VECTOR_SIZE_8, "1"}) public static void testI256toD512(int[] input, double[] output) { vectorCast(I2D, ISPEC256, DSPEC512, input, output); } @@ -704,7 +705,7 @@ public static void runI256toD512() throws Throwable { } @Test - @IR(counts = {L2X_NODE, "1"}) + @IR(counts = {IRNode.VECTOR_CAST_L2B, IRNode.VECTOR_SIZE_2, "1"}) public static void testL64toB64(long[] input, byte[] output) { vectorCast(L2B, LSPEC64, BSPEC64, input, output); } @@ -715,7 +716,7 @@ public static void runL64toB64() throws Throwable { } @Test - @IR(counts = {L2X_NODE, "1"}) + @IR(counts = {IRNode.VECTOR_CAST_L2B, IRNode.VECTOR_SIZE_2, "1"}) public static void testL128toB64(long[] input, byte[] output) { vectorCast(L2B, LSPEC128, BSPEC64, input, output); } @@ -726,7 +727,7 @@ public static void runL128toB64() throws Throwable { } @Test - @IR(counts = {L2X_NODE, "1"}) + @IR(counts = {IRNode.VECTOR_CAST_L2B, IRNode.VECTOR_SIZE_4, "1"}) public static void testL256toB64(long[] input, byte[] output) { vectorCast(L2B, LSPEC256, BSPEC64, input, output); } @@ -737,7 +738,7 @@ public static void runL256toB64() throws Throwable { } @Test - @IR(counts = {L2X_NODE, "1"}) + @IR(counts = {IRNode.VECTOR_CAST_L2B, IRNode.VECTOR_SIZE_8, "1"}) public static void testL512toB64(long[] input, byte[] output) { vectorCast(L2B, LSPEC512, BSPEC64, input, output); } @@ -748,7 +749,7 @@ public static void runL512toB64() throws Throwable { } @Test - @IR(counts = {L2X_NODE, "1"}) + @IR(counts = {IRNode.VECTOR_CAST_L2S, IRNode.VECTOR_SIZE_2, "1"}) public static void testL64toS64(long[] input, short[] output) { vectorCast(L2S, LSPEC64, SSPEC64, input, output); } @@ -759,7 +760,7 @@ public static void runL64toS64() throws Throwable { } @Test - @IR(counts = {L2X_NODE, "1"}) + @IR(counts = {IRNode.VECTOR_CAST_L2S, IRNode.VECTOR_SIZE_2, "1"}) public static void testL128toS64(long[] input, short[] output) { vectorCast(L2S, LSPEC128, SSPEC64, input, output); } @@ -770,7 +771,7 @@ public static void runL128toS64() throws Throwable { } @Test - @IR(counts = {L2X_NODE, "1"}) + @IR(counts = {IRNode.VECTOR_CAST_L2S, IRNode.VECTOR_SIZE_4, "1"}) public static void testL256toS64(long[] input, short[] output) { vectorCast(L2S, LSPEC256, SSPEC64, input, output); } @@ -781,7 +782,7 @@ public static void runL256toS64() throws Throwable { } @Test - @IR(counts = {L2X_NODE, "1"}) + @IR(counts = {IRNode.VECTOR_CAST_L2S, IRNode.VECTOR_SIZE_8, "1"}) public static void testL512toS128(long[] input, short[] output) { vectorCast(L2S, LSPEC512, SSPEC128, input, output); } @@ -792,7 +793,7 @@ public static void runL512toS128() throws Throwable { } @Test - @IR(counts = {L2X_NODE, "1"}) + @IR(counts = {IRNode.VECTOR_CAST_L2I, IRNode.VECTOR_SIZE_2, "1"}) public static void testL64toI64(long[] input, int[] output) { vectorCast(L2I, LSPEC64, ISPEC64, input, output); } @@ -803,7 +804,7 @@ public static void runL64toI64() throws Throwable { } @Test - @IR(counts = {L2X_NODE, "1"}) + @IR(counts = {IRNode.VECTOR_CAST_L2I, IRNode.VECTOR_SIZE_2, "1"}) public static void testL128toI64(long[] input, int[] output) { vectorCast(L2I, LSPEC128, ISPEC64, input, output); } @@ -814,7 +815,7 @@ public static void runL128toI64() throws Throwable { } @Test - @IR(counts = {L2X_NODE, "1"}) + @IR(counts = {IRNode.VECTOR_CAST_L2I, IRNode.VECTOR_SIZE_4, "1"}) public static void testL256toI128(long[] input, int[] output) { vectorCast(L2I, LSPEC256, ISPEC128, input, output); } @@ -825,7 +826,7 @@ public static void runL256toI128() throws Throwable { } @Test - @IR(counts = {L2X_NODE, "1"}) + @IR(counts = {IRNode.VECTOR_CAST_L2I, IRNode.VECTOR_SIZE_8, "1"}) public static void testL512toI256(long[] input, int[] output) { vectorCast(L2I, LSPEC512, ISPEC256, input, output); } @@ -836,7 +837,7 @@ public static void runL512toI256() throws Throwable { } @Test - @IR(counts = {L2X_NODE, "1"}) + @IR(counts = {IRNode.VECTOR_CAST_L2F, IRNode.VECTOR_SIZE_2, "1"}) public static void testL64toF64(long[] input, float[] output) { vectorCast(L2F, LSPEC64, FSPEC64, input, output); } @@ -847,7 +848,7 @@ public static void runL64toF64() throws Throwable { } @Test - @IR(counts = {L2X_NODE, "1"}) + @IR(counts = {IRNode.VECTOR_CAST_L2F, IRNode.VECTOR_SIZE_2, "1"}) public static void testL128toF64(long[] input, float[] output) { vectorCast(L2F, LSPEC128, FSPEC64, input, output); } @@ -858,7 +859,7 @@ public static void runL128toF64() throws Throwable { } @Test - @IR(counts = {L2X_NODE, "1"}) + @IR(counts = {IRNode.VECTOR_CAST_L2F, IRNode.VECTOR_SIZE_4, "1"}) public static void testL256toF128(long[] input, float[] output) { vectorCast(L2F, LSPEC256, FSPEC128, input, output); } @@ -869,7 +870,7 @@ public static void runL256toF128() throws Throwable { } @Test - @IR(counts = {L2X_NODE, "1"}) + @IR(counts = {IRNode.VECTOR_CAST_L2F, IRNode.VECTOR_SIZE_8, "1"}) public static void testL512toF256(long[] input, float[] output) { vectorCast(L2F, LSPEC512, FSPEC256, input, output); } @@ -880,7 +881,7 @@ public static void runL512toF256() throws Throwable { } @Test - @IR(counts = {L2X_NODE, "1"}) + @IR(counts = {IRNode.VECTOR_CAST_L2D, IRNode.VECTOR_SIZE_2, "1"}) public static void testL64toD64(long[] input, double[] output) { vectorCast(L2D, LSPEC64, DSPEC64, input, output); } @@ -891,7 +892,7 @@ public static void runL64toD64() throws Throwable { } @Test - @IR(counts = {L2X_NODE, "1"}) + @IR(counts = {IRNode.VECTOR_CAST_L2D, IRNode.VECTOR_SIZE_2, "1"}) public static void testL128toD128(long[] input, double[] output) { vectorCast(L2D, LSPEC128, DSPEC128, input, output); } @@ -902,7 +903,7 @@ public static void runL128toD128() throws Throwable { } @Test - @IR(counts = {L2X_NODE, "1"}) + @IR(counts = {IRNode.VECTOR_CAST_L2D, IRNode.VECTOR_SIZE_4, "1"}) public static void testL256toD256(long[] input, double[] output) { vectorCast(L2D, LSPEC256, DSPEC256, input, output); } @@ -913,7 +914,7 @@ public static void runL256toD256() throws Throwable { } @Test - @IR(counts = {L2X_NODE, "1"}) + @IR(counts = {IRNode.VECTOR_CAST_L2D, IRNode.VECTOR_SIZE_8, "1"}) public static void testL512toD512(long[] input, double[] output) { vectorCast(L2D, LSPEC512, DSPEC512, input, output); } @@ -924,7 +925,7 @@ public static void runL512toD512() throws Throwable { } @Test - @IR(counts = {F2X_NODE, "1"}) + @IR(counts = {IRNode.VECTOR_CAST_F2B, IRNode.VECTOR_SIZE_2, "1"}) public static void testF64toB64(float[] input, byte[] output) { vectorCast(F2B, FSPEC64, BSPEC64, input, output); } @@ -935,7 +936,7 @@ public static void runF64toB64() throws Throwable { } @Test - @IR(counts = {F2X_NODE, "1"}) + @IR(counts = {IRNode.VECTOR_CAST_F2B, IRNode.VECTOR_SIZE_4, "1"}) public static void testF128toB64(float[] input, byte[] output) { vectorCast(F2B, FSPEC128, BSPEC64, input, output); } @@ -946,7 +947,7 @@ public static void runF128toB64() throws Throwable { } @Test - @IR(counts = {F2X_NODE, "1"}) + @IR(counts = {IRNode.VECTOR_CAST_F2B, IRNode.VECTOR_SIZE_8, "1"}) public static void testF256toB64(float[] input, byte[] output) { vectorCast(F2B, FSPEC256, BSPEC64, input, output); } @@ -957,7 +958,7 @@ public static void runF256toB64() throws Throwable { } @Test - @IR(counts = {F2X_NODE, "1"}) + @IR(counts = {IRNode.VECTOR_CAST_F2B, IRNode.VECTOR_SIZE_16, "1"}) public static void testF512toB128(float[] input, byte[] output) { vectorCast(F2B, FSPEC512, BSPEC128, input, output); } @@ -968,7 +969,7 @@ public static void runF512toB128() throws Throwable { } @Test - @IR(counts = {F2X_NODE, "1"}) + @IR(counts = {IRNode.VECTOR_CAST_F2S, IRNode.VECTOR_SIZE_2, "1"}) public static void testF64toS64(float[] input, short[] output) { vectorCast(F2S, FSPEC64, SSPEC64, input, output); } @@ -979,7 +980,7 @@ public static void runF64toS64() throws Throwable { } @Test - @IR(counts = {F2X_NODE, "1"}) + @IR(counts = {IRNode.VECTOR_CAST_F2S, IRNode.VECTOR_SIZE_4, "1"}) public static void testF128toS64(float[] input, short[] output) { vectorCast(F2S, FSPEC128, SSPEC64, input, output); } @@ -990,7 +991,7 @@ public static void runF128toS64() throws Throwable { } @Test - @IR(counts = {F2X_NODE, "1"}) + @IR(counts = {IRNode.VECTOR_CAST_F2S, IRNode.VECTOR_SIZE_8, "1"}) public static void testF256toS128(float[] input, short[] output) { vectorCast(F2S, FSPEC256, SSPEC128, input, output); } @@ -1001,7 +1002,7 @@ public static void runF256toS128() throws Throwable { } @Test - @IR(counts = {F2X_NODE, "1"}) + @IR(counts = {IRNode.VECTOR_CAST_F2S, IRNode.VECTOR_SIZE_16, "1"}) public static void testF512toS256(float[] input, short[] output) { vectorCast(F2S, FSPEC512, SSPEC256, input, output); } @@ -1012,7 +1013,7 @@ public static void runF512toS256() throws Throwable { } @Test - @IR(counts = {F2X_NODE, "1"}) + @IR(counts = {IRNode.VECTOR_CAST_F2I, IRNode.VECTOR_SIZE_2, "1"}) public static void testF64toI64(float[] input, int[] output) { vectorCast(F2I, FSPEC64, ISPEC64, input, output); } @@ -1023,7 +1024,7 @@ public static void runF64toI64() throws Throwable { } @Test - @IR(counts = {F2X_NODE, "1"}) + @IR(counts = {IRNode.VECTOR_CAST_F2I, IRNode.VECTOR_SIZE_4, "1"}) public static void testF128toI128(float[] input, int[] output) { vectorCast(F2I, FSPEC128, ISPEC128, input, output); } @@ -1034,7 +1035,7 @@ public static void runF128toI128() throws Throwable { } @Test - @IR(counts = {F2X_NODE, "1"}) + @IR(counts = {IRNode.VECTOR_CAST_F2I, IRNode.VECTOR_SIZE_8, "1"}) public static void testF256toI256(float[] input, int[] output) { vectorCast(F2I, FSPEC256, ISPEC256, input, output); } @@ -1045,7 +1046,7 @@ public static void runF256toI256() throws Throwable { } @Test - @IR(counts = {F2X_NODE, "1"}) + @IR(counts = {IRNode.VECTOR_CAST_F2I, IRNode.VECTOR_SIZE_16, "1"}) public static void testF512toI512(float[] input, int[] output) { vectorCast(F2I, FSPEC512, ISPEC512, input, output); } @@ -1056,7 +1057,7 @@ public static void runF512toI512() throws Throwable { } @Test - @IR(counts = {F2X_NODE, "1"}) + @IR(counts = {IRNode.VECTOR_CAST_F2L, IRNode.VECTOR_SIZE_2, "1"}) public static void testF64toL64(float[] input, long[] output) { vectorCast(F2L, FSPEC64, LSPEC64, input, output); } @@ -1067,7 +1068,7 @@ public static void runF64toL64() throws Throwable { } @Test - @IR(counts = {F2X_NODE, "1"}) + @IR(counts = {IRNode.VECTOR_CAST_F2L, IRNode.VECTOR_SIZE_2, "1"}) public static void testF64toL128(float[] input, long[] output) { vectorCast(F2L, FSPEC64, LSPEC128, input, output); } @@ -1078,7 +1079,7 @@ public static void runF64toL128() throws Throwable { } @Test - @IR(counts = {F2X_NODE, "1"}) + @IR(counts = {IRNode.VECTOR_CAST_F2L, IRNode.VECTOR_SIZE_4, "1"}) public static void testF128toL256(float[] input, long[] output) { vectorCast(F2L, FSPEC128, LSPEC256, input, output); } @@ -1089,7 +1090,7 @@ public static void runF128toL256() throws Throwable { } @Test - @IR(counts = {F2X_NODE, "1"}) + @IR(counts = {IRNode.VECTOR_CAST_F2L, IRNode.VECTOR_SIZE_8, "1"}) public static void testF256toL512(float[] input, long[] output) { vectorCast(F2L, FSPEC256, LSPEC512, input, output); } @@ -1100,7 +1101,7 @@ public static void runF256toL512() throws Throwable { } @Test - @IR(counts = {F2X_NODE, "1"}) + @IR(counts = {IRNode.VECTOR_CAST_F2L, IRNode.VECTOR_SIZE_8, "1"}) public static void testF64toD64(float[] input, double[] output) { vectorCast(F2D, FSPEC64, DSPEC64, input, output); } @@ -1111,7 +1112,7 @@ public static void runF64toD64() throws Throwable { } @Test - @IR(counts = {F2X_NODE, "1"}) + @IR(counts = {IRNode.VECTOR_CAST_F2D, IRNode.VECTOR_SIZE_2, "1"}) public static void testF64toD128(float[] input, double[] output) { vectorCast(F2D, FSPEC64, DSPEC128, input, output); } @@ -1122,7 +1123,7 @@ public static void runF64toD128() throws Throwable { } @Test - @IR(counts = {F2X_NODE, "1"}) + @IR(counts = {IRNode.VECTOR_CAST_F2D, IRNode.VECTOR_SIZE_4, "1"}) public static void testF128toD256(float[] input, double[] output) { vectorCast(F2D, FSPEC128, DSPEC256, input, output); } @@ -1133,7 +1134,7 @@ public static void runF128toD256() throws Throwable { } @Test - @IR(counts = {F2X_NODE, "1"}) + @IR(counts = {IRNode.VECTOR_CAST_F2D, IRNode.VECTOR_SIZE_8, "1"}) public static void testF256toD512(float[] input, double[] output) { vectorCast(F2D, FSPEC256, DSPEC512, input, output); } @@ -1144,7 +1145,7 @@ public static void runF256toD512() throws Throwable { } @Test - @IR(counts = {D2X_NODE, "1"}) + @IR(counts = {IRNode.VECTOR_CAST_D2B, IRNode.VECTOR_SIZE_2, "1"}) public static void testD64toB64(double[] input, byte[] output) { vectorCast(D2B, DSPEC64, BSPEC64, input, output); } @@ -1155,7 +1156,7 @@ public static void runD64toB64() throws Throwable { } @Test - @IR(counts = {D2X_NODE, "1"}) + @IR(counts = {IRNode.VECTOR_CAST_D2B, IRNode.VECTOR_SIZE_2, "1"}) public static void testD128toB64(double[] input, byte[] output) { vectorCast(D2B, DSPEC128, BSPEC64, input, output); } @@ -1166,7 +1167,7 @@ public static void runD128toB64() throws Throwable { } @Test - @IR(counts = {D2X_NODE, "1"}) + @IR(counts = {IRNode.VECTOR_CAST_D2B, IRNode.VECTOR_SIZE_4, "1"}) public static void testD256toB64(double[] input, byte[] output) { vectorCast(D2B, DSPEC256, BSPEC64, input, output); } @@ -1177,7 +1178,7 @@ public static void runD256toB64() throws Throwable { } @Test - @IR(counts = {D2X_NODE, "1"}) + @IR(counts = {IRNode.VECTOR_CAST_D2B, IRNode.VECTOR_SIZE_8, "1"}) public static void testD512toB64(double[] input, byte[] output) { vectorCast(D2B, DSPEC512, BSPEC64, input, output); } @@ -1188,7 +1189,7 @@ public static void runD512toB64() throws Throwable { } @Test - @IR(counts = {D2X_NODE, "1"}) + @IR(counts = {IRNode.VECTOR_CAST_D2S, IRNode.VECTOR_SIZE_2, "1"}) public static void testD64toS64(double[] input, short[] output) { vectorCast(D2S, DSPEC64, SSPEC64, input, output); } @@ -1199,7 +1200,7 @@ public static void runD64toS64() throws Throwable { } @Test - @IR(counts = {D2X_NODE, "1"}) + @IR(counts = {IRNode.VECTOR_CAST_D2S, IRNode.VECTOR_SIZE_2, "1"}) public static void testD128toS64(double[] input, short[] output) { vectorCast(D2S, DSPEC128, SSPEC64, input, output); } @@ -1210,7 +1211,7 @@ public static void runD128toS64() throws Throwable { } @Test - @IR(counts = {D2X_NODE, "1"}) + @IR(counts = {IRNode.VECTOR_CAST_D2S, IRNode.VECTOR_SIZE_4, "1"}) public static void testD256toS64(double[] input, short[] output) { vectorCast(D2S, DSPEC256, SSPEC64, input, output); } @@ -1221,7 +1222,7 @@ public static void runD256toS64() throws Throwable { } @Test - @IR(counts = {D2X_NODE, "1"}) + @IR(counts = {IRNode.VECTOR_CAST_D2S, IRNode.VECTOR_SIZE_8, "1"}) public static void testD512toS128(double[] input, short[] output) { vectorCast(D2S, DSPEC512, SSPEC128, input, output); } @@ -1232,7 +1233,7 @@ public static void runD512toS128() throws Throwable { } @Test - @IR(counts = {D2X_NODE, "1"}) + @IR(counts = {IRNode.VECTOR_CAST_D2I, IRNode.VECTOR_SIZE_2, "1"}) public static void testD64toI64(double[] input, int[] output) { vectorCast(D2I, DSPEC64, ISPEC64, input, output); } @@ -1243,7 +1244,7 @@ public static void runD64toI64() throws Throwable { } @Test - @IR(counts = {D2X_NODE, "1"}) + @IR(counts = {IRNode.VECTOR_CAST_D2I, IRNode.VECTOR_SIZE_2, "1"}) public static void testD128toI64(double[] input, int[] output) { vectorCast(D2I, DSPEC128, ISPEC64, input, output); } @@ -1254,7 +1255,7 @@ public static void runD128toI64() throws Throwable { } @Test - @IR(counts = {D2X_NODE, "1"}) + @IR(counts = {IRNode.VECTOR_CAST_D2I, IRNode.VECTOR_SIZE_4, "1"}) public static void testD256toI128(double[] input, int[] output) { vectorCast(D2I, DSPEC256, ISPEC128, input, output); } @@ -1265,7 +1266,7 @@ public static void runD256toI128() throws Throwable { } @Test - @IR(counts = {D2X_NODE, "1"}) + @IR(counts = {IRNode.VECTOR_CAST_D2I, IRNode.VECTOR_SIZE_8, "1"}) public static void testD512toI256(double[] input, int[] output) { vectorCast(D2I, DSPEC512, ISPEC256, input, output); } @@ -1276,7 +1277,7 @@ public static void runD512toI256() throws Throwable { } @Test - @IR(counts = {D2X_NODE, "1"}) + @IR(counts = {IRNode.VECTOR_CAST_D2L, IRNode.VECTOR_SIZE_2, "1"}) public static void testD64toL64(double[] input, long[] output) { vectorCast(D2L, DSPEC64, LSPEC64, input, output); } @@ -1287,7 +1288,7 @@ public static void runD64toL64() throws Throwable { } @Test - @IR(counts = {D2X_NODE, "1"}) + @IR(counts = {IRNode.VECTOR_CAST_D2L, IRNode.VECTOR_SIZE_2, "1"}) public static void testD128toL128(double[] input, long[] output) { vectorCast(D2L, DSPEC128, LSPEC128, input, output); } @@ -1298,7 +1299,7 @@ public static void runD128toL128() throws Throwable { } @Test - @IR(counts = {D2X_NODE, "1"}) + @IR(counts = {IRNode.VECTOR_CAST_D2L, IRNode.VECTOR_SIZE_4, "1"}) public static void testD256toL256(double[] input, long[] output) { vectorCast(D2L, DSPEC256, LSPEC256, input, output); } @@ -1309,7 +1310,7 @@ public static void runD256toL256() throws Throwable { } @Test - @IR(counts = {D2X_NODE, "1"}) + @IR(counts = {IRNode.VECTOR_CAST_D2L, IRNode.VECTOR_SIZE_8, "1"}) public static void testD512toL512(double[] input, long[] output) { vectorCast(D2L, DSPEC512, LSPEC512, input, output); } @@ -1320,7 +1321,7 @@ public static void runD512toL512() throws Throwable { } @Test - @IR(counts = {D2X_NODE, "1"}) + @IR(counts = {IRNode.VECTOR_CAST_D2L, IRNode.VECTOR_SIZE_8, "1"}) public static void testD64toF64(double[] input, float[] output) { vectorCast(D2F, DSPEC64, FSPEC64, input, output); } @@ -1331,7 +1332,7 @@ public static void runD64toF64() throws Throwable { } @Test - @IR(counts = {D2X_NODE, "1"}) + @IR(counts = {IRNode.VECTOR_CAST_D2F, IRNode.VECTOR_SIZE_2, "1"}) public static void testD128toF64(double[] input, float[] output) { vectorCast(D2F, DSPEC128, FSPEC64, input, output); } @@ -1342,7 +1343,7 @@ public static void runD128toF64() throws Throwable { } @Test - @IR(counts = {D2X_NODE, "1"}) + @IR(counts = {IRNode.VECTOR_CAST_D2F, IRNode.VECTOR_SIZE_4, "1"}) public static void testD256toF128(double[] input, float[] output) { vectorCast(D2F, DSPEC256, FSPEC128, input, output); } @@ -1353,7 +1354,7 @@ public static void runD256toF128() throws Throwable { } @Test - @IR(counts = {D2X_NODE, "1"}) + @IR(counts = {IRNode.VECTOR_CAST_D2F, IRNode.VECTOR_SIZE_8, "1"}) public static void testD512toF256(double[] input, float[] output) { vectorCast(D2F, DSPEC512, FSPEC256, input, output); } @@ -1364,7 +1365,7 @@ public static void runD512toF256() throws Throwable { } @Test - @IR(counts = {UB2X_NODE, "1"}) + @IR(counts = {IRNode.VECTOR_UCAST_B2S, IRNode.VECTOR_SIZE_4, "1"}) public static void testUB64toS64(byte[] input, short[] output) { vectorCast(ZERO_EXTEND_B2S, BSPEC64, SSPEC64, input, output); } @@ -1375,7 +1376,7 @@ public static void runUB64toS64() throws Throwable { } @Test - @IR(counts = {UB2X_NODE, "1"}) + @IR(counts = {IRNode.VECTOR_UCAST_B2S, IRNode.VECTOR_SIZE_8, "1"}) public static void testUB64toS128(byte[] input, short[] output) { vectorCast(ZERO_EXTEND_B2S, BSPEC64, SSPEC128, input, output); } @@ -1386,7 +1387,7 @@ public static void runUB64toS128() throws Throwable { } @Test - @IR(counts = {UB2X_NODE, "1"}) + @IR(counts = {IRNode.VECTOR_UCAST_B2S, IRNode.VECTOR_SIZE_16, "1"}) public static void testUB128toS256(byte[] input, short[] output) { vectorCast(ZERO_EXTEND_B2S, BSPEC128, SSPEC256, input, output); } @@ -1397,7 +1398,7 @@ public static void runUB128toS256() throws Throwable { } @Test - @IR(counts = {UB2X_NODE, "1"}) + @IR(counts = {IRNode.VECTOR_UCAST_B2S, IRNode.VECTOR_SIZE_32, "1"}) public static void testUB256toS512(byte[] input, short[] output) { vectorCast(ZERO_EXTEND_B2S, BSPEC256, SSPEC512, input, output); } @@ -1408,7 +1409,7 @@ public static void runUB256toS512() throws Throwable { } @Test - @IR(counts = {UB2X_NODE, "1"}) + @IR(counts = {IRNode.VECTOR_UCAST_B2I, IRNode.VECTOR_SIZE_2, "1"}) public static void testUB64toI64(byte[] input, int[] output) { vectorCast(ZERO_EXTEND_B2I, BSPEC64, ISPEC64, input, output); } @@ -1419,7 +1420,7 @@ public static void runUB64toI64() throws Throwable { } @Test - @IR(counts = {UB2X_NODE, "1"}) + @IR(counts = {IRNode.VECTOR_UCAST_B2I, IRNode.VECTOR_SIZE_4, "1"}) public static void testUB64toI128(byte[] input, int[] output) { vectorCast(ZERO_EXTEND_B2I, BSPEC64, ISPEC128, input, output); } @@ -1430,7 +1431,7 @@ public static void runUB64toI128() throws Throwable { } @Test - @IR(counts = {UB2X_NODE, "1"}) + @IR(counts = {IRNode.VECTOR_UCAST_B2I, IRNode.VECTOR_SIZE_8, "1"}) public static void testUB64toI256(byte[] input, int[] output) { vectorCast(ZERO_EXTEND_B2I, BSPEC64, ISPEC256, input, output); } @@ -1441,7 +1442,7 @@ public static void runUB64toI256() throws Throwable { } @Test - @IR(counts = {UB2X_NODE, "1"}) + @IR(counts = {IRNode.VECTOR_UCAST_B2I, IRNode.VECTOR_SIZE_16, "1"}) public static void testUB128toI512(byte[] input, int[] output) { vectorCast(ZERO_EXTEND_B2I, BSPEC128, ISPEC512, input, output); } @@ -1452,7 +1453,7 @@ public static void runUB128toI512() throws Throwable { } @Test - @IR(counts = {UB2X_NODE, "1"}) + @IR(counts = {IRNode.VECTOR_UCAST_B2L, IRNode.VECTOR_SIZE_2, "1"}) public static void testUB64toL64(byte[] input, long[] output) { vectorCast(ZERO_EXTEND_B2L, BSPEC64, LSPEC64, input, output); } @@ -1463,7 +1464,7 @@ public static void runUB64toL64() throws Throwable { } @Test - @IR(counts = {UB2X_NODE, "1"}) + @IR(counts = {IRNode.VECTOR_UCAST_B2L, IRNode.VECTOR_SIZE_2, "1"}) public static void testUB64toL128(byte[] input, long[] output) { vectorCast(ZERO_EXTEND_B2L, BSPEC64, LSPEC128, input, output); } @@ -1474,7 +1475,7 @@ public static void runUB64toL128() throws Throwable { } @Test - @IR(counts = {UB2X_NODE, "1"}) + @IR(counts = {IRNode.VECTOR_UCAST_B2L, IRNode.VECTOR_SIZE_4, "1"}) public static void testUB64toL256(byte[] input, long[] output) { vectorCast(ZERO_EXTEND_B2L, BSPEC64, LSPEC256, input, output); } @@ -1485,7 +1486,7 @@ public static void runUB64toL256() throws Throwable { } @Test - @IR(counts = {UB2X_NODE, "1"}) + @IR(counts = {IRNode.VECTOR_UCAST_B2L, IRNode.VECTOR_SIZE_8, "1"}) public static void testUB64toL512(byte[] input, long[] output) { vectorCast(ZERO_EXTEND_B2L, BSPEC64, LSPEC512, input, output); } @@ -1496,7 +1497,7 @@ public static void runUB64toL512() throws Throwable { } @Test - @IR(counts = {US2X_NODE, "1"}) + @IR(counts = {IRNode.VECTOR_UCAST_S2I, IRNode.VECTOR_SIZE_2, "1"}) public static void testUS64toI64(short[] input, int[] output) { vectorCast(ZERO_EXTEND_S2I, SSPEC64, ISPEC64, input, output); } @@ -1507,7 +1508,7 @@ public static void runUS64toI64() throws Throwable { } @Test - @IR(counts = {US2X_NODE, "1"}) + @IR(counts = {IRNode.VECTOR_UCAST_S2I, IRNode.VECTOR_SIZE_4, "1"}) public static void testUS64toI128(short[] input, int[] output) { vectorCast(ZERO_EXTEND_S2I, SSPEC64, ISPEC128, input, output); } @@ -1518,7 +1519,7 @@ public static void runUS64toI128() throws Throwable { } @Test - @IR(counts = {US2X_NODE, "1"}) + @IR(counts = {IRNode.VECTOR_UCAST_S2I, IRNode.VECTOR_SIZE_8, "1"}) public static void testUS128toI256(short[] input, int[] output) { vectorCast(ZERO_EXTEND_S2I, SSPEC128, ISPEC256, input, output); } @@ -1529,7 +1530,7 @@ public static void runUS128toI256() throws Throwable { } @Test - @IR(counts = {US2X_NODE, "1"}) + @IR(counts = {IRNode.VECTOR_UCAST_S2I, IRNode.VECTOR_SIZE_16, "1"}) public static void testUS256toI512(short[] input, int[] output) { vectorCast(ZERO_EXTEND_S2I, SSPEC256, ISPEC512, input, output); } @@ -1540,7 +1541,7 @@ public static void runUS256toI512() throws Throwable { } @Test - @IR(counts = {US2X_NODE, "1"}) + @IR(counts = {IRNode.VECTOR_UCAST_S2L, IRNode.VECTOR_SIZE_2, "1"}) public static void testUS64toL64(short[] input, long[] output) { vectorCast(ZERO_EXTEND_S2L, SSPEC64, LSPEC64, input, output); } @@ -1551,7 +1552,7 @@ public static void runUS64toL64() throws Throwable { } @Test - @IR(counts = {US2X_NODE, "1"}) + @IR(counts = {IRNode.VECTOR_UCAST_S2L, IRNode.VECTOR_SIZE_2, "1"}) public static void testUS64toL128(short[] input, long[] output) { vectorCast(ZERO_EXTEND_S2L, SSPEC64, LSPEC128, input, output); } @@ -1562,7 +1563,7 @@ public static void runUS64toL128() throws Throwable { } @Test - @IR(counts = {US2X_NODE, "1"}) + @IR(counts = {IRNode.VECTOR_UCAST_S2L, IRNode.VECTOR_SIZE_4, "1"}) public static void testUS64toL256(short[] input, long[] output) { vectorCast(ZERO_EXTEND_S2L, SSPEC64, LSPEC256, input, output); } @@ -1573,7 +1574,7 @@ public static void runUS64toL256() throws Throwable { } @Test - @IR(counts = {US2X_NODE, "1"}) + @IR(counts = {IRNode.VECTOR_UCAST_S2L, IRNode.VECTOR_SIZE_8, "1"}) public static void testUS128toL512(short[] input, long[] output) { vectorCast(ZERO_EXTEND_S2L, SSPEC128, LSPEC512, input, output); } @@ -1584,7 +1585,7 @@ public static void runUS128toL512() throws Throwable { } @Test - @IR(counts = {UI2X_NODE, "1"}) + @IR(counts = {IRNode.VECTOR_UCAST_I2L, IRNode.VECTOR_SIZE_2, "1"}) public static void testUI64toL64(int[] input, long[] output) { vectorCast(ZERO_EXTEND_I2L, ISPEC64, LSPEC64, input, output); } @@ -1595,7 +1596,7 @@ public static void runUI64toL64() throws Throwable { } @Test - @IR(counts = {UI2X_NODE, "1"}) + @IR(counts = {IRNode.VECTOR_UCAST_I2L, IRNode.VECTOR_SIZE_2, "1"}) public static void testUI64toL128(int[] input, long[] output) { vectorCast(ZERO_EXTEND_I2L, ISPEC64, LSPEC128, input, output); } @@ -1606,7 +1607,7 @@ public static void runUI64toL128() throws Throwable { } @Test - @IR(counts = {UI2X_NODE, "1"}) + @IR(counts = {IRNode.VECTOR_UCAST_I2L, IRNode.VECTOR_SIZE_4, "1"}) public static void testUI128toL256(int[] input, long[] output) { vectorCast(ZERO_EXTEND_I2L, ISPEC128, LSPEC256, input, output); } @@ -1617,7 +1618,7 @@ public static void runUI128toL256() throws Throwable { } @Test - @IR(counts = {UI2X_NODE, "1"}) + @IR(counts = {IRNode.VECTOR_UCAST_I2L, IRNode.VECTOR_SIZE_8, "1"}) public static void testUI256toL512(int[] input, long[] output) { vectorCast(ZERO_EXTEND_I2L, ISPEC256, LSPEC512, input, output); } diff --git a/test/hotspot/jtreg/compiler/vectorapi/reshape/utils/VectorReshapeHelper.java b/test/hotspot/jtreg/compiler/vectorapi/reshape/utils/VectorReshapeHelper.java index 0349ae0187136..349429b6c8046 100644 --- a/test/hotspot/jtreg/compiler/vectorapi/reshape/utils/VectorReshapeHelper.java +++ b/test/hotspot/jtreg/compiler/vectorapi/reshape/utils/VectorReshapeHelper.java @@ -71,15 +71,6 @@ public class VectorReshapeHelper { public static final VectorSpecies FSPEC512 = FloatVector.SPECIES_512; public static final VectorSpecies DSPEC512 = DoubleVector.SPECIES_512; - public static final String B2X_NODE = IRNode.VECTOR_CAST_B2X; - public static final String S2X_NODE = IRNode.VECTOR_CAST_S2X; - public static final String I2X_NODE = IRNode.VECTOR_CAST_I2X; - public static final String L2X_NODE = IRNode.VECTOR_CAST_L2X; - public static final String F2X_NODE = IRNode.VECTOR_CAST_F2X; - public static final String D2X_NODE = IRNode.VECTOR_CAST_D2X; - public static final String UB2X_NODE = IRNode.VECTOR_UCAST_B2X; - public static final String US2X_NODE = IRNode.VECTOR_UCAST_S2X; - public static final String UI2X_NODE = IRNode.VECTOR_UCAST_I2X; public static final String REINTERPRET_NODE = IRNode.VECTOR_REINTERPRET; public static void runMainHelper(Class testClass, Stream testMethods, String... flags) { diff --git a/test/hotspot/jtreg/compiler/vectorization/TestAutoVecIntMinMax.java b/test/hotspot/jtreg/compiler/vectorization/TestAutoVecIntMinMax.java index e15a4c834cd07..e3baed37804e0 100644 --- a/test/hotspot/jtreg/compiler/vectorization/TestAutoVecIntMinMax.java +++ b/test/hotspot/jtreg/compiler/vectorization/TestAutoVecIntMinMax.java @@ -62,8 +62,8 @@ public static void main(String[] args) { // Test for auto-vectorization of Math.min operation on an array of integers @Test - @IR(counts = {IRNode.LOAD_VECTOR, " >0 "}) - @IR(counts = {IRNode.MIN_V, " >0 "}) + @IR(counts = {IRNode.LOAD_VECTOR_I, " >0 "}) + @IR(counts = {IRNode.MIN_VI, " >0 "}) @IR(counts = {IRNode.STORE_VECTOR, " >0 "}) private static void testIntMin(int[] a, int[] b) { for(int i = 0; i < LENGTH; i++) { @@ -73,8 +73,8 @@ private static void testIntMin(int[] a, int[] b) { // Test for auto-vectorization of StrictMath.min operation on an array of integers @Test - @IR(counts = {IRNode.LOAD_VECTOR, " >0 "}) - @IR(counts = {IRNode.MIN_V, " >0 "}) + @IR(counts = {IRNode.LOAD_VECTOR_I, " >0 "}) + @IR(counts = {IRNode.MIN_VI, " >0 "}) @IR(counts = {IRNode.STORE_VECTOR, " >0 "}) private static void testIntStrictMin(int[] a, int[] b) { for(int i = 0; i < LENGTH; i++) { @@ -84,8 +84,8 @@ private static void testIntStrictMin(int[] a, int[] b) { // Test for auto-vectorization of Math.max operation on an array of integers @Test - @IR(counts = {IRNode.LOAD_VECTOR, " >0 "}) - @IR(counts = {IRNode.MAX_V, " >0 "}) + @IR(counts = {IRNode.LOAD_VECTOR_I, " >0 "}) + @IR(counts = {IRNode.MAX_VI, " >0 "}) @IR(counts = {IRNode.STORE_VECTOR, " >0 "}) private static void testIntMax(int[] a, int[] b) { for(int i = 0; i < LENGTH; i++) { @@ -95,8 +95,8 @@ private static void testIntMax(int[] a, int[] b) { // Test for auto-vectorization of StrictMath.max operation on an array of integers @Test - @IR(counts = {IRNode.LOAD_VECTOR, " >0 "}) - @IR(counts = {IRNode.MAX_V, " >0 "}) + @IR(counts = {IRNode.LOAD_VECTOR_I, " >0 "}) + @IR(counts = {IRNode.MAX_VI, " >0 "}) @IR(counts = {IRNode.STORE_VECTOR, " >0 "}) private static void testIntStrictMax(int[] a, int[] b) { for(int i = 0; i < LENGTH; i++) { diff --git a/test/hotspot/jtreg/compiler/vectorization/TestFloatConversionsVector.java b/test/hotspot/jtreg/compiler/vectorization/TestFloatConversionsVector.java index 186f829f18f7e..49035332fa432 100644 --- a/test/hotspot/jtreg/compiler/vectorization/TestFloatConversionsVector.java +++ b/test/hotspot/jtreg/compiler/vectorization/TestFloatConversionsVector.java @@ -51,7 +51,7 @@ public static void main(String args[]) { } @Test - @IR(counts = {IRNode.VECTOR_CAST_F2HF, "> 0"}) + @IR(counts = {IRNode.VECTOR_CAST_F2HF, IRNode.VECTOR_SIZE + "min(max_float, max_short)", "> 0"}) public void test_float_float16(short[] sout, float[] finp) { for (int i = 0; i < finp.length; i++) { sout[i] = Float.floatToFloat16(finp[i]); @@ -94,7 +94,7 @@ public void kernel_test_float_float16() { } @Test - @IR(counts = {IRNode.VECTOR_CAST_HF2F, "> 0"}) + @IR(counts = {IRNode.VECTOR_CAST_HF2F, IRNode.VECTOR_SIZE + "min(max_float, max_short)", "> 0"}) public void test_float16_float(float[] fout, short[] sinp) { for (int i = 0; i < sinp.length; i++) { fout[i] = Float.float16ToFloat(sinp[i]); diff --git a/test/hotspot/jtreg/compiler/vectorization/TestOptionVectorizeIR.java b/test/hotspot/jtreg/compiler/vectorization/TestOptionVectorizeIR.java index 8c5217c1d5121..7d10070401338 100644 --- a/test/hotspot/jtreg/compiler/vectorization/TestOptionVectorizeIR.java +++ b/test/hotspot/jtreg/compiler/vectorization/TestOptionVectorizeIR.java @@ -34,8 +34,8 @@ import compiler.lib.ir_framework.*; public class TestOptionVectorizeIR { - static final int RANGE = 512; - static final int ITER = 100; + static int RANGE = 1024*2; + static int ITER = 100; int[] gold1 = new int[RANGE]; int[] gold2 = new int[RANGE]; int[] gold3 = new int[RANGE]; @@ -220,7 +220,7 @@ static void test1(int[] data) { } @Test - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.ADD_VI, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_I, "> 0", IRNode.ADD_VI, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIf = {"AlignVector", "false"}, applyIfCPUFeatureOr = {"sse4.1", "true", "asimd", "true"}) static void test2(int[] data) { @@ -231,7 +231,7 @@ static void test2(int[] data) { } @Test - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.REPLICATE_I, "> 0", IRNode.ADD_VI, "> 0", IRNode.MUL_VI, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_I, "> 0", IRNode.REPLICATE_I, "> 0", IRNode.ADD_VI, "> 0", IRNode.MUL_VI, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIf = {"AlignVector", "false"}, applyIfCPUFeatureOr = {"sse4.1", "true", "asimd", "true"}) static void test3(int[] data, int A, int B) { @@ -273,7 +273,7 @@ static void test6(int[] data) { // ------------------------- Long ----------------------------- @Test - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.ADD_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_L, "> 0", IRNode.ADD_VL, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIf = {"AlignVector", "false"}, applyIfCPUFeatureOr = {"sse4.1", "true", "asimd", "true"}) static void test10(long[] data) { @@ -283,7 +283,7 @@ static void test10(long[] data) { } @Test - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.ADD_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_L, "> 0", IRNode.ADD_VL, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIf = {"AlignVector", "false"}, applyIfCPUFeatureOr = {"sse4.1", "true", "asimd", "true"}) static void test11(long[] data) { @@ -347,7 +347,7 @@ public void runTest13() { // ------------------------- Short ----------------------------- @Test - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.ADD_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_S, "> 0", IRNode.ADD_VS, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIf = {"AlignVector", "false"}, applyIfCPUFeatureOr = {"sse4.1", "true", "asimd", "true"}) static void test20(short[] data) { @@ -357,7 +357,7 @@ static void test20(short[] data) { } @Test - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.ADD_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_S, "> 0", IRNode.ADD_VS, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIf = {"AlignVector", "false"}, applyIfCPUFeatureOr = {"sse4.1", "true", "asimd", "true"}) static void test21(short[] data) { @@ -420,7 +420,7 @@ public void runTest23() { // ------------------------- Byte ----------------------------- @Test - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.ADD_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_B, "> 0", IRNode.ADD_VB, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIf = {"AlignVector", "false"}, applyIfCPUFeatureOr = {"sse4.1", "true", "asimd", "true"}) static void test30(byte[] data) { @@ -430,7 +430,7 @@ static void test30(byte[] data) { } @Test - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.ADD_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_B, "> 0", IRNode.ADD_VB, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIf = {"AlignVector", "false"}, applyIfCPUFeatureOr = {"sse4.1", "true", "asimd", "true"}) static void test31(byte[] data) { @@ -493,7 +493,7 @@ public void runTest33() { // ------------------------- Char ----------------------------- @Test - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.ADD_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_C, "> 0", IRNode.ADD_VS, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIf = {"AlignVector", "false"}, applyIfCPUFeatureOr = {"sse4.1", "true", "asimd", "true"}) static void test40(char[] data) { @@ -503,7 +503,7 @@ static void test40(char[] data) { } @Test - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.ADD_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_C, "> 0", IRNode.ADD_VS, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIf = {"AlignVector", "false"}, applyIfCPUFeatureOr = {"sse4.1", "true", "asimd", "true"}) static void test41(char[] data) { @@ -565,7 +565,7 @@ public void runTest43() { // ------------------------- Float ----------------------------- @Test - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.ADD_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_F, "> 0", IRNode.ADD_VF, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIf = {"AlignVector", "false"}, applyIfCPUFeatureOr = {"sse4.1", "true", "asimd", "true"}) static void test50(float[] data) { @@ -575,7 +575,7 @@ static void test50(float[] data) { } @Test - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.ADD_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_F, "> 0", IRNode.ADD_VF, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIf = {"AlignVector", "false"}, applyIfCPUFeatureOr = {"sse4.1", "true", "asimd", "true"}) static void test51(float[] data) { @@ -637,7 +637,7 @@ public void runTest53() { // ------------------------- Double ----------------------------- @Test - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.ADD_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_D, "> 0", IRNode.ADD_VD, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIf = {"AlignVector", "false"}, applyIfCPUFeatureOr = {"sse4.1", "true", "asimd", "true"}) static void test60(double[] data) { @@ -647,7 +647,7 @@ static void test60(double[] data) { } @Test - @IR(counts = {IRNode.LOAD_VECTOR, "> 0", IRNode.ADD_V, "> 0", IRNode.STORE_VECTOR, "> 0"}, + @IR(counts = {IRNode.LOAD_VECTOR_D, "> 0", IRNode.ADD_VD, "> 0", IRNode.STORE_VECTOR, "> 0"}, applyIf = {"AlignVector", "false"}, applyIfCPUFeatureOr = {"sse4.1", "true", "asimd", "true"}) static void test61(double[] data) { diff --git a/test/hotspot/jtreg/compiler/vectorization/TestReverseBitsVector.java b/test/hotspot/jtreg/compiler/vectorization/TestReverseBitsVector.java index a30015d73f823..1144186d8e585 100644 --- a/test/hotspot/jtreg/compiler/vectorization/TestReverseBitsVector.java +++ b/test/hotspot/jtreg/compiler/vectorization/TestReverseBitsVector.java @@ -73,7 +73,7 @@ public static void main(String args[]) { } @Test - @IR(counts = {IRNode.REVERSE_V, "> 0"}) + @IR(counts = {IRNode.REVERSE_VL, "> 0"}) public void test_reverse_long1(long[] lout, long[] linp) { for (int i = 0; i < lout.length; i+=1) { lout[i] = Long.reverse(linp[i]); @@ -89,7 +89,7 @@ public void kernel_test_reverse_long1() { } @Test - @IR(failOn = {IRNode.REVERSE_V, IRNode.REVERSE_L}) + @IR(failOn = {IRNode.REVERSE_VL, IRNode.REVERSE_L}) public void test_reverse_long2(long[] lout, long[] linp) { for (int i = 0; i < lout.length; i+=1) { lout[i] = Long.reverse(Long.reverse(linp[i])); @@ -105,7 +105,7 @@ public void kernel_test_reverse_long2() { } @Test - @IR(failOn = {IRNode.REVERSE_V, IRNode.REVERSE_L}) + @IR(failOn = {IRNode.REVERSE_VL, IRNode.REVERSE_L}) public void test_reverse_long3(long[] lout, long[] linp) { for (int i = 0; i < lout.length; i+=1) { lout[i] = Long.reverse(linp[i] ^ linp[i]); @@ -121,7 +121,7 @@ public void kernel_test_reverse_long3() { } @Test - @IR(counts = {IRNode.REVERSE_V, "> 0"}) + @IR(counts = {IRNode.REVERSE_VI, "> 0"}) public void test_reverse_int1(int[] iout, int[] iinp) { for (int i = 0; i < iout.length; i+=1) { iout[i] = Integer.reverse(iinp[i]); @@ -137,7 +137,7 @@ public void kernel_test_reverse_int1() { } @Test - @IR(failOn = {IRNode.REVERSE_V, IRNode.REVERSE_I}) + @IR(failOn = {IRNode.REVERSE_VI, IRNode.REVERSE_I}) public void test_reverse_int2(int[] iout, int[] iinp) { for (int i = 0; i < iout.length; i+=1) { iout[i] = Integer.reverse(Integer.reverse(iinp[i])); @@ -153,7 +153,7 @@ public void kernel_test_reverse_int2() { } @Test - @IR(failOn = {IRNode.REVERSE_V, IRNode.REVERSE_I}) + @IR(failOn = {IRNode.REVERSE_VI, IRNode.REVERSE_I}) public void test_reverse_int3(int[] iout, int[] iinp) { for (int i = 0; i < iout.length; i+=1) { iout[i] = Integer.reverse(iinp[i] ^ iinp[i]); diff --git a/test/hotspot/jtreg/compiler/vectorization/TestReverseBytes.java b/test/hotspot/jtreg/compiler/vectorization/TestReverseBytes.java index 2d399fbd2743d..47813e2790e8e 100644 --- a/test/hotspot/jtreg/compiler/vectorization/TestReverseBytes.java +++ b/test/hotspot/jtreg/compiler/vectorization/TestReverseBytes.java @@ -74,7 +74,7 @@ public static void main(String args[]) { } @Test - @IR(counts = {IRNode.REVERSE_BYTES_V, "> 0"}) + @IR(counts = {IRNode.REVERSE_BYTES_VL, "> 0"}) public void test_reverse_bytes_long(long[] lout, long[] linp) { for (int i = 0; i < lout.length; i+=1) { lout[i] = Long.reverseBytes(linp[i]); @@ -90,7 +90,7 @@ public void kernel_test_reverse_bytes_long() { } @Test - @IR(counts = {IRNode.REVERSE_BYTES_V, "> 0"}) + @IR(counts = {IRNode.REVERSE_BYTES_VI, "> 0"}) public void test_reverse_bytes_int(int[] iout, int[] iinp) { for (int i = 0; i < iout.length; i+=1) { iout[i] = Integer.reverseBytes(iinp[i]); @@ -106,7 +106,7 @@ public void kernel_test_reverse_bytes_int() { } @Test - @IR(counts = {IRNode.REVERSE_BYTES_V, "> 0"}) + @IR(counts = {IRNode.REVERSE_BYTES_VS, "> 0"}) public void test_reverse_bytes_short(short[] sout, short[] sinp) { for (int i = 0; i < sout.length; i+=1) { sout[i] = Short.reverseBytes(sinp[i]); @@ -122,7 +122,7 @@ public void kernel_test_reverse_bytes_short() { } @Test - @IR(counts = {IRNode.REVERSE_BYTES_V, "> 0"}) + @IR(counts = {IRNode.REVERSE_BYTES_VS, "> 0"}) public void test_reverse_bytes_char(char[] cout, char[] cinp) { for (int i = 0; i < cout.length; i+=1) { cout[i] = Character.reverseBytes(cinp[i]); diff --git a/test/hotspot/jtreg/compiler/vectorization/TestSubwordReverseBytes.java b/test/hotspot/jtreg/compiler/vectorization/TestSubwordReverseBytes.java index 69e97e5c0ef06..d1baf7fae4d4f 100644 --- a/test/hotspot/jtreg/compiler/vectorization/TestSubwordReverseBytes.java +++ b/test/hotspot/jtreg/compiler/vectorization/TestSubwordReverseBytes.java @@ -54,7 +54,7 @@ public class TestSubwordReverseBytes { } @Test - @IR(failOn = {IRNode.REVERSE_BYTES_V}) + @IR(failOn = {IRNode.REVERSE_BYTES_VS}) public static int[] testShortReverseBytes() { int[] res = new int[SIZE]; for (int i = 0; i < SIZE; i++) { @@ -75,7 +75,7 @@ public static void testShort() { } @Test - @IR(failOn = {IRNode.REVERSE_BYTES_V}) + @IR(failOn = {IRNode.REVERSE_BYTES_VS}) public static int[] testCharacterReverseBytes() { int[] res = new int[SIZE]; for (int i = 0; i < SIZE; i++) { diff --git a/test/hotspot/jtreg/compiler/vectorization/runner/ArrayShiftOpTest.java b/test/hotspot/jtreg/compiler/vectorization/runner/ArrayShiftOpTest.java index 1d73221a5499a..0d53c74897905 100644 --- a/test/hotspot/jtreg/compiler/vectorization/runner/ArrayShiftOpTest.java +++ b/test/hotspot/jtreg/compiler/vectorization/runner/ArrayShiftOpTest.java @@ -98,7 +98,7 @@ public long[] longCombinedRotateShift() { @Test @IR(applyIfCPUFeatureOr = {"asimd", "true", "sse2", "true"}, - counts = {IRNode.RSHIFT_V, ">0"}) + counts = {IRNode.RSHIFT_VI, ">0"}) public int[] intShiftLargeDistConstant() { int[] res = new int[SIZE]; for (int i = 0; i < SIZE; i++) { @@ -109,7 +109,7 @@ public int[] intShiftLargeDistConstant() { @Test @IR(applyIfCPUFeatureOr = {"asimd", "true", "sse2", "true"}, - counts = {IRNode.RSHIFT_V, ">0"}) + counts = {IRNode.RSHIFT_VI, ">0"}) public int[] intShiftLargeDistInvariant() { int[] res = new int[SIZE]; for (int i = 0; i < SIZE; i++) { @@ -120,7 +120,7 @@ public int[] intShiftLargeDistInvariant() { @Test @IR(applyIfCPUFeatureOr = {"asimd", "true", "sse2", "true"}, - counts = {IRNode.RSHIFT_V, ">0"}) + counts = {IRNode.RSHIFT_VS, ">0"}) public short[] shortShiftLargeDistConstant() { short[] res = new short[SIZE]; for (int i = 0; i < SIZE; i++) { @@ -131,7 +131,7 @@ public short[] shortShiftLargeDistConstant() { @Test @IR(applyIfCPUFeatureOr = {"asimd", "true", "sse2", "true"}, - counts = {IRNode.RSHIFT_V, ">0"}) + counts = {IRNode.RSHIFT_VS, ">0"}) public short[] shortShiftLargeDistInvariant() { short[] res = new short[SIZE]; for (int i = 0; i < SIZE; i++) { @@ -142,7 +142,7 @@ public short[] shortShiftLargeDistInvariant() { @Test @IR(applyIfCPUFeatureOr = {"asimd", "true", "sse2", "true"}, - counts = {IRNode.LSHIFT_V, ">0"}) + counts = {IRNode.LSHIFT_VL, ">0"}) public long[] longShiftLargeDistConstant() { long[] res = new long[SIZE]; for (int i = 0; i < SIZE; i++) { @@ -153,7 +153,7 @@ public long[] longShiftLargeDistConstant() { @Test @IR(applyIfCPUFeatureOr = {"asimd", "true", "sse2", "true"}, - counts = {IRNode.URSHIFT_V, ">0"}) + counts = {IRNode.URSHIFT_VL, ">0"}) public long[] longShiftLargeDistInvariant() { long[] res = new long[SIZE]; for (int i = 0; i < SIZE; i++) { @@ -186,7 +186,7 @@ public short[] loopIndexShiftDistance() { @Test @IR(applyIfCPUFeatureOr = {"asimd", "true", "sse2", "true"}, - counts = {IRNode.RSHIFT_V, ">0"}) + counts = {IRNode.RSHIFT_VS, ">0"}) public short[] vectorUnsignedShiftRight() { short[] res = new short[SIZE]; for (int i = 0; i < SIZE; i++) { diff --git a/test/hotspot/jtreg/compiler/vectorization/runner/ArrayTypeConvertTest.java b/test/hotspot/jtreg/compiler/vectorization/runner/ArrayTypeConvertTest.java index f7f3dc3943141..a4640bbc302b9 100644 --- a/test/hotspot/jtreg/compiler/vectorization/runner/ArrayTypeConvertTest.java +++ b/test/hotspot/jtreg/compiler/vectorization/runner/ArrayTypeConvertTest.java @@ -132,7 +132,7 @@ public byte[] NarrowToByte() { // ---------------- Convert I/L to F/D ---------------- @Test @IR(applyIfCPUFeatureOr = {"asimd", "true", "avx", "true"}, - counts = {IRNode.VECTOR_CAST_I2X, ">0"}) + counts = {IRNode.VECTOR_CAST_I2F, IRNode.VECTOR_SIZE + "min(max_int, max_float)", ">0"}) public float[] convertIntToFloat() { float[] res = new float[SIZE]; for (int i = 0; i < SIZE; i++) { @@ -146,7 +146,7 @@ public float[] convertIntToFloat() { // The vectorization of some conversions may fail when `+AlignVector`. // We can remove the condition after JDK-8303827. applyIf = {"AlignVector", "false"}, - counts = {IRNode.VECTOR_CAST_I2X, ">0"}) + counts = {IRNode.VECTOR_CAST_I2D, IRNode.VECTOR_SIZE + "min(max_int, max_double)", ">0"}) public double[] convertIntToDouble() { double[] res = new double[SIZE]; for (int i = 0; i < SIZE; i++) { @@ -157,7 +157,7 @@ public double[] convertIntToDouble() { @Test @IR(applyIfCPUFeatureOr = {"sve", "true", "avx512dq", "true"}, - counts = {IRNode.VECTOR_CAST_L2X, ">0"}) + counts = {IRNode.VECTOR_CAST_L2F, IRNode.VECTOR_SIZE + "min(max_long, max_float)", ">0"}) public float[] convertLongToFloat() { float[] res = new float[SIZE]; for (int i = 0; i < SIZE; i++) { @@ -168,7 +168,7 @@ public float[] convertLongToFloat() { @Test @IR(applyIfCPUFeatureOr = {"asimd", "true", "avx512dq", "true"}, - counts = {IRNode.VECTOR_CAST_L2X, ">0"}) + counts = {IRNode.VECTOR_CAST_L2D, IRNode.VECTOR_SIZE + "min(max_long, max_double)", ">0"}) public double[] convertLongToDouble() { double[] res = new double[SIZE]; for (int i = 0; i < SIZE; i++) { @@ -180,7 +180,7 @@ public double[] convertLongToDouble() { // ---------------- Convert Subword-I to F/D ---------------- @Test @IR(applyIfCPUFeatureOr = {"asimd", "true", "avx2", "true"}, - counts = {IRNode.VECTOR_CAST_S2X, ">0"}) + counts = {IRNode.VECTOR_CAST_S2F, IRNode.VECTOR_SIZE + "min(max_short, max_float)", ">0"}) public float[] convertShortToFloat() { float[] res = new float[SIZE]; for (int i = 0; i < SIZE; i++) { @@ -192,7 +192,7 @@ public float[] convertShortToFloat() { @Test @IR(applyIfCPUFeatureOr = {"sve", "true", "avx2", "true"}, applyIf = {"MaxVectorSize", ">=32"}, - counts = {IRNode.VECTOR_CAST_S2X, ">0"}) + counts = {IRNode.VECTOR_CAST_S2D, IRNode.VECTOR_SIZE + "min(max_short, max_double)", ">0"}) public double[] convertShortToDouble() { double[] res = new double[SIZE]; for (int i = 0; i < SIZE; i++) { @@ -222,7 +222,7 @@ public double[] convertCharToDouble() { // ---------------- Convert F/D to I/L ---------------- @Test @IR(applyIfCPUFeatureOr = {"asimd", "true", "avx", "true"}, - counts = {IRNode.VECTOR_CAST_F2X, ">0"}) + counts = {IRNode.VECTOR_CAST_F2I, IRNode.VECTOR_SIZE + "min(max_float, max_int)", ">0"}) public int[] convertFloatToInt() { int[] res = new int[SIZE]; for (int i = 0; i < SIZE; i++) { @@ -236,7 +236,7 @@ public int[] convertFloatToInt() { // The vectorization of some conversions may fail when `+AlignVector`. // We can remove the condition after JDK-8303827. applyIf = {"AlignVector", "false"}, - counts = {IRNode.VECTOR_CAST_F2X, ">0"}) + counts = {IRNode.VECTOR_CAST_F2L, IRNode.VECTOR_SIZE + "min(max_float, max_long)", ">0"}) public long[] convertFloatToLong() { long[] res = new long[SIZE]; for (int i = 0; i < SIZE; i++) { @@ -247,7 +247,7 @@ public long[] convertFloatToLong() { @Test @IR(applyIfCPUFeatureOr = {"sve", "true", "avx", "true"}, - counts = {IRNode.VECTOR_CAST_D2X, ">0"}) + counts = {IRNode.VECTOR_CAST_D2I, IRNode.VECTOR_SIZE + "min(max_double, max_int)", ">0"}) public int[] convertDoubleToInt() { int[] res = new int[SIZE]; for (int i = 0; i < SIZE; i++) { @@ -258,7 +258,7 @@ public int[] convertDoubleToInt() { @Test @IR(applyIfCPUFeatureOr = {"asimd", "true", "avx512dq", "true"}, - counts = {IRNode.VECTOR_CAST_D2X, ">0"}) + counts = {IRNode.VECTOR_CAST_D2L, IRNode.VECTOR_SIZE + "min(max_double, max_long)", ">0"}) public long[] convertDoubleToLong() { long[] res = new long[SIZE]; for (int i = 0; i < SIZE; i++) { @@ -270,7 +270,7 @@ public long[] convertDoubleToLong() { // ---------------- Convert F/D to Subword-I ---------------- @Test @IR(applyIfCPUFeatureOr = {"asimd", "true", "avx2", "true"}, - counts = {IRNode.VECTOR_CAST_F2X, ">0"}) + counts = {IRNode.VECTOR_CAST_F2S, IRNode.VECTOR_SIZE + "min(max_float, max_short)", ">0"}) public short[] convertFloatToShort() { short[] res = new short[SIZE]; for (int i = 0; i < SIZE; i++) { @@ -281,7 +281,7 @@ public short[] convertFloatToShort() { @Test @IR(applyIfCPUFeatureOr = {"asimd", "true", "avx2", "true"}, - counts = {IRNode.VECTOR_CAST_F2X, ">0"}) + counts = {IRNode.VECTOR_CAST_F2S, IRNode.VECTOR_SIZE + "min(max_float, max_char)", ">0"}) public char[] convertFloatToChar() { char[] res = new char[SIZE]; for (int i = 0; i < SIZE; i++) { @@ -293,7 +293,7 @@ public char[] convertFloatToChar() { @Test @IR(applyIfCPUFeatureOr = {"sve", "true", "avx", "true"}, applyIf = {"MaxVectorSize", ">=32"}, - counts = {IRNode.VECTOR_CAST_D2X, ">0"}) + counts = {IRNode.VECTOR_CAST_D2S, IRNode.VECTOR_SIZE + "min(max_double, max_short)", ">0"}) public short[] convertDoubleToShort() { short[] res = new short[SIZE]; for (int i = 0; i < SIZE; i++) { @@ -305,7 +305,7 @@ public short[] convertDoubleToShort() { @Test @IR(applyIfCPUFeatureOr = {"sve", "true", "avx", "true"}, applyIf = {"MaxVectorSize", ">=32"}, - counts = {IRNode.VECTOR_CAST_D2X, ">0"}) + counts = {IRNode.VECTOR_CAST_D2S, IRNode.VECTOR_SIZE + "min(max_double, max_char)", ">0"}) public char[] convertDoubleToChar() { char[] res = new char[SIZE]; for (int i = 0; i < SIZE; i++) { @@ -320,7 +320,7 @@ public char[] convertDoubleToChar() { // The vectorization of some conversions may fail when `+AlignVector`. // We can remove the condition after JDK-8303827. applyIf = {"AlignVector", "false"}, - counts = {IRNode.VECTOR_CAST_F2X, ">0"}) + counts = {IRNode.VECTOR_CAST_F2D, IRNode.VECTOR_SIZE + "min(max_float, max_double)", ">0"}) public double[] convertFloatToDouble() { double[] res = new double[SIZE]; for (int i = 0; i < SIZE; i++) { @@ -331,7 +331,7 @@ public double[] convertFloatToDouble() { @Test @IR(applyIfCPUFeatureOr = {"asimd", "true", "avx", "true"}, - counts = {IRNode.VECTOR_CAST_D2X, ">0"}) + counts = {IRNode.VECTOR_CAST_D2F, IRNode.VECTOR_SIZE + "min(max_double, max_float)", ">0"}) public float[] convertDoubleToFloat() { float[] res = new float[SIZE]; for (int i = 0; i < SIZE; i++) { diff --git a/test/hotspot/jtreg/compiler/vectorization/runner/BasicBooleanOpTest.java b/test/hotspot/jtreg/compiler/vectorization/runner/BasicBooleanOpTest.java index b4c5108c6311e..e1d30a5c839c0 100644 --- a/test/hotspot/jtreg/compiler/vectorization/runner/BasicBooleanOpTest.java +++ b/test/hotspot/jtreg/compiler/vectorization/runner/BasicBooleanOpTest.java @@ -44,7 +44,7 @@ public class BasicBooleanOpTest extends VectorizationTestRunner { - private static final int SIZE = 543; + private static final int SIZE = 6543; private boolean[] a; private boolean[] b; @@ -72,9 +72,9 @@ public boolean[] vectorNot() { @Test @IR(applyIfCPUFeature = {"asimd", "true"}, - counts = {IRNode.AND_V, ">0"}) + counts = {IRNode.AND_VB, ">0"}) @IR(applyIfCPUFeatureAnd = {"avx512f", "false", "sse2", "true"}, - counts = {IRNode.AND_V, ">0"}) + counts = {IRNode.AND_VB, ">0"}) @IR(applyIfCPUFeature = {"avx512f", "true"}, counts = {IRNode.MACRO_LOGIC_V, ">0"}) public boolean[] vectorAnd() { @@ -87,7 +87,7 @@ public boolean[] vectorAnd() { @Test @IR(applyIfCPUFeatureOr = {"asimd", "true", "sse2", "true"}, - counts = {IRNode.OR_V, ">0"}) + counts = {IRNode.OR_VB, ">0"}) public boolean[] vectorOr() { boolean[] res = new boolean[SIZE]; for (int i = 0; i < SIZE; i++) { @@ -98,7 +98,7 @@ public boolean[] vectorOr() { @Test @IR(applyIfCPUFeatureOr = {"asimd", "true", "sse2", "true"}, - counts = {IRNode.XOR_V, ">0"}) + counts = {IRNode.XOR_VB, ">0"}) public boolean[] vectorXor() { boolean[] res = new boolean[SIZE]; for (int i = 0; i < SIZE; i++) { diff --git a/test/hotspot/jtreg/compiler/vectorization/runner/BasicByteOpTest.java b/test/hotspot/jtreg/compiler/vectorization/runner/BasicByteOpTest.java index 03716157ca6cf..1ed615317d1d4 100644 --- a/test/hotspot/jtreg/compiler/vectorization/runner/BasicByteOpTest.java +++ b/test/hotspot/jtreg/compiler/vectorization/runner/BasicByteOpTest.java @@ -34,6 +34,8 @@ * @run main/othervm -Xbootclasspath/a:. * -XX:+UnlockDiagnosticVMOptions * -XX:+WhiteBoxAPI + * -XX:CompileCommand=CompileOnly,compiler.vectorization.runner.BasicByteOpTest::* + * -XX:LoopUnrollLimit=1000 * compiler.vectorization.runner.BasicByteOpTest * * @requires vm.compiler2.enabled & vm.flagless @@ -45,7 +47,7 @@ public class BasicByteOpTest extends VectorizationTestRunner { - private static final int SIZE = 543; + private static int SIZE = 6543; private byte[] a; private byte[] b; @@ -65,7 +67,7 @@ public BasicByteOpTest() { // ---------------- Arithmetic ---------------- @Test @IR(applyIfCPUFeatureOr = {"asimd", "true", "sse2", "true"}, - counts = {IRNode.SUB_V, ">0"}) + counts = {IRNode.SUB_VB, ">0"}) public byte[] vectorNeg() { byte[] res = new byte[SIZE]; for (int i = 0; i < SIZE; i++) { @@ -76,7 +78,7 @@ public byte[] vectorNeg() { @Test @IR(applyIfCPUFeatureOr = {"asimd", "true", "ssse3", "true"}, - counts = {IRNode.ABS_V, ">0"}) + counts = {IRNode.ABS_VB, ">0"}) public byte[] vectorAbs() { byte[] res = new byte[SIZE]; for (int i = 0; i < SIZE; i++) { @@ -87,7 +89,7 @@ public byte[] vectorAbs() { @Test @IR(applyIfCPUFeatureOr = {"asimd", "true", "sse2", "true"}, - counts = {IRNode.ADD_V, ">0"}) + counts = {IRNode.ADD_VB, ">0"}) public byte[] vectorAdd() { byte[] res = new byte[SIZE]; for (int i = 0; i < SIZE; i++) { @@ -98,7 +100,7 @@ public byte[] vectorAdd() { @Test @IR(applyIfCPUFeatureOr = {"asimd", "true", "sse2", "true"}, - counts = {IRNode.SUB_V, ">0"}) + counts = {IRNode.SUB_VB, ">0"}) public byte[] vectorSub() { byte[] res = new byte[SIZE]; for (int i = 0; i < SIZE; i++) { @@ -109,7 +111,7 @@ public byte[] vectorSub() { @Test @IR(applyIfCPUFeatureOr = {"asimd", "true", "sse4.1", "true"}, - counts = {IRNode.MUL_V, ">0"}) + counts = {IRNode.MUL_VB, ">0"}) public byte[] vectorMul() { byte[] res = new byte[SIZE]; for (int i = 0; i < SIZE; i++) { @@ -120,7 +122,7 @@ public byte[] vectorMul() { @Test @IR(applyIfCPUFeatureOr = {"asimd", "true", "sse4.1", "true"}, - counts = {IRNode.MUL_V, ">0", IRNode.ADD_V, ">0"}) + counts = {IRNode.MUL_VB, ">0", IRNode.ADD_VB, ">0"}) public byte[] vectorMulAdd() { byte[] res = new byte[SIZE]; for (int i = 0; i < SIZE; i++) { @@ -131,7 +133,7 @@ public byte[] vectorMulAdd() { @Test @IR(applyIfCPUFeatureOr = {"asimd", "true", "sse4.1", "true"}, - counts = {IRNode.MUL_V, ">0", IRNode.SUB_V, ">0"}) + counts = {IRNode.MUL_VB, ">0", IRNode.SUB_VB, ">0"}) public byte[] vectorMulSub() { byte[] res = new byte[SIZE]; for (int i = 0; i < SIZE; i++) { @@ -143,7 +145,7 @@ public byte[] vectorMulSub() { // ---------------- Logic ---------------- @Test @IR(applyIfCPUFeatureOr = {"asimd", "true", "sse2", "true"}, - counts = {IRNode.XOR_V, ">0"}) + counts = {IRNode.XOR_VB, ">0"}) public byte[] vectorNot() { byte[] res = new byte[SIZE]; for (int i = 0; i < SIZE; i++) { @@ -154,7 +156,7 @@ public byte[] vectorNot() { @Test @IR(applyIfCPUFeatureOr = {"asimd", "true", "sse2", "true"}, - counts = {IRNode.AND_V, ">0"}) + counts = {IRNode.AND_VB, ">0"}) public byte[] vectorAnd() { byte[] res = new byte[SIZE]; for (int i = 0; i < SIZE; i++) { @@ -165,7 +167,7 @@ public byte[] vectorAnd() { @Test @IR(applyIfCPUFeatureOr = {"asimd", "true", "sse2", "true"}, - counts = {IRNode.OR_V, ">0"}) + counts = {IRNode.OR_VB, ">0"}) public byte[] vectorOr() { byte[] res = new byte[SIZE]; for (int i = 0; i < SIZE; i++) { @@ -176,7 +178,7 @@ public byte[] vectorOr() { @Test @IR(applyIfCPUFeatureOr = {"asimd", "true", "sse2", "true"}, - counts = {IRNode.XOR_V, ">0"}) + counts = {IRNode.XOR_VB, ">0"}) public byte[] vectorXor() { byte[] res = new byte[SIZE]; for (int i = 0; i < SIZE; i++) { @@ -188,7 +190,7 @@ public byte[] vectorXor() { // ---------------- Shift ---------------- @Test @IR(applyIfCPUFeatureOr = {"asimd", "true", "sse4.1", "true"}, - counts = {IRNode.LSHIFT_V, ">0"}) + counts = {IRNode.LSHIFT_VB, ">0"}) public byte[] vectorShiftLeft() { byte[] res = new byte[SIZE]; for (int i = 0; i < SIZE; i++) { @@ -199,7 +201,7 @@ public byte[] vectorShiftLeft() { @Test @IR(applyIfCPUFeatureOr = {"asimd", "true", "sse4.1", "true"}, - counts = {IRNode.RSHIFT_V, ">0"}) + counts = {IRNode.RSHIFT_VB, ">0"}) public byte[] vectorSignedShiftRight() { byte[] res = new byte[SIZE]; for (int i = 0; i < SIZE; i++) { @@ -210,7 +212,7 @@ public byte[] vectorSignedShiftRight() { @Test @IR(applyIfCPUFeatureOr = {"asimd", "true", "sse4.1", "true"}, - counts = {IRNode.RSHIFT_V, ">0"}) + counts = {IRNode.RSHIFT_VB, ">0"}) public byte[] vectorUnsignedShiftRight() { byte[] res = new byte[SIZE]; for (int i = 0; i < SIZE; i++) { diff --git a/test/hotspot/jtreg/compiler/vectorization/runner/BasicCharOpTest.java b/test/hotspot/jtreg/compiler/vectorization/runner/BasicCharOpTest.java index e43f5c888a647..4b91360fc540a 100644 --- a/test/hotspot/jtreg/compiler/vectorization/runner/BasicCharOpTest.java +++ b/test/hotspot/jtreg/compiler/vectorization/runner/BasicCharOpTest.java @@ -67,7 +67,7 @@ public BasicCharOpTest() { // ---------------- Arithmetic ---------------- @Test @IR(applyIfCPUFeatureOr = {"asimd", "true", "sse2", "true"}, - counts = {IRNode.SUB_V, ">0"}) + counts = {IRNode.SUB_VS, ">0"}) public char[] vectorNeg() { char[] res = new char[SIZE]; for (int i = 0; i < SIZE; i++) { @@ -79,7 +79,7 @@ public char[] vectorNeg() { @Test @IR(applyIfCPUFeatureOr = {"asimd", "true", "ssse3", "true"}, counts = {IRNode.STORE_VECTOR, ">0"}) - @IR(failOn = {IRNode.ABS_V}) + @IR(failOn = {IRNode.ABS_VI, IRNode.ABS_VB, IRNode.ABS_VL}) // AVS_VC does not exist public char[] vectorAbs() { char[] res = new char[SIZE]; for (int i = 0; i < SIZE; i++) { @@ -90,7 +90,7 @@ public char[] vectorAbs() { @Test @IR(applyIfCPUFeatureOr = {"asimd", "true", "sse2", "true"}, - counts = {IRNode.ADD_V, ">0"}) + counts = {IRNode.ADD_VS, ">0"}) // char add same as for short public char[] vectorAdd() { char[] res = new char[SIZE]; for (int i = 0; i < SIZE; i++) { @@ -101,7 +101,7 @@ public char[] vectorAdd() { @Test @IR(applyIfCPUFeatureOr = {"asimd", "true", "sse2", "true"}, - counts = {IRNode.SUB_V, ">0"}) + counts = {IRNode.SUB_VS, ">0"}) public char[] vectorSub() { char[] res = new char[SIZE]; for (int i = 0; i < SIZE; i++) { @@ -112,7 +112,7 @@ public char[] vectorSub() { @Test @IR(applyIfCPUFeatureOr = {"asimd", "true", "sse2", "true"}, - counts = {IRNode.MUL_V, ">0"}) + counts = {IRNode.MUL_VS, ">0"}) public char[] vectorMul() { char[] res = new char[SIZE]; for (int i = 0; i < SIZE; i++) { @@ -123,7 +123,8 @@ public char[] vectorMul() { @Test @IR(applyIfCPUFeatureOr = {"asimd", "true", "sse2", "true"}, - counts = {IRNode.MUL_V, ">0", IRNode.ADD_V, ">0"}) + counts = {IRNode.MUL_VS, ">0", + IRNode.ADD_VS, ">0"}) // char add same as for short public char[] vectorMulAdd() { char[] res = new char[SIZE]; for (int i = 0; i < SIZE; i++) { @@ -134,7 +135,7 @@ public char[] vectorMulAdd() { @Test @IR(applyIfCPUFeatureOr = {"asimd", "true", "sse2", "true"}, - counts = {IRNode.MUL_V, ">0", IRNode.SUB_V, ">0"}) + counts = {IRNode.MUL_VS, ">0", IRNode.SUB_VS, ">0"}) public char[] vectorMulSub() { char[] res = new char[SIZE]; for (int i = 0; i < SIZE; i++) { @@ -146,7 +147,7 @@ public char[] vectorMulSub() { // ---------------- Logic ---------------- @Test @IR(applyIfCPUFeatureOr = {"asimd", "true", "sse2", "true"}, - counts = {IRNode.XOR_V, ">0"}) + counts = {IRNode.XOR_VS, ">0"}) public char[] vectorNot() { char[] res = new char[SIZE]; for (int i = 0; i < SIZE; i++) { @@ -157,7 +158,7 @@ public char[] vectorNot() { @Test @IR(applyIfCPUFeatureOr = {"asimd", "true", "sse2", "true"}, - counts = {IRNode.AND_V, ">0"}) + counts = {IRNode.AND_VS, ">0"}) public char[] vectorAnd() { char[] res = new char[SIZE]; for (int i = 0; i < SIZE; i++) { @@ -168,7 +169,7 @@ public char[] vectorAnd() { @Test @IR(applyIfCPUFeatureOr = {"asimd", "true", "sse2", "true"}, - counts = {IRNode.OR_V, ">0"}) + counts = {IRNode.OR_VS, ">0"}) public char[] vectorOr() { char[] res = new char[SIZE]; for (int i = 0; i < SIZE; i++) { @@ -179,7 +180,7 @@ public char[] vectorOr() { @Test @IR(applyIfCPUFeatureOr = {"asimd", "true", "sse2", "true"}, - counts = {IRNode.XOR_V, ">0"}) + counts = {IRNode.XOR_VS, ">0"}) public char[] vectorXor() { char[] res = new char[SIZE]; for (int i = 0; i < SIZE; i++) { @@ -191,7 +192,7 @@ public char[] vectorXor() { // ---------------- Shift ---------------- @Test @IR(applyIfCPUFeatureOr = {"asimd", "true", "sse2", "true"}, - counts = {IRNode.LSHIFT_V, ">0"}) + counts = {IRNode.LSHIFT_VC, ">0"}) public char[] vectorShiftLeft() { char[] res = new char[SIZE]; for (int i = 0; i < SIZE; i++) { @@ -202,7 +203,7 @@ public char[] vectorShiftLeft() { @Test @IR(applyIfCPUFeatureOr = {"asimd", "true", "sse2", "true"}, - counts = {IRNode.URSHIFT_V, ">0"}) + counts = {IRNode.URSHIFT_VC, ">0"}) public char[] vectorSignedShiftRight() { char[] res = new char[SIZE]; for (int i = 0; i < SIZE; i++) { @@ -213,7 +214,7 @@ public char[] vectorSignedShiftRight() { @Test @IR(applyIfCPUFeatureOr = {"asimd", "true", "sse2", "true"}, - counts = {IRNode.URSHIFT_V, ">0"}) + counts = {IRNode.URSHIFT_VC, ">0"}) public char[] vectorUnsignedShiftRight() { char[] res = new char[SIZE]; for (int i = 0; i < SIZE; i++) { @@ -225,7 +226,7 @@ public char[] vectorUnsignedShiftRight() { // ------------- ReverseBytes ------------- @Test @IR(applyIfCPUFeatureOr = {"asimd", "true", "avx2", "true"}, - counts = {IRNode.REVERSE_BYTES_V, ">0"}) + counts = {IRNode.REVERSE_BYTES_VS, ">0"}) public char[] reverseBytesWithChar() { char[] res = new char[SIZE]; for (int i = 0; i < SIZE; i++) { diff --git a/test/hotspot/jtreg/compiler/vectorization/runner/BasicDoubleOpTest.java b/test/hotspot/jtreg/compiler/vectorization/runner/BasicDoubleOpTest.java index 60dc8a5e148fa..cddeee1d35123 100644 --- a/test/hotspot/jtreg/compiler/vectorization/runner/BasicDoubleOpTest.java +++ b/test/hotspot/jtreg/compiler/vectorization/runner/BasicDoubleOpTest.java @@ -65,7 +65,7 @@ public BasicDoubleOpTest() { // ---------------- Arithmetic ---------------- @Test @IR(applyIfCPUFeatureOr = {"asimd", "true", "sse2", "true"}, - counts = {IRNode.NEG_V, ">0"}) + counts = {IRNode.NEG_VD, ">0"}) public double[] vectorNeg() { double[] res = new double[SIZE]; for (int i = 0; i < SIZE; i++) { @@ -76,7 +76,7 @@ public double[] vectorNeg() { @Test @IR(applyIfCPUFeatureOr = {"asimd", "true", "sse2", "true"}, - counts = {IRNode.ABS_V, ">0"}) + counts = {IRNode.ABS_VD, ">0"}) public double[] vectorAbs() { double[] res = new double[SIZE]; for (int i = 0; i < SIZE; i++) { @@ -87,7 +87,7 @@ public double[] vectorAbs() { @Test @IR(applyIfCPUFeatureOr = {"asimd", "true", "avx", "true"}, - counts = {IRNode.SQRT_V, ">0"}) + counts = {IRNode.SQRT_VD, ">0"}) public double[] vectorSqrt() { double[] res = new double[SIZE]; for (int i = 0; i < SIZE; i++) { @@ -131,7 +131,7 @@ public double[] vectorRint() { @Test @IR(applyIfCPUFeatureOr = {"asimd", "true", "sse2", "true"}, - counts = {IRNode.ADD_V, ">0"}) + counts = {IRNode.ADD_VD, ">0"}) public double[] vectorAdd() { double[] res = new double[SIZE]; for (int i = 0; i < SIZE; i++) { @@ -142,7 +142,7 @@ public double[] vectorAdd() { @Test @IR(applyIfCPUFeatureOr = {"asimd", "true", "sse2", "true"}, - counts = {IRNode.SUB_V, ">0"}) + counts = {IRNode.SUB_VD, ">0"}) public double[] vectorSub() { double[] res = new double[SIZE]; for (int i = 0; i < SIZE; i++) { @@ -153,7 +153,7 @@ public double[] vectorSub() { @Test @IR(applyIfCPUFeatureOr = {"asimd", "true", "sse2", "true"}, - counts = {IRNode.MUL_V, ">0"}) + counts = {IRNode.MUL_VD, ">0"}) public double[] vectorMul() { double[] res = new double[SIZE]; for (int i = 0; i < SIZE; i++) { @@ -164,7 +164,7 @@ public double[] vectorMul() { @Test @IR(applyIfCPUFeatureOr = {"asimd", "true", "sse2", "true"}, - counts = {IRNode.DIV_V, ">0"}) + counts = {IRNode.DIV_VD, ">0"}) public double[] vectorDiv() { double[] res = new double[SIZE]; for (int i = 0; i < SIZE; i++) { @@ -175,7 +175,7 @@ public double[] vectorDiv() { @Test @IR(applyIfCPUFeatureOr = {"asimd", "true", "avx", "true"}, - counts = {IRNode.MAX_V, ">0"}) + counts = {IRNode.MAX_VD, ">0"}) public double[] vectorMax() { double[] res = new double[SIZE]; for (int i = 0; i < SIZE; i++) { @@ -186,7 +186,7 @@ public double[] vectorMax() { @Test @IR(applyIfCPUFeatureOr = {"asimd", "true", "avx", "true"}, - counts = {IRNode.MIN_V, ">0"}) + counts = {IRNode.MIN_VD, ">0"}) public double[] vectorMin() { double[] res = new double[SIZE]; for (int i = 0; i < SIZE; i++) { @@ -197,9 +197,9 @@ public double[] vectorMin() { @Test @IR(applyIfCPUFeature = {"asimd", "true"}, - counts = {IRNode.FMA_V, ">0", IRNode.VFMLA, ">0"}) + counts = {IRNode.FMA_VD, ">0", IRNode.VFMLA, ">0"}) @IR(applyIfCPUFeatureAnd = {"fma", "true", "avx", "true"}, - counts = {IRNode.FMA_V, ">0"}) + counts = {IRNode.FMA_VD, ">0"}) public double[] vectorMulAdd() { double[] res = new double[SIZE]; for (int i = 0; i < SIZE; i++) { @@ -210,9 +210,9 @@ public double[] vectorMulAdd() { @Test @IR(applyIfCPUFeature = {"asimd", "true"}, - counts = {IRNode.FMA_V, ">0", IRNode.VFMLS, ">0"}) + counts = {IRNode.FMA_VD, ">0", IRNode.VFMLS, ">0"}) @IR(applyIfCPUFeatureAnd = {"fma", "true", "avx", "true"}, - counts = {IRNode.FMA_V, ">0"}) + counts = {IRNode.FMA_VD, ">0"}) public double[] vectorMulSub1() { double[] res = new double[SIZE]; for (int i = 0; i < SIZE; i++) { @@ -223,9 +223,9 @@ public double[] vectorMulSub1() { @Test @IR(applyIfCPUFeature = {"asimd", "true"}, - counts = {IRNode.FMA_V, ">0", IRNode.VFMLS, ">0"}) + counts = {IRNode.FMA_VD, ">0", IRNode.VFMLS, ">0"}) @IR(applyIfCPUFeatureAnd = {"fma", "true", "avx", "true"}, - counts = {IRNode.FMA_V, ">0"}) + counts = {IRNode.FMA_VD, ">0"}) public double[] vectorMulSub2() { double[] res = new double[SIZE]; for (int i = 0; i < SIZE; i++) { @@ -236,11 +236,11 @@ public double[] vectorMulSub2() { @Test @IR(applyIfCPUFeature = {"asimd", "true"}, - counts = {IRNode.FMA_V, ">0"}) + counts = {IRNode.FMA_VD, ">0"}) @IR(applyIfCPUFeature = {"sve", "true"}, counts = {IRNode.VFNMLA, ">0"}) @IR(applyIfCPUFeatureAnd = {"fma", "true", "avx", "true"}, - counts = {IRNode.FMA_V, ">0"}) + counts = {IRNode.FMA_VD, ">0"}) public double[] vectorNegateMulAdd1() { double[] res = new double[SIZE]; for (int i = 0; i < SIZE; i++) { @@ -251,11 +251,11 @@ public double[] vectorNegateMulAdd1() { @Test @IR(applyIfCPUFeature = {"asimd", "true"}, - counts = {IRNode.FMA_V, ">0"}) + counts = {IRNode.FMA_VD, ">0"}) @IR(applyIfCPUFeature = {"sve", "true"}, counts = {IRNode.VFNMLA, ">0"}) @IR(applyIfCPUFeatureAnd = {"fma", "true", "avx", "true"}, - counts = {IRNode.FMA_V, ">0"}) + counts = {IRNode.FMA_VD, ">0"}) public double[] vectorNegateMulAdd2() { double[] res = new double[SIZE]; for (int i = 0; i < SIZE; i++) { @@ -266,9 +266,9 @@ public double[] vectorNegateMulAdd2() { @Test @IR(applyIfCPUFeature = {"asimd", "true"}, - counts = {IRNode.FMA_V, ">0"}) + counts = {IRNode.FMA_VD, ">0"}) @IR(applyIfCPUFeatureAnd = {"fma", "true", "avx", "true"}, - counts = {IRNode.FMA_V, ">0"}) + counts = {IRNode.FMA_VD, ">0"}) public double[] vectorNegateMulSub() { double[] res = new double[SIZE]; for (int i = 0; i < SIZE; i++) { diff --git a/test/hotspot/jtreg/compiler/vectorization/runner/BasicFloatOpTest.java b/test/hotspot/jtreg/compiler/vectorization/runner/BasicFloatOpTest.java index b52fb5a1364ec..3bd7bb2a15d56 100644 --- a/test/hotspot/jtreg/compiler/vectorization/runner/BasicFloatOpTest.java +++ b/test/hotspot/jtreg/compiler/vectorization/runner/BasicFloatOpTest.java @@ -65,7 +65,7 @@ public BasicFloatOpTest() { // ---------------- Arithmetic ---------------- @Test @IR(applyIfCPUFeatureOr = {"asimd", "true", "sse", "true"}, - counts = {IRNode.NEG_V, ">0"}) + counts = {IRNode.NEG_VF, ">0"}) public float[] vectorNeg() { float[] res = new float[SIZE]; for (int i = 0; i < SIZE; i++) { @@ -76,7 +76,7 @@ public float[] vectorNeg() { @Test @IR(applyIfCPUFeatureOr = {"asimd", "true", "sse", "true"}, - counts = {IRNode.ABS_V, ">0"}) + counts = {IRNode.ABS_VF, ">0"}) public float[] vectorAbs() { float[] res = new float[SIZE]; for (int i = 0; i < SIZE; i++) { @@ -87,7 +87,7 @@ public float[] vectorAbs() { @Test @IR(applyIfCPUFeatureOr = {"asimd", "true", "avx", "true"}, - counts = {IRNode.SQRT_V, ">0"}) + counts = {IRNode.SQRT_VF, ">0"}) public float[] vectorSqrt() { float[] res = new float[SIZE]; for (int i = 0; i < SIZE; i++) { @@ -98,7 +98,7 @@ public float[] vectorSqrt() { @Test @IR(applyIfCPUFeatureOr = {"asimd", "true", "sse2", "true"}, - counts = {IRNode.ADD_V, ">0"}) + counts = {IRNode.ADD_VF, ">0"}) public float[] vectorAdd() { float[] res = new float[SIZE]; for (int i = 0; i < SIZE; i++) { @@ -109,7 +109,7 @@ public float[] vectorAdd() { @Test @IR(applyIfCPUFeatureOr = {"asimd", "true", "sse2", "true"}, - counts = {IRNode.SUB_V, ">0"}) + counts = {IRNode.SUB_VF, ">0"}) public float[] vectorSub() { float[] res = new float[SIZE]; for (int i = 0; i < SIZE; i++) { @@ -120,7 +120,7 @@ public float[] vectorSub() { @Test @IR(applyIfCPUFeatureOr = {"asimd", "true", "sse2", "true"}, - counts = {IRNode.MUL_V, ">0"}) + counts = {IRNode.MUL_VF, ">0"}) public float[] vectorMul() { float[] res = new float[SIZE]; for (int i = 0; i < SIZE; i++) { @@ -131,7 +131,7 @@ public float[] vectorMul() { @Test @IR(applyIfCPUFeatureOr = {"asimd", "true", "sse2", "true"}, - counts = {IRNode.DIV_V, ">0"}) + counts = {IRNode.DIV_VF, ">0"}) public float[] vectorDiv() { float[] res = new float[SIZE]; for (int i = 0; i < SIZE; i++) { @@ -142,7 +142,7 @@ public float[] vectorDiv() { @Test @IR(applyIfCPUFeatureOr = {"asimd", "true", "avx", "true"}, - counts = {IRNode.MAX_V, ">0"}) + counts = {IRNode.MAX_VF, ">0"}) public float[] vectorMax() { float[] res = new float[SIZE]; for (int i = 0; i < SIZE; i++) { @@ -153,7 +153,7 @@ public float[] vectorMax() { @Test @IR(applyIfCPUFeatureOr = {"asimd", "true", "avx", "true"}, - counts = {IRNode.MIN_V, ">0"}) + counts = {IRNode.MIN_VF, ">0"}) public float[] vectorMin() { float[] res = new float[SIZE]; for (int i = 0; i < SIZE; i++) { @@ -164,9 +164,9 @@ public float[] vectorMin() { @Test @IR(applyIfCPUFeature = {"asimd", "true"}, - counts = {IRNode.FMA_V, ">0", IRNode.VFMLA, ">0"}) + counts = {IRNode.FMA_VF, ">0", IRNode.VFMLA, ">0"}) @IR(applyIfCPUFeatureAnd = {"fma", "true", "avx", "true"}, - counts = {IRNode.FMA_V, ">0"}) + counts = {IRNode.FMA_VF, ">0"}) public float[] vectorMulAdd() { float[] res = new float[SIZE]; for (int i = 0; i < SIZE; i++) { @@ -177,9 +177,9 @@ public float[] vectorMulAdd() { @Test @IR(applyIfCPUFeature = {"asimd", "true"}, - counts = {IRNode.FMA_V, ">0", IRNode.VFMLS, ">0"}) + counts = {IRNode.FMA_VF, ">0", IRNode.VFMLS, ">0"}) @IR(applyIfCPUFeatureAnd = {"fma", "true", "avx", "true"}, - counts = {IRNode.FMA_V, ">0"}) + counts = {IRNode.FMA_VF, ">0"}) public float[] vectorMulSub1() { float[] res = new float[SIZE]; for (int i = 0; i < SIZE; i++) { @@ -190,9 +190,9 @@ public float[] vectorMulSub1() { @Test @IR(applyIfCPUFeature = {"asimd", "true"}, - counts = {IRNode.FMA_V, ">0", IRNode.VFMLS, ">0"}) + counts = {IRNode.FMA_VF, ">0", IRNode.VFMLS, ">0"}) @IR(applyIfCPUFeatureAnd = {"fma", "true", "avx", "true"}, - counts = {IRNode.FMA_V, ">0"}) + counts = {IRNode.FMA_VF, ">0"}) public float[] vectorMulSub2() { float[] res = new float[SIZE]; for (int i = 0; i < SIZE; i++) { @@ -203,11 +203,11 @@ public float[] vectorMulSub2() { @Test @IR(applyIfCPUFeature = {"asimd", "true"}, - counts = {IRNode.FMA_V, ">0"}) + counts = {IRNode.FMA_VF, ">0"}) @IR(applyIfCPUFeature = {"sve", "true"}, counts = {IRNode.VFNMLA, ">0"}) @IR(applyIfCPUFeatureAnd = {"fma", "true", "avx", "true"}, - counts = {IRNode.FMA_V, ">0"}) + counts = {IRNode.FMA_VF, ">0"}) public float[] vectorNegateMulAdd1() { float[] res = new float[SIZE]; for (int i = 0; i < SIZE; i++) { @@ -218,11 +218,11 @@ public float[] vectorNegateMulAdd1() { @Test @IR(applyIfCPUFeature = {"asimd", "true"}, - counts = {IRNode.FMA_V, ">0"}) + counts = {IRNode.FMA_VF, ">0"}) @IR(applyIfCPUFeature = {"sve", "true"}, counts = {IRNode.VFNMLA, ">0"}) @IR(applyIfCPUFeatureAnd = {"fma", "true", "avx", "true"}, - counts = {IRNode.FMA_V, ">0"}) + counts = {IRNode.FMA_VF, ">0"}) public float[] vectorNegateMulAdd2() { float[] res = new float[SIZE]; for (int i = 0; i < SIZE; i++) { @@ -233,9 +233,9 @@ public float[] vectorNegateMulAdd2() { @Test @IR(applyIfCPUFeature = {"asimd", "true"}, - counts = {IRNode.FMA_V, ">0"}) + counts = {IRNode.FMA_VF, ">0"}) @IR(applyIfCPUFeatureAnd = {"fma", "true", "avx", "true"}, - counts = {IRNode.FMA_V, ">0"}) + counts = {IRNode.FMA_VF, ">0"}) public float[] vectorNegateMulSub() { float[] res = new float[SIZE]; for (int i = 0; i < SIZE; i++) { diff --git a/test/hotspot/jtreg/compiler/vectorization/runner/BasicIntOpTest.java b/test/hotspot/jtreg/compiler/vectorization/runner/BasicIntOpTest.java index 4d86cd113459e..d392214c96959 100644 --- a/test/hotspot/jtreg/compiler/vectorization/runner/BasicIntOpTest.java +++ b/test/hotspot/jtreg/compiler/vectorization/runner/BasicIntOpTest.java @@ -65,7 +65,7 @@ public BasicIntOpTest() { // ---------------- Arithmetic ---------------- @Test @IR(applyIfCPUFeatureOr = {"asimd", "true", "sse2", "true"}, - counts = {IRNode.SUB_V, ">0"}) + counts = {IRNode.SUB_VI, ">0"}) public int[] vectorNeg() { int[] res = new int[SIZE]; for (int i = 0; i < SIZE; i++) { @@ -76,7 +76,7 @@ public int[] vectorNeg() { @Test @IR(applyIfCPUFeatureOr = {"asimd", "true", "ssse3", "true"}, - counts = {IRNode.ABS_V, ">0"}) + counts = {IRNode.ABS_VI, ">0"}) public int[] vectorAbs() { int[] res = new int[SIZE]; for (int i = 0; i < SIZE; i++) { @@ -87,7 +87,7 @@ public int[] vectorAbs() { @Test @IR(applyIfCPUFeatureOr = {"asimd", "true", "sse2", "true"}, - counts = {IRNode.ADD_V, ">0"}) + counts = {IRNode.ADD_VI, ">0"}) public int[] vectorAdd() { int[] res = new int[SIZE]; for (int i = 0; i < SIZE; i++) { @@ -98,7 +98,7 @@ public int[] vectorAdd() { @Test @IR(applyIfCPUFeatureOr = {"asimd", "true", "sse2", "true"}, - counts = {IRNode.SUB_V, ">0"}) + counts = {IRNode.SUB_VI, ">0"}) public int[] vectorSub() { int[] res = new int[SIZE]; for (int i = 0; i < SIZE; i++) { @@ -109,7 +109,7 @@ public int[] vectorSub() { @Test @IR(applyIfCPUFeatureOr = {"asimd", "true", "sse4.1", "true"}, - counts = {IRNode.MUL_V, ">0"}) + counts = {IRNode.MUL_VI, ">0"}) public int[] vectorMul() { int[] res = new int[SIZE]; for (int i = 0; i < SIZE; i++) { @@ -120,7 +120,7 @@ public int[] vectorMul() { @Test @IR(applyIfCPUFeatureOr = {"asimd", "true", "sse4.1", "true"}, - counts = {IRNode.MUL_V, ">0", IRNode.ADD_V, ">0"}) + counts = {IRNode.MUL_VI, ">0", IRNode.ADD_VI, ">0"}) public int[] vectorMulAdd() { int[] res = new int[SIZE]; for (int i = 0; i < SIZE; i++) { @@ -131,7 +131,7 @@ public int[] vectorMulAdd() { @Test @IR(applyIfCPUFeatureOr = {"asimd", "true", "sse4.1", "true"}, - counts = {IRNode.MUL_V, ">0", IRNode.SUB_V, ">0"}) + counts = {IRNode.MUL_VI, ">0", IRNode.SUB_VI, ">0"}) public int[] vectorMulSub() { int[] res = new int[SIZE]; for (int i = 0; i < SIZE; i++) { @@ -154,7 +154,7 @@ public int[] vectorPopCount() { // ---------------- Logic ---------------- @Test @IR(applyIfCPUFeatureOr = {"asimd", "true", "sse2", "true"}, - counts = {IRNode.XOR_V, ">0"}) + counts = {IRNode.XOR_VI, ">0"}) public int[] vectorNot() { int[] res = new int[SIZE]; for (int i = 0; i < SIZE; i++) { @@ -165,7 +165,7 @@ public int[] vectorNot() { @Test @IR(applyIfCPUFeatureOr = {"asimd", "true", "sse2", "true"}, - counts = {IRNode.AND_V, ">0"}) + counts = {IRNode.AND_VI, ">0"}) public int[] vectorAnd() { int[] res = new int[SIZE]; for (int i = 0; i < SIZE; i++) { @@ -176,7 +176,7 @@ public int[] vectorAnd() { @Test @IR(applyIfCPUFeatureOr = {"asimd", "true", "sse2", "true"}, - counts = {IRNode.OR_V, ">0"}) + counts = {IRNode.OR_VI, ">0"}) public int[] vectorOr() { int[] res = new int[SIZE]; for (int i = 0; i < SIZE; i++) { @@ -187,7 +187,7 @@ public int[] vectorOr() { @Test @IR(applyIfCPUFeatureOr = {"asimd", "true", "sse2", "true"}, - counts = {IRNode.XOR_V, ">0"}) + counts = {IRNode.XOR_VI, ">0"}) public int[] vectorXor() { int[] res = new int[SIZE]; for (int i = 0; i < SIZE; i++) { @@ -199,7 +199,7 @@ public int[] vectorXor() { // ---------------- Shift ---------------- @Test @IR(applyIfCPUFeatureOr = {"asimd", "true", "sse2", "true"}, - counts = {IRNode.LSHIFT_V, ">0"}) + counts = {IRNode.LSHIFT_VI, ">0"}) public int[] vectorShiftLeft() { int[] res = new int[SIZE]; for (int i = 0; i < SIZE; i++) { @@ -210,7 +210,7 @@ public int[] vectorShiftLeft() { @Test @IR(applyIfCPUFeatureOr = {"asimd", "true", "sse2", "true"}, - counts = {IRNode.RSHIFT_V, ">0"}) + counts = {IRNode.RSHIFT_VI, ">0"}) public int[] vectorSignedShiftRight() { int[] res = new int[SIZE]; for (int i = 0; i < SIZE; i++) { @@ -221,7 +221,7 @@ public int[] vectorSignedShiftRight() { @Test @IR(applyIfCPUFeatureOr = {"asimd", "true", "sse2", "true"}, - counts = {IRNode.URSHIFT_V, ">0"}) + counts = {IRNode.URSHIFT_VI, ">0"}) public int[] vectorUnsignedShiftRight() { int[] res = new int[SIZE]; for (int i = 0; i < SIZE; i++) { diff --git a/test/hotspot/jtreg/compiler/vectorization/runner/BasicLongOpTest.java b/test/hotspot/jtreg/compiler/vectorization/runner/BasicLongOpTest.java index 8adce9eceffb4..1e41ae97ea286 100644 --- a/test/hotspot/jtreg/compiler/vectorization/runner/BasicLongOpTest.java +++ b/test/hotspot/jtreg/compiler/vectorization/runner/BasicLongOpTest.java @@ -66,7 +66,7 @@ public BasicLongOpTest() { // ---------------- Arithmetic ---------------- @Test @IR(applyIfCPUFeatureOr = {"asimd", "true", "sse2", "true"}, - counts = {IRNode.SUB_V, ">0"}) + counts = {IRNode.SUB_VL, ">0"}) public long[] vectorNeg() { long[] res = new long[SIZE]; for (int i = 0; i < SIZE; i++) { @@ -77,7 +77,7 @@ public long[] vectorNeg() { @Test @IR(applyIfCPUFeatureOr = {"asimd", "true", "avx512vl", "true"}, - counts = {IRNode.ABS_V, ">0"}) + counts = {IRNode.ABS_VL, ">0"}) public long[] vectorAbs() { long[] res = new long[SIZE]; for (int i = 0; i < SIZE; i++) { @@ -88,7 +88,7 @@ public long[] vectorAbs() { @Test @IR(applyIfCPUFeatureOr = {"asimd", "true", "sse2", "true"}, - counts = {IRNode.ADD_V, ">0"}) + counts = {IRNode.ADD_VL, ">0"}) public long[] vectorAdd() { long[] res = new long[SIZE]; for (int i = 0; i < SIZE; i++) { @@ -99,7 +99,7 @@ public long[] vectorAdd() { @Test @IR(applyIfCPUFeatureOr = {"asimd", "true", "sse2", "true"}, - counts = {IRNode.SUB_V, ">0"}) + counts = {IRNode.SUB_VL, ">0"}) public long[] vectorSub() { long[] res = new long[SIZE]; for (int i = 0; i < SIZE; i++) { @@ -110,7 +110,7 @@ public long[] vectorSub() { @Test @IR(applyIfCPUFeatureOr = {"sve", "true", "avx512dq", "true"}, - counts = {IRNode.MUL_V, ">0"}) + counts = {IRNode.MUL_VL, ">0"}) public long[] vectorMul() { long[] res = new long[SIZE]; for (int i = 0; i < SIZE; i++) { @@ -121,9 +121,9 @@ public long[] vectorMul() { @Test @IR(applyIfCPUFeatureOr = {"sve", "true", "sse4.1", "true"}, - counts = {IRNode.ADD_V, ">0"}) + counts = {IRNode.ADD_VL, ">0"}) @IR(applyIfCPUFeatureOr = {"sve", "true", "sse4.1", "true"}, - counts = {IRNode.MUL_V, ">0"}) + counts = {IRNode.MUL_VL, ">0"}) public long[] vectorMulAdd() { long[] res = new long[SIZE]; for (int i = 0; i < SIZE; i++) { @@ -134,7 +134,7 @@ public long[] vectorMulAdd() { @Test @IR(applyIfCPUFeatureOr = {"sve", "true", "sse4.1", "true"}, - counts = {IRNode.MUL_V, ">0", IRNode.SUB_V, ">0"}) + counts = {IRNode.MUL_VL, ">0", IRNode.SUB_VL, ">0"}) public long[] vectorMulSub() { long[] res = new long[SIZE]; for (int i = 0; i < SIZE; i++) { @@ -146,7 +146,7 @@ public long[] vectorMulSub() { // ---------------- Logic ---------------- @Test @IR(applyIfCPUFeatureOr = {"asimd", "true", "sse2", "true"}, - counts = {IRNode.XOR_V, ">0"}) + counts = {IRNode.XOR_VL, ">0"}) public long[] vectorNot() { long[] res = new long[SIZE]; for (int i = 0; i < SIZE; i++) { @@ -157,7 +157,7 @@ public long[] vectorNot() { @Test @IR(applyIfCPUFeatureOr = {"asimd", "true", "sse2", "true"}, - counts = {IRNode.AND_V, ">0"}) + counts = {IRNode.AND_VL, ">0"}) public long[] vectorAnd() { long[] res = new long[SIZE]; for (int i = 0; i < SIZE; i++) { @@ -168,7 +168,7 @@ public long[] vectorAnd() { @Test @IR(applyIfCPUFeatureOr = {"asimd", "true", "sse2", "true"}, - counts = {IRNode.OR_V, ">0"}) + counts = {IRNode.OR_VL, ">0"}) public long[] vectorOr() { long[] res = new long[SIZE]; for (int i = 0; i < SIZE; i++) { @@ -179,7 +179,7 @@ public long[] vectorOr() { @Test @IR(applyIfCPUFeatureOr = {"asimd", "true", "sse2", "true"}, - counts = {IRNode.XOR_V, ">0"}) + counts = {IRNode.XOR_VL, ">0"}) public long[] vectorXor() { long[] res = new long[SIZE]; for (int i = 0; i < SIZE; i++) { @@ -191,7 +191,7 @@ public long[] vectorXor() { // ---------------- Shift ---------------- @Test @IR(applyIfCPUFeatureOr = {"asimd", "true", "sse2", "true"}, - counts = {IRNode.LSHIFT_V, ">0"}) + counts = {IRNode.LSHIFT_VL, ">0"}) public long[] vectorShiftLeft() { long[] res = new long[SIZE]; for (int i = 0; i < SIZE; i++) { @@ -202,7 +202,7 @@ public long[] vectorShiftLeft() { @Test @IR(applyIfCPUFeatureOr = {"asimd", "true", "sse2", "true"}, - counts = {IRNode.RSHIFT_V, ">0"}) + counts = {IRNode.RSHIFT_VL, ">0"}) public long[] vectorSignedShiftRight() { long[] res = new long[SIZE]; for (int i = 0; i < SIZE; i++) { @@ -213,7 +213,7 @@ public long[] vectorSignedShiftRight() { @Test @IR(applyIfCPUFeatureOr = {"asimd", "true", "sse2", "true"}, - counts = {IRNode.URSHIFT_V, ">0"}) + counts = {IRNode.URSHIFT_VL, ">0"}) public long[] vectorUnsignedShiftRight() { long[] res = new long[SIZE]; for (int i = 0; i < SIZE; i++) { diff --git a/test/hotspot/jtreg/compiler/vectorization/runner/BasicShortOpTest.java b/test/hotspot/jtreg/compiler/vectorization/runner/BasicShortOpTest.java index b2a096758bca2..b47267e550786 100644 --- a/test/hotspot/jtreg/compiler/vectorization/runner/BasicShortOpTest.java +++ b/test/hotspot/jtreg/compiler/vectorization/runner/BasicShortOpTest.java @@ -67,7 +67,7 @@ public BasicShortOpTest() { // ---------------- Arithmetic ---------------- @Test @IR(applyIfCPUFeatureOr = {"asimd", "true", "sse2", "true"}, - counts = {IRNode.SUB_V, ">0"}) + counts = {IRNode.SUB_VS, ">0"}) public short[] vectorNeg() { short[] res = new short[SIZE]; for (int i = 0; i < SIZE; i++) { @@ -78,7 +78,7 @@ public short[] vectorNeg() { @Test @IR(applyIfCPUFeatureOr = {"asimd", "true", "ssse3", "true"}, - counts = {IRNode.ABS_V, ">0"}) + counts = {IRNode.ABS_VS, ">0"}) public short[] vectorAbs() { short[] res = new short[SIZE]; for (int i = 0; i < SIZE; i++) { @@ -89,7 +89,7 @@ public short[] vectorAbs() { @Test @IR(applyIfCPUFeatureOr = {"asimd", "true", "sse2", "true"}, - counts = {IRNode.ADD_V, ">0"}) + counts = {IRNode.ADD_VS, ">0"}) public short[] vectorAdd() { short[] res = new short[SIZE]; for (int i = 0; i < SIZE; i++) { @@ -100,7 +100,7 @@ public short[] vectorAdd() { @Test @IR(applyIfCPUFeatureOr = {"asimd", "true", "sse2", "true"}, - counts = {IRNode.SUB_V, ">0"}) + counts = {IRNode.SUB_VS, ">0"}) public short[] vectorSub() { short[] res = new short[SIZE]; for (int i = 0; i < SIZE; i++) { @@ -111,7 +111,7 @@ public short[] vectorSub() { @Test @IR(applyIfCPUFeatureOr = {"asimd", "true", "sse2", "true"}, - counts = {IRNode.MUL_V, ">0"}) + counts = {IRNode.MUL_VS, ">0"}) public short[] vectorMul() { short[] res = new short[SIZE]; for (int i = 0; i < SIZE; i++) { @@ -122,7 +122,7 @@ public short[] vectorMul() { @Test @IR(applyIfCPUFeatureOr = {"asimd", "true", "sse2", "true"}, - counts = {IRNode.MUL_V, ">0", IRNode.ADD_V, ">0"}) + counts = {IRNode.MUL_VS, ">0", IRNode.ADD_VS, ">0"}) public short[] vectorMulAdd() { short[] res = new short[SIZE]; for (int i = 0; i < SIZE; i++) { @@ -133,7 +133,7 @@ public short[] vectorMulAdd() { @Test @IR(applyIfCPUFeatureOr = {"asimd", "true", "sse2", "true"}, - counts = {IRNode.MUL_V, ">0", IRNode.SUB_V, ">0"}) + counts = {IRNode.MUL_VS, ">0", IRNode.SUB_VS, ">0"}) public short[] vectorMulSub() { short[] res = new short[SIZE]; for (int i = 0; i < SIZE; i++) { @@ -145,7 +145,7 @@ public short[] vectorMulSub() { // ---------------- Logic ---------------- @Test @IR(applyIfCPUFeatureOr = {"asimd", "true", "sse2", "true"}, - counts = {IRNode.XOR_V, ">0"}) + counts = {IRNode.XOR_VS, ">0"}) public short[] vectorNot() { short[] res = new short[SIZE]; for (int i = 0; i < SIZE; i++) { @@ -156,7 +156,7 @@ public short[] vectorNot() { @Test @IR(applyIfCPUFeatureOr = {"asimd", "true", "sse2", "true"}, - counts = {IRNode.AND_V, ">0"}) + counts = {IRNode.AND_VS, ">0"}) public short[] vectorAnd() { short[] res = new short[SIZE]; for (int i = 0; i < SIZE; i++) { @@ -167,7 +167,7 @@ public short[] vectorAnd() { @Test @IR(applyIfCPUFeatureOr = {"asimd", "true", "sse2", "true"}, - counts = {IRNode.OR_V, ">0"}) + counts = {IRNode.OR_VS, ">0"}) public short[] vectorOr() { short[] res = new short[SIZE]; for (int i = 0; i < SIZE; i++) { @@ -178,7 +178,7 @@ public short[] vectorOr() { @Test @IR(applyIfCPUFeatureOr = {"asimd", "true", "sse2", "true"}, - counts = {IRNode.XOR_V, ">0"}) + counts = {IRNode.XOR_VS, ">0"}) public short[] vectorXor() { short[] res = new short[SIZE]; for (int i = 0; i < SIZE; i++) { @@ -190,7 +190,7 @@ public short[] vectorXor() { // ---------------- Shift ---------------- @Test @IR(applyIfCPUFeatureOr = {"asimd", "true", "sse2", "true"}, - counts = {IRNode.LSHIFT_V, ">0"}) + counts = {IRNode.LSHIFT_VS, ">0"}) public short[] vectorShiftLeft() { short[] res = new short[SIZE]; for (int i = 0; i < SIZE; i++) { @@ -201,7 +201,7 @@ public short[] vectorShiftLeft() { @Test @IR(applyIfCPUFeatureOr = {"asimd", "true", "sse2", "true"}, - counts = {IRNode.RSHIFT_V, ">0"}) + counts = {IRNode.RSHIFT_VS, ">0"}) public short[] vectorSignedShiftRight() { short[] res = new short[SIZE]; for (int i = 0; i < SIZE; i++) { @@ -237,7 +237,7 @@ public short[] vectorMax() { @Test @IR(applyIfCPUFeatureOr = {"asimd", "true", "sse2", "true"}, - counts = {IRNode.RSHIFT_V, ">0"}) + counts = {IRNode.RSHIFT_VS, ">0"}) public short[] vectorUnsignedShiftRight() { short[] res = new short[SIZE]; for (int i = 0; i < SIZE; i++) { @@ -249,7 +249,7 @@ public short[] vectorUnsignedShiftRight() { // ------------- ReverseBytes ------------- @Test @IR(applyIfCPUFeatureOr = {"asimd", "true", "avx2", "true"}, - counts = {IRNode.REVERSE_BYTES_V, ">0"}) + counts = {IRNode.REVERSE_BYTES_VS, ">0"}) public short[] reverseBytesWithShort() { short[] res = new short[SIZE]; for (int i = 0; i < SIZE; i++) { diff --git a/test/hotspot/jtreg/compiler/vectorization/runner/LoopArrayIndexComputeTest.java b/test/hotspot/jtreg/compiler/vectorization/runner/LoopArrayIndexComputeTest.java index cc35213e5db33..2ef686c2fd547 100644 --- a/test/hotspot/jtreg/compiler/vectorization/runner/LoopArrayIndexComputeTest.java +++ b/test/hotspot/jtreg/compiler/vectorization/runner/LoopArrayIndexComputeTest.java @@ -48,7 +48,7 @@ public class LoopArrayIndexComputeTest extends VectorizationTestRunner { - private static final int SIZE = 543; + private static final int SIZE = 6543; private int[] ints; private short[] shorts; @@ -95,7 +95,7 @@ public int[] indexPlusConstant() { @IR(applyIfCPUFeatureOr = {"sve", "true", "avx2", "true"}, counts = {IRNode.STORE_VECTOR, ">0"}) @IR(applyIfCPUFeatureOr = {"sve", "true", "avx2", "true"}, - counts = {IRNode.MUL_V, ">0"}) + counts = {IRNode.MUL_VI, ">0"}) public int[] indexMinusConstant() { int[] res = new int[SIZE]; for (int i = SIZE / 2; i < SIZE; i++) { @@ -108,7 +108,7 @@ public int[] indexMinusConstant() { @IR(applyIfCPUFeatureOr = {"asimd", "true", "sse4.1", "true"}, counts = {IRNode.STORE_VECTOR, ">0"}) @IR(applyIfCPUFeatureOr = {"asimd", "true", "sse4.1", "true"}, - counts = {IRNode.MUL_V, ">0"}) + counts = {IRNode.MUL_VI, ">0"}) public int[] indexPlusInvariant() { int[] res = new int[SIZE]; System.arraycopy(ints, 0, res, 0, SIZE); @@ -122,7 +122,7 @@ public int[] indexPlusInvariant() { @IR(applyIfCPUFeatureOr = {"sve", "true", "avx2", "true"}, counts = {IRNode.STORE_VECTOR, ">0"}) @IR(applyIfCPUFeatureOr = {"sve", "true", "avx2", "true"}, - counts = {IRNode.MUL_V, ">0"}) + counts = {IRNode.MUL_VI, ">0"}) public int[] indexMinusInvariant() { int[] res = new int[SIZE]; System.arraycopy(ints, 0, res, 0, SIZE); @@ -136,7 +136,7 @@ public int[] indexMinusInvariant() { @IR(applyIfCPUFeatureOr = {"asimd", "true", "sse4.1", "true"}, counts = {IRNode.STORE_VECTOR, ">0"}) @IR(applyIfCPUFeatureOr = {"asimd", "true", "sse4.1", "true"}, - counts = {IRNode.MUL_V, ">0"}) + counts = {IRNode.MUL_VI, ">0"}) public int[] indexWithInvariantAndConstant() { int[] res = new int[SIZE]; System.arraycopy(ints, 0, res, 0, SIZE); @@ -150,7 +150,7 @@ public int[] indexWithInvariantAndConstant() { @IR(applyIfCPUFeatureOr = {"asimd", "true", "sse2", "true"}, counts = {IRNode.STORE_VECTOR, ">0"}) @IR(applyIfCPUFeatureOr = {"asimd", "true", "sse2", "true"}, - counts = {IRNode.SUB_V, ">0"}) + counts = {IRNode.SUB_VI, ">0"}) public int[] indexWithTwoInvariants() { int[] res = new int[SIZE]; System.arraycopy(ints, 0, res, 0, SIZE); diff --git a/test/hotspot/jtreg/compiler/vectorization/runner/LoopReductionOpTest.java b/test/hotspot/jtreg/compiler/vectorization/runner/LoopReductionOpTest.java index 99f889ae74ca7..72667a66d8212 100644 --- a/test/hotspot/jtreg/compiler/vectorization/runner/LoopReductionOpTest.java +++ b/test/hotspot/jtreg/compiler/vectorization/runner/LoopReductionOpTest.java @@ -79,9 +79,8 @@ public LoopReductionOpTest() { @Test @IR(applyIfCPUFeatureOr = {"asimd", "true", "sse3", "true"}, - counts = {IRNode.LOAD_VECTOR, ">0"}) - @IR(applyIfCPUFeatureOr = {"asimd", "true", "sse3", "true"}, - counts = {IRNode.ADD_REDUCTION_V, ">0"}) + counts = {IRNode.LOAD_VECTOR_I, ">0", + IRNode.ADD_REDUCTION_V, ">0"}) public int reductionAddSumOfArray() { int res = 0; for (int i = 0; i < SIZE; i++) { @@ -121,9 +120,8 @@ public int reductionAddLoopInv() { @Test @IR(applyIfCPUFeatureOr = {"sve", "true", "avx2", "true"}, - counts = {IRNode.LOAD_VECTOR, ">0"}) - @IR(applyIfCPUFeatureOr = {"sve", "true", "avx2", "true"}, - counts = {IRNode.ADD_REDUCTION_V, ">0"}) + counts = {IRNode.LOAD_VECTOR_I, ">0", + IRNode.ADD_REDUCTION_V, ">0"}) public int reductionAddSumOfMultiple() { int res = 0; for (int i = 0; i < SIZE; i++) { diff --git a/test/hotspot/jtreg/testlibrary_tests/ir_framework/examples/IRExample.java b/test/hotspot/jtreg/testlibrary_tests/ir_framework/examples/IRExample.java index 2c1a228f76fcb..539673a6c286c 100644 --- a/test/hotspot/jtreg/testlibrary_tests/ir_framework/examples/IRExample.java +++ b/test/hotspot/jtreg/testlibrary_tests/ir_framework/examples/IRExample.java @@ -119,6 +119,109 @@ public void mixFailOnAndCounts() { public void compilePhases() { iFld = 42; } + + // Rules for vector nodes. + @Test + // By default, we search for the maximal size possible + @IR(counts = {IRNode.LOAD_VECTOR_I, "> 0"}, + applyIfCPUFeatureOr = {"sse2", "true", "asimd", "true"}) + // We can also specify that we want the maximum explicitly + @IR(counts = {IRNode.LOAD_VECTOR_I, IRNode.VECTOR_SIZE_MAX, "> 0"}, + applyIfCPUFeatureOr = {"sse2", "true", "asimd", "true"}) + // Explicitly take the maximum size for this type (here int) + @IR(counts = {IRNode.LOAD_VECTOR_I, IRNode.VECTOR_SIZE + "max_for_type", "> 0"}, + applyIfCPUFeatureOr = {"sse2", "true", "asimd", "true"}) + // Exlicitly take the maximum size for the int type + @IR(counts = {IRNode.LOAD_VECTOR_I, IRNode.VECTOR_SIZE + "max_int", "> 0"}, + applyIfCPUFeatureOr = {"sse2", "true", "asimd", "true"}) + // As a last resort, we can match with any size + @IR(counts = {IRNode.LOAD_VECTOR_I, IRNode.VECTOR_SIZE_ANY, "> 0"}, + applyIfCPUFeatureOr = {"sse2", "true", "asimd", "true"}) + // Specify comma separated list of numbers, match for any of them + @IR(counts = {IRNode.LOAD_VECTOR_I, IRNode.VECTOR_SIZE + "2,4,8,16,32,64", "> 0"}, + applyIfCPUFeatureOr = {"sse2", "true", "asimd", "true"}) + // Two or more arguments to min(...): the minimal value is applied + @IR(counts = {IRNode.LOAD_VECTOR_I, IRNode.VECTOR_SIZE + "min(max_for_type, max_int, LoopMaxUnroll, 64)", "> 0"}, + applyIfCPUFeatureOr = {"sse2", "true", "asimd", "true"}) + static int[] testVectorNode() { + int[] a = new int[1024*8]; + for (int i = 0; i < a.length; i++) { + a[i]++; + } + return a; + } + + // Rules for vector nodes. + @Test + // By default, we search for the maximal size possible + @IR(counts = {IRNode.LOAD_VECTOR_F, "> 0"}, + applyIfCPUFeatureOr = {"sse2", "true", "asimd", "true"}) + // In some cases, we can know the exact size, here 16 + @IR(counts = {IRNode.LOAD_VECTOR_F, IRNode.VECTOR_SIZE_16, "> 0"}, + applyIf = {"MaxVectorSize", "=64"}, + applyIfCPUFeatureOr = {"sse2", "true", "asimd", "true"}) + @IR(counts = {IRNode.LOAD_VECTOR_F, IRNode.VECTOR_SIZE_8, "> 0"}, + applyIf = {"MaxVectorSize", "=32"}, + applyIfCPUFeatureOr = {"sse2", "true", "asimd", "true"}) + // In some cases, we can know the exact size, here 4 + @IR(counts = {IRNode.LOAD_VECTOR_F, IRNode.VECTOR_SIZE_4, "> 0"}, + applyIf = {"MaxVectorSize", "=16"}, + applyIfCPUFeatureOr = {"sse2", "true", "asimd", "true"}) + static float[] testVectorNodeExactSize1() { + float[] a = new float[1024*8]; + for (int i = 0; i < a.length; i++) { + a[i]++; + } + return a; + } + + // Rules for vector nodes. Same as badTestVectorNodeSize but with good rules. + @Test + // In some cases, we can know the exact size, here 4 + @IR(counts = {IRNode.LOAD_VECTOR_F, IRNode.VECTOR_SIZE_4, "> 0"}, + applyIf = {"MaxVectorSize", ">=16"}, + applyIfCPUFeatureOr = {"sse2", "true", "asimd", "true"}) + // Hence, we know any other sizes are impossible. + // We can also specify that explicitly for failOn + @IR(failOn = {IRNode.LOAD_VECTOR_F, IRNode.VECTOR_SIZE_2, + IRNode.LOAD_VECTOR_F, IRNode.VECTOR_SIZE_8, + IRNode.LOAD_VECTOR_F, IRNode.VECTOR_SIZE_16, + IRNode.LOAD_VECTOR_F, IRNode.VECTOR_SIZE_32, + IRNode.LOAD_VECTOR_F, IRNode.VECTOR_SIZE_64, + IRNode.LOAD_VECTOR_F, IRNode.VECTOR_SIZE + "2,8,16,32,64"}, + applyIf = {"MaxVectorSize", ">=16"}, + applyIfCPUFeatureOr = {"sse2", "true", "asimd", "true"}) + static float[] testVectorNodeExactSize2() { + float[] a = new float[1024*8]; + for (int i = 0; i < a.length/8; i++) { + a[i*8 + 0]++; // block of 4, then gap of 4 + a[i*8 + 1]++; + a[i*8 + 2]++; + a[i*8 + 3]++; + } + return a; + } + + @Test + // Here, we can pack at most 8 given the 8-blocks and 8-gaps. + // But we can also never pack more than max_float + @IR(counts = {IRNode.LOAD_VECTOR_F, IRNode.VECTOR_SIZE + "min(8, max_float)", "> 0"}, + applyIf = {"MaxVectorSize", ">=16"}, + applyIfCPUFeatureOr = {"sse2", "true", "asimd", "true"}) + static float[] testVectorNodeSizeMinClause() { + float[] a = new float[1024*8]; + for (int i = 0; i < a.length/16; i++) { + a[i*16 + 0]++; // block of 8, then gap of 8 + a[i*16 + 1]++; + a[i*16 + 2]++; + a[i*16 + 3]++; + a[i*16 + 4]++; + a[i*16 + 5]++; + a[i*16 + 6]++; + a[i*16 + 7]++; + } + return a; + } } class FailingExamples { @@ -194,4 +297,29 @@ public void testNotCompiled() { public void badStandAloneNotCompiled() { testNotCompiled(); } + + // Failing rules for vector nodes. Same as testVectorNodeExactSize2 but with bad rules. + @Test + // By default we look for the IRNode.VECTOR_SIZE_MAX, which is more than 4. + @IR(counts = {IRNode.LOAD_VECTOR_F, "> 0"}, + applyIf = {"MaxVectorSize", ">16"}, + applyIfCPUFeatureOr = {"sse2", "true", "asimd", "true"}) + // By default, we look for IRNode.VECTOR_SIZE_ANY. But there are some of size 4. + @IR(failOn = {IRNode.LOAD_VECTOR_F}, + applyIf = {"MaxVectorSize", ">=16"}, + applyIfCPUFeatureOr = {"sse2", "true", "asimd", "true"}) + // By default, we look for IRNode.VECTOR_SIZE_ANY. But there are at least two of size 4. + @IR(counts = {IRNode.LOAD_VECTOR_F, "<2"}, + applyIf = {"MaxVectorSize", ">=16"}, + applyIfCPUFeatureOr = {"sse2", "true", "asimd", "true"}) + static float[] badTestVectorNodeSize() { + float[] a = new float[1024*8]; + for (int i = 0; i < a.length/8; i++) { + a[i*8 + 0]++; // block of 4, then gap of 4 + a[i*8 + 1]++; + a[i*8 + 2]++; + a[i*8 + 3]++; + } + return a; + } } diff --git a/test/hotspot/jtreg/testlibrary_tests/ir_framework/tests/TestBadFormat.java b/test/hotspot/jtreg/testlibrary_tests/ir_framework/tests/TestBadFormat.java index 9dd605b3f6503..c0d43f768f5f9 100644 --- a/test/hotspot/jtreg/testlibrary_tests/ir_framework/tests/TestBadFormat.java +++ b/test/hotspot/jtreg/testlibrary_tests/ir_framework/tests/TestBadFormat.java @@ -999,7 +999,7 @@ public void emtpyUserProvidedPostfix() {} public void missingCountString() {} @Test - @FailCount(45) + @FailCount(51) @IR(counts = {IRNode.STORE, IRNode.STORE}) @IR(counts = {IRNode.STORE, IRNode.STORE, IRNode.STORE, IRNode.STORE}) @IR(counts = {IRNode.STORE_OF_CLASS, "Foo", IRNode.STORE}) @@ -1025,6 +1025,12 @@ public void missingCountString() {} @IR(counts = {IRNode.STORE, " > 3.0"}) @IR(counts = {IRNode.STORE, " > a3"}) @IR(counts = {IRNode.STORE, " > 0x1"}) + @IR(counts = {IRNode.STORE, "!= 1000"}) + @IR(counts = {IRNode.STORE, "< 0"}) + @IR(counts = {IRNode.STORE, "< 1"}) + @IR(counts = {IRNode.STORE, "<= 0"}) + @IR(counts = {IRNode.STORE, "> -1"}) + @IR(counts = {IRNode.STORE, ">= 0"}) @IR(counts = {IRNode.STORE_OF_CLASS, "Foo", "<"}) @IR(counts = {IRNode.STORE_OF_CLASS, "Foo", "!"}) @IR(counts = {IRNode.STORE_OF_CLASS, "Foo", "!3"}) @@ -1046,6 +1052,38 @@ public void missingCountString() {} @IR(counts = {IRNode.STORE_OF_CLASS, "Foo", " > a3"}) @IR(counts = {IRNode.STORE_OF_CLASS, "Foo", " > 0x1"}) public void wrongCountString() {} + + @Test + @FailCount(8) + @IR(counts = {IRNode.LOAD_VECTOR_I, "> 0"}, + applyIfCPUFeatureOr = {"sse2", "true", "asimd", "true"}) + @IR(counts = {IRNode.LOAD_VECTOR_I, IRNode.VECTOR_SIZE_MAX, "> 0"}, // valid + applyIfCPUFeatureOr = {"sse2", "true", "asimd", "true"}) + @IR(counts = {IRNode.LOAD_VECTOR_I, IRNode.VECTOR_SIZE_ANY, "> 0"}, // valid + applyIfCPUFeatureOr = {"sse2", "true", "asimd", "true"}) + @IR(counts = {IRNode.LOAD_VECTOR_I, IRNode.VECTOR_SIZE + "", "> 0"}, + applyIfCPUFeatureOr = {"sse2", "true", "asimd", "true"}) + @IR(counts = {IRNode.LOAD_VECTOR_I, IRNode.VECTOR_SIZE + "xxx", "> 0"}, + applyIfCPUFeatureOr = {"sse2", "true", "asimd", "true"}) + @IR(counts = {IRNode.LOAD_VECTOR_I, IRNode.VECTOR_SIZE + "min()", "> 0"}, + applyIfCPUFeatureOr = {"sse2", "true", "asimd", "true"}) + @IR(counts = {IRNode.LOAD_VECTOR_I, IRNode.VECTOR_SIZE + "min(max_for_type)", "> 0"}, + applyIfCPUFeatureOr = {"sse2", "true", "asimd", "true"}) + @IR(counts = {IRNode.LOAD_VECTOR_I, IRNode.VECTOR_SIZE + "2,4,8,16,32,64,max_int", "> 0"}, + applyIfCPUFeatureOr = {"sse2", "true", "asimd", "true"}) + @IR(counts = {IRNode.LOAD_VECTOR_I, IRNode.VECTOR_SIZE + "2,4,8,16,32,64,-3", "> 0"}, + applyIfCPUFeatureOr = {"sse2", "true", "asimd", "true"}) + @IR(counts = {IRNode.LOAD_VECTOR_I, IRNode.VECTOR_SIZE + "min(max_for_type, xxx)", "> 0"}, + applyIfCPUFeatureOr = {"sse2", "true", "asimd", "true"}) + @IR(counts = {IRNode.LOAD_VECTOR_I, IRNode.VECTOR_SIZE + "min(max_for_type, min(max_for_type, max_for_type))", "> 0"}, + applyIfCPUFeatureOr = {"sse2", "true", "asimd", "true"}) + public int[] badVectorNodeSize() { + int[] a = new int[1024*8]; + for (int i = 0; i < a.length; i++) { + a[i]++; + } + return a; + } } class BadIRNodeForPhase { @@ -1096,18 +1134,18 @@ public void loops() {} @Test @FailCount(6) - @IR(failOn = IRNode.LOAD_VECTOR, phase = CompilePhase.BEFORE_REMOVEUSELESS) // works + @IR(failOn = IRNode.LOAD_VECTOR_I, phase = CompilePhase.BEFORE_REMOVEUSELESS) // works @IR(failOn = IRNode.STORE_VECTOR, phase = CompilePhase.BEFORE_REMOVEUSELESS) // works - @IR(failOn = IRNode.VECTOR_CAST_B2X, phase = CompilePhase.BEFORE_REMOVEUSELESS) // works - @IR(failOn = IRNode.LOAD_VECTOR, phase = CompilePhase.BEFORE_MATCHING) // works + @IR(failOn = IRNode.VECTOR_CAST_B2I, phase = CompilePhase.BEFORE_REMOVEUSELESS) // works + @IR(failOn = IRNode.LOAD_VECTOR_I, phase = CompilePhase.BEFORE_MATCHING) // works @IR(failOn = IRNode.STORE_VECTOR, phase = CompilePhase.BEFORE_MATCHING) // works - @IR(failOn = IRNode.VECTOR_CAST_B2X, phase = CompilePhase.BEFORE_MATCHING) // works - @IR(failOn = IRNode.LOAD_VECTOR, phase = {CompilePhase.MATCHING, CompilePhase.MATCHING}) + @IR(failOn = IRNode.VECTOR_CAST_B2I, phase = CompilePhase.BEFORE_MATCHING) // works + @IR(failOn = IRNode.LOAD_VECTOR_I, phase = {CompilePhase.MATCHING, CompilePhase.MATCHING}) @IR(failOn = IRNode.STORE_VECTOR, phase = {CompilePhase.MATCHING, CompilePhase.MATCHING}) - @IR(failOn = IRNode.VECTOR_CAST_B2X, phase = {CompilePhase.MATCHING, CompilePhase.MATCHING}) - @IR(failOn = IRNode.LOAD_VECTOR, phase = CompilePhase.FINAL_CODE) + @IR(failOn = IRNode.VECTOR_CAST_B2I, phase = {CompilePhase.MATCHING, CompilePhase.MATCHING}) + @IR(failOn = IRNode.LOAD_VECTOR_I, phase = CompilePhase.FINAL_CODE) @IR(failOn = IRNode.STORE_VECTOR, phase = CompilePhase.FINAL_CODE) - @IR(failOn = IRNode.VECTOR_CAST_B2X, phase = CompilePhase.FINAL_CODE) + @IR(failOn = IRNode.VECTOR_CAST_B2I, phase = CompilePhase.FINAL_CODE) public void vector() {} @Test diff --git a/test/hotspot/jtreg/testlibrary_tests/ir_framework/tests/TestIRMatching.java b/test/hotspot/jtreg/testlibrary_tests/ir_framework/tests/TestIRMatching.java index 5160ccb8e3b78..4794a9c812723 100644 --- a/test/hotspot/jtreg/testlibrary_tests/ir_framework/tests/TestIRMatching.java +++ b/test/hotspot/jtreg/testlibrary_tests/ir_framework/tests/TestIRMatching.java @@ -100,12 +100,12 @@ public static void main(String[] args) { GoodFailOnRegexConstraint.create(MultipleFailOnBad.class, "fail10()", 1, 2, 3) ); - runCheck(BadCountsConstraint.create(BadCount.class, "bad1()", 1, 1, "Load"), + runCheck(BadCountsConstraint.create(BadCount.class, "bad1()", 1, 2, "Load"), GoodCountsConstraint.create(BadCount.class, "bad1()", 2), GoodCountsConstraint.create(BadCount.class, "bad2()", 1), - BadCountsConstraint.create(BadCount.class, "bad2()", 2, 1, "Store"), - BadCountsConstraint.create(BadCount.class, "bad3()", 1, 1, "Load"), - BadCountsConstraint.create(BadCount.class, "bad3()", 2, 1, "Store") + BadCountsConstraint.create(BadCount.class, "bad2()", 2, 2, "Store"), + BadCountsConstraint.create(BadCount.class, "bad3()", 1, 2, "Load"), + BadCountsConstraint.create(BadCount.class, "bad3()", 2, 2, "Store") ); runCheck(GoodRuleConstraint.create(Calls.class, "calls()", 1), @@ -629,10 +629,6 @@ class CountComparisons { IRNode.STORE, "<=1", IRNode.STORE, " <= 1", IRNode.STORE, " <= 1", - IRNode.STORE, "!= 0", - IRNode.STORE, "!=0", - IRNode.STORE, " != 0", - IRNode.STORE, " != 0", IRNode.STORE, "> 0", IRNode.STORE, ">0", IRNode.STORE, " > 0", @@ -823,27 +819,32 @@ public void good11() { class BadCount { int iFld; + int iFld2; int result; + int result2; @Test - @IR(counts = {IRNode.LOAD, "!= 1"}) // fail + @IR(counts = {IRNode.LOAD, "> 1000"}) // fail @IR(counts = {IRNode.STORE, "> 0"}) public void bad1() { result = iFld; + result2 = iFld2; } @Test - @IR(counts = {IRNode.LOAD, "1"}) // fail - @IR(counts = {IRNode.STORE, "< 1"}) + @IR(counts = {IRNode.LOAD, "2"}) // fail + @IR(counts = {IRNode.STORE, "< 2"}) public void bad2() { result = iFld; + result2 = iFld2; } @Test @IR(counts = {IRNode.LOAD, "0"}) // fail - @IR(counts = {IRNode.STORE, " <= 0"}) // fail + @IR(counts = {IRNode.STORE, " <= 1"}) // fail public void bad3() { result = iFld; + result2 = iFld2; } } diff --git a/test/hotspot/jtreg/testlibrary_tests/ir_framework/tests/TestSafepointWhilePrinting.java b/test/hotspot/jtreg/testlibrary_tests/ir_framework/tests/TestSafepointWhilePrinting.java index ee5ee38e331fc..99de3c1510ca7 100644 --- a/test/hotspot/jtreg/testlibrary_tests/ir_framework/tests/TestSafepointWhilePrinting.java +++ b/test/hotspot/jtreg/testlibrary_tests/ir_framework/tests/TestSafepointWhilePrinting.java @@ -75,6 +75,15 @@ public void test() throws IOException { testCompilePhaseBackToBackFirst,1 testCompilePhaseBackToBackLast,1 ----- END ----- + ##### IRMatchingVMInfo - used by TestFramework ##### + : + cpuFeatures:empty_cpu_info + MaxVectorSize:64 + MaxVectorSizeIsDefault:1 + LoopMaxUnroll:64 + UseAVX:1 + UseAVXIsDefault:1 + ----- END VMInfo ----- """; TestClassParser testClassParser = new TestClassParser(TestSafepointWhilePrinting.class); Matchable testClassMatchable = testClassParser.parse(hotspotPidFileName, irEncoding);