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8153837: AArch64: Handle special cases for MaxINode & MinINode
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Reviewed-by: fyang, aph
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Dmitry Chuyko committed Jan 18, 2023
1 parent 754f6e6 commit b3684f4
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Showing 3 changed files with 498 additions and 39 deletions.
339 changes: 305 additions & 34 deletions src/hotspot/cpu/aarch64/aarch64.ad
Expand Up @@ -11164,7 +11164,6 @@ instruct rShiftL_reg_imm(iRegLNoSp dst, iRegL src1, immI src2) %{
// BEGIN This section of the file is automatically generated. Do not edit --------------
// This section is generated from aarch64_ad.m4


// This pattern is automatically generated from aarch64_ad.m4
// DO NOT EDIT ANYTHING IN THIS SECTION OF THE FILE
instruct regL_not_reg(iRegLNoSp dst,
Expand Down Expand Up @@ -12980,6 +12979,7 @@ instruct ubfizIConvI2LAndI(iRegLNoSp dst, iRegI src, immI_bitmask msk)


// Rotations

// This pattern is automatically generated from aarch64_ad.m4
// DO NOT EDIT ANYTHING IN THIS SECTION OF THE FILE
instruct extrOrL(iRegLNoSp dst, iRegL src1, iRegL src2, immI lshift, immI rshift, rFlagsReg cr)
Expand Down Expand Up @@ -13051,7 +13051,6 @@ instruct extrAddI(iRegINoSp dst, iRegIorL2I src1, iRegIorL2I src2, immI lshift,
ins_pipe(ialu_reg_reg_extr);
%}


// This pattern is automatically generated from aarch64_ad.m4
// DO NOT EDIT ANYTHING IN THIS SECTION OF THE FILE
instruct rorI_imm(iRegINoSp dst, iRegI src, immI shift)
Expand Down Expand Up @@ -13765,6 +13764,298 @@ instruct SubExtI_uxth_and_shift(iRegINoSp dst, iRegIorL2I src1, iRegIorL2I src2,
ins_pipe(ialu_reg_reg_shift);
%}

// This pattern is automatically generated from aarch64_ad.m4
// DO NOT EDIT ANYTHING IN THIS SECTION OF THE FILE
instruct cmovI_reg_reg_lt(iRegINoSp dst, iRegI src1, iRegI src2, rFlagsReg cr)
%{
effect(DEF dst, USE src1, USE src2, USE cr);
ins_cost(INSN_COST * 2);
format %{ "cselw $dst, $src1, $src2 lt\t" %}

ins_encode %{
__ cselw($dst$$Register,
$src1$$Register,
$src2$$Register,
Assembler::LT);
%}
ins_pipe(icond_reg_reg);
%}

// This pattern is automatically generated from aarch64_ad.m4
// DO NOT EDIT ANYTHING IN THIS SECTION OF THE FILE
instruct cmovI_reg_reg_gt(iRegINoSp dst, iRegI src1, iRegI src2, rFlagsReg cr)
%{
effect(DEF dst, USE src1, USE src2, USE cr);
ins_cost(INSN_COST * 2);
format %{ "cselw $dst, $src1, $src2 gt\t" %}

ins_encode %{
__ cselw($dst$$Register,
$src1$$Register,
$src2$$Register,
Assembler::GT);
%}
ins_pipe(icond_reg_reg);
%}

// This pattern is automatically generated from aarch64_ad.m4
// DO NOT EDIT ANYTHING IN THIS SECTION OF THE FILE
instruct cmovI_reg_imm0_lt(iRegINoSp dst, iRegI src1, rFlagsReg cr)
%{
effect(DEF dst, USE src1, USE cr);
ins_cost(INSN_COST * 2);
format %{ "cselw $dst, $src1, zr lt\t" %}

ins_encode %{
__ cselw($dst$$Register,
$src1$$Register,
zr,
Assembler::LT);
%}
ins_pipe(icond_reg);
%}

// This pattern is automatically generated from aarch64_ad.m4
// DO NOT EDIT ANYTHING IN THIS SECTION OF THE FILE
instruct cmovI_reg_imm0_gt(iRegINoSp dst, iRegI src1, rFlagsReg cr)
%{
effect(DEF dst, USE src1, USE cr);
ins_cost(INSN_COST * 2);
format %{ "cselw $dst, $src1, zr gt\t" %}

ins_encode %{
__ cselw($dst$$Register,
$src1$$Register,
zr,
Assembler::GT);
%}
ins_pipe(icond_reg);
%}

// This pattern is automatically generated from aarch64_ad.m4
// DO NOT EDIT ANYTHING IN THIS SECTION OF THE FILE
instruct cmovI_reg_imm1_le(iRegINoSp dst, iRegI src1, rFlagsReg cr)
%{
effect(DEF dst, USE src1, USE cr);
ins_cost(INSN_COST * 2);
format %{ "csincw $dst, $src1, zr le\t" %}

ins_encode %{
__ csincw($dst$$Register,
$src1$$Register,
zr,
Assembler::LE);
%}
ins_pipe(icond_reg);
%}

// This pattern is automatically generated from aarch64_ad.m4
// DO NOT EDIT ANYTHING IN THIS SECTION OF THE FILE
instruct cmovI_reg_imm1_gt(iRegINoSp dst, iRegI src1, rFlagsReg cr)
%{
effect(DEF dst, USE src1, USE cr);
ins_cost(INSN_COST * 2);
format %{ "csincw $dst, $src1, zr gt\t" %}

ins_encode %{
__ csincw($dst$$Register,
$src1$$Register,
zr,
Assembler::GT);
%}
ins_pipe(icond_reg);
%}

// This pattern is automatically generated from aarch64_ad.m4
// DO NOT EDIT ANYTHING IN THIS SECTION OF THE FILE
instruct cmovI_reg_immM1_lt(iRegINoSp dst, iRegI src1, rFlagsReg cr)
%{
effect(DEF dst, USE src1, USE cr);
ins_cost(INSN_COST * 2);
format %{ "csinvw $dst, $src1, zr lt\t" %}

ins_encode %{
__ csinvw($dst$$Register,
$src1$$Register,
zr,
Assembler::LT);
%}
ins_pipe(icond_reg);
%}

// This pattern is automatically generated from aarch64_ad.m4
// DO NOT EDIT ANYTHING IN THIS SECTION OF THE FILE
instruct cmovI_reg_immM1_ge(iRegINoSp dst, iRegI src1, rFlagsReg cr)
%{
effect(DEF dst, USE src1, USE cr);
ins_cost(INSN_COST * 2);
format %{ "csinvw $dst, $src1, zr ge\t" %}

ins_encode %{
__ csinvw($dst$$Register,
$src1$$Register,
zr,
Assembler::GE);
%}
ins_pipe(icond_reg);
%}

// This pattern is automatically generated from aarch64_ad.m4
// DO NOT EDIT ANYTHING IN THIS SECTION OF THE FILE
instruct minI_reg_imm0(iRegINoSp dst, iRegIorL2I src, immI0 imm)
%{
match(Set dst (MinI src imm));
ins_cost(INSN_COST * 3);
expand %{
rFlagsReg cr;
compI_reg_imm0(cr, src);
cmovI_reg_imm0_lt(dst, src, cr);
%}
%}

// This pattern is automatically generated from aarch64_ad.m4
// DO NOT EDIT ANYTHING IN THIS SECTION OF THE FILE
instruct minI_imm0_reg(iRegINoSp dst, immI0 imm, iRegIorL2I src)
%{
match(Set dst (MinI imm src));
ins_cost(INSN_COST * 3);
expand %{
rFlagsReg cr;
compI_reg_imm0(cr, src);
cmovI_reg_imm0_lt(dst, src, cr);
%}
%}

// This pattern is automatically generated from aarch64_ad.m4
// DO NOT EDIT ANYTHING IN THIS SECTION OF THE FILE
instruct minI_reg_imm1(iRegINoSp dst, iRegIorL2I src, immI_1 imm)
%{
match(Set dst (MinI src imm));
ins_cost(INSN_COST * 3);
expand %{
rFlagsReg cr;
compI_reg_imm0(cr, src);
cmovI_reg_imm1_le(dst, src, cr);
%}
%}

// This pattern is automatically generated from aarch64_ad.m4
// DO NOT EDIT ANYTHING IN THIS SECTION OF THE FILE
instruct minI_imm1_reg(iRegINoSp dst, immI_1 imm, iRegIorL2I src)
%{
match(Set dst (MinI imm src));
ins_cost(INSN_COST * 3);
expand %{
rFlagsReg cr;
compI_reg_imm0(cr, src);
cmovI_reg_imm1_le(dst, src, cr);
%}
%}

// This pattern is automatically generated from aarch64_ad.m4
// DO NOT EDIT ANYTHING IN THIS SECTION OF THE FILE
instruct minI_reg_immM1(iRegINoSp dst, iRegIorL2I src, immI_M1 imm)
%{
match(Set dst (MinI src imm));
ins_cost(INSN_COST * 3);
expand %{
rFlagsReg cr;
compI_reg_imm0(cr, src);
cmovI_reg_immM1_lt(dst, src, cr);
%}
%}

// This pattern is automatically generated from aarch64_ad.m4
// DO NOT EDIT ANYTHING IN THIS SECTION OF THE FILE
instruct minI_immM1_reg(iRegINoSp dst, immI_M1 imm, iRegIorL2I src)
%{
match(Set dst (MinI imm src));
ins_cost(INSN_COST * 3);
expand %{
rFlagsReg cr;
compI_reg_imm0(cr, src);
cmovI_reg_immM1_lt(dst, src, cr);
%}
%}

// This pattern is automatically generated from aarch64_ad.m4
// DO NOT EDIT ANYTHING IN THIS SECTION OF THE FILE
instruct maxI_reg_imm0(iRegINoSp dst, iRegIorL2I src, immI0 imm)
%{
match(Set dst (MaxI src imm));
ins_cost(INSN_COST * 3);
expand %{
rFlagsReg cr;
compI_reg_imm0(cr, src);
cmovI_reg_imm0_gt(dst, src, cr);
%}
%}

// This pattern is automatically generated from aarch64_ad.m4
// DO NOT EDIT ANYTHING IN THIS SECTION OF THE FILE
instruct maxI_imm0_reg(iRegINoSp dst, immI0 imm, iRegIorL2I src)
%{
match(Set dst (MaxI imm src));
ins_cost(INSN_COST * 3);
expand %{
rFlagsReg cr;
compI_reg_imm0(cr, src);
cmovI_reg_imm0_gt(dst, src, cr);
%}
%}

// This pattern is automatically generated from aarch64_ad.m4
// DO NOT EDIT ANYTHING IN THIS SECTION OF THE FILE
instruct maxI_reg_imm1(iRegINoSp dst, iRegIorL2I src, immI_1 imm)
%{
match(Set dst (MaxI src imm));
ins_cost(INSN_COST * 3);
expand %{
rFlagsReg cr;
compI_reg_imm0(cr, src);
cmovI_reg_imm1_gt(dst, src, cr);
%}
%}

// This pattern is automatically generated from aarch64_ad.m4
// DO NOT EDIT ANYTHING IN THIS SECTION OF THE FILE
instruct maxI_imm1_reg(iRegINoSp dst, immI_1 imm, iRegIorL2I src)
%{
match(Set dst (MaxI imm src));
ins_cost(INSN_COST * 3);
expand %{
rFlagsReg cr;
compI_reg_imm0(cr, src);
cmovI_reg_imm1_gt(dst, src, cr);
%}
%}

// This pattern is automatically generated from aarch64_ad.m4
// DO NOT EDIT ANYTHING IN THIS SECTION OF THE FILE
instruct maxI_reg_immM1(iRegINoSp dst, iRegIorL2I src, immI_M1 imm)
%{
match(Set dst (MaxI src imm));
ins_cost(INSN_COST * 3);
expand %{
rFlagsReg cr;
compI_reg_imm0(cr, src);
cmovI_reg_immM1_ge(dst, src, cr);
%}
%}

// This pattern is automatically generated from aarch64_ad.m4
// DO NOT EDIT ANYTHING IN THIS SECTION OF THE FILE
instruct maxI_immM1_reg(iRegINoSp dst, immI_M1 imm, iRegIorL2I src)
%{
match(Set dst (MaxI imm src));
ins_cost(INSN_COST * 3);
expand %{
rFlagsReg cr;
compI_reg_imm0(cr, src);
cmovI_reg_immM1_ge(dst, src, cr);
%}
%}



// END This section of the file is automatically generated. Do not edit --------------
Expand Down Expand Up @@ -15775,24 +16066,21 @@ instruct cmpLTMask_reg_zero(iRegINoSp dst, iRegIorL2I src, immI0 zero, rFlagsReg
// ============================================================================
// Max and Min

instruct cmovI_reg_reg_lt(iRegINoSp dst, iRegI src1, iRegI src2, rFlagsReg cr)
%{
effect( DEF dst, USE src1, USE src2, USE cr );
// Like compI_reg_reg or compI_reg_immI0 but without match rule and second zero parameter.

ins_cost(INSN_COST * 2);
format %{ "cselw $dst, $src1, $src2 lt\t" %}
instruct compI_reg_imm0(rFlagsReg cr, iRegI src)
%{
effect(DEF cr, USE src);
ins_cost(INSN_COST);
format %{ "cmpw $src, 0" %}

ins_encode %{
__ cselw(as_Register($dst$$reg),
as_Register($src1$$reg),
as_Register($src2$$reg),
Assembler::LT);
__ cmpw($src$$Register, 0);
%}

ins_pipe(icond_reg_reg);
ins_pipe(icmp_reg_imm);
%}

instruct minI_rReg(iRegINoSp dst, iRegI src1, iRegI src2)
instruct minI_reg_reg(iRegINoSp dst, iRegIorL2I src1, iRegIorL2I src2)
%{
match(Set dst (MinI src1 src2));
ins_cost(INSN_COST * 3);
Expand All @@ -15802,38 +16090,21 @@ instruct minI_rReg(iRegINoSp dst, iRegI src1, iRegI src2)
compI_reg_reg(cr, src1, src2);
cmovI_reg_reg_lt(dst, src1, src2, cr);
%}

%}
// FROM HERE

instruct cmovI_reg_reg_gt(iRegINoSp dst, iRegI src1, iRegI src2, rFlagsReg cr)
%{
effect( DEF dst, USE src1, USE src2, USE cr );

ins_cost(INSN_COST * 2);
format %{ "cselw $dst, $src1, $src2 gt\t" %}

ins_encode %{
__ cselw(as_Register($dst$$reg),
as_Register($src1$$reg),
as_Register($src2$$reg),
Assembler::GT);
%}

ins_pipe(icond_reg_reg);
%}

instruct maxI_rReg(iRegINoSp dst, iRegI src1, iRegI src2)
instruct maxI_reg_reg(iRegINoSp dst, iRegIorL2I src1, iRegIorL2I src2)
%{
match(Set dst (MaxI src1 src2));
ins_cost(INSN_COST * 3);

expand %{
rFlagsReg cr;
compI_reg_reg(cr, src1, src2);
cmovI_reg_reg_gt(dst, src1, src2, cr);
%}
%}


// ============================================================================
// Branch Instructions

Expand Down

3 comments on commit b3684f4

@openjdk-notifier
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@TheRealMDoerr
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/backport jdk17u-dev

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@openjdk openjdk bot commented on b3684f4 Jun 21, 2023

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@TheRealMDoerr the backport was successfully created on the branch TheRealMDoerr-backport-b3684f4b in my personal fork of openjdk/jdk17u-dev. To create a pull request with this backport targeting openjdk/jdk17u-dev:master, just click the following link:

➡️ Create pull request

The title of the pull request is automatically filled in correctly and below you find a suggestion for the pull request body:

Hi all,

This pull request contains a backport of commit b3684f4b from the openjdk/jdk repository.

The commit being backported was authored by Dmitry Chuyko on 18 Jan 2023 and was reviewed by Fei Yang and Andrew Haley.

Thanks!

If you need to update the source branch of the pull then run the following commands in a local clone of your personal fork of openjdk/jdk17u-dev:

$ git fetch https://github.com/openjdk-bots/jdk17u-dev.git TheRealMDoerr-backport-b3684f4b:TheRealMDoerr-backport-b3684f4b
$ git checkout TheRealMDoerr-backport-b3684f4b
# make changes
$ git add paths/to/changed/files
$ git commit --message 'Describe additional changes made'
$ git push https://github.com/openjdk-bots/jdk17u-dev.git TheRealMDoerr-backport-b3684f4b

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