8351155: C1/C2: Remove 32-bit x86 specific FP rounding support

Reviewed-by: vlivanov, kvn

Author: shipilev

src/hotspot/cpu/aarch64/c1_Defs_aarch64.hpp

@@ -32,11 +32,6 @@ enum {
   pd_hi_word_offset_in_bytes = BytesPerWord
 };
 
-// explicit rounding operations are required to implement the strictFP mode
-enum {
-  pd_strict_fp_requires_explicit_rounding = false
-};
-
 // FIXME: There are no callee-saved
 
 // registers

src/hotspot/cpu/aarch64/c1_LIRGenerator_aarch64.cpp

@@ -407,7 +407,7 @@ void LIRGenerator::do_ArithmeticOp_FPU(ArithmeticOp* x) {
 
   arithmetic_op_fpu(x->op(), reg, left.result(), right.result());
 
-  set_result(x, round_item(reg));
+  set_result(x, reg);
 }
 
 // for  _ladd, _lmul, _lsub, _ldiv, _lrem

src/hotspot/cpu/aarch64/matcher_aarch64.hpp

@@ -115,9 +115,6 @@
   // C code as the Java calling convention forces doubles to be aligned.
   static const bool misaligned_doubles_ok = true;
 
-  // Advertise here if the CPU requires explicit rounding operations to implement strictfp mode.
-  static const bool strict_fp_requires_explicit_rounding = false;
-
   // Are floats converted to double when stored to stack during
   // deoptimization?
   static constexpr bool float_in_double() { return false; }

src/hotspot/cpu/arm/arm.ad

@@ -4510,18 +4510,6 @@ instruct unnecessary_membar_volatile() %{
 %}
 
 //----------Register Move Instructions-----------------------------------------
-// instruct roundDouble_nop(regD dst) %{
-//   match(Set dst (RoundDouble dst));
-//   ins_pipe(empty);
-// %}
-
-
-// instruct roundFloat_nop(regF dst) %{
-//   match(Set dst (RoundFloat dst));
-//   ins_pipe(empty);
-// %}
-
-
 
 // Cast Index to Pointer for unsafe natives
 instruct castX2P(iRegX src, iRegP dst) %{

src/hotspot/cpu/arm/c1_Defs_arm.hpp

@@ -31,11 +31,6 @@ enum {
   pd_hi_word_offset_in_bytes = BytesPerWord
 };
 
-// explicit rounding operations are required to implement the strictFP mode
-enum {
-  pd_strict_fp_requires_explicit_rounding = false
-};
-
 #ifdef __SOFTFP__
 #define SOFT(n) n
 #define VFP(n)

src/hotspot/cpu/arm/matcher_arm.hpp

@@ -101,9 +101,6 @@
   // Java calling convention forces doubles to be aligned.
   static const bool misaligned_doubles_ok = false;
 
-  // Advertise here if the CPU requires explicit rounding operations to implement strictfp mode.
-  static const bool strict_fp_requires_explicit_rounding = false;
-
   // Are floats converted to double when stored to stack during deoptimization?
   // ARM does not handle callee-save floats.
   static constexpr bool float_in_double() {

src/hotspot/cpu/ppc/c1_Defs_ppc.hpp

@@ -38,12 +38,6 @@ enum {
 };
 
 
-// Explicit rounding operations are not required to implement the strictFP mode.
-enum {
-  pd_strict_fp_requires_explicit_rounding = false
-};
-
-
 // registers
 enum {
   pd_nof_cpu_regs_frame_map = 32,              // Number of registers used during code emission.

src/hotspot/cpu/ppc/matcher_ppc.hpp

@@ -115,9 +115,6 @@
   // Java calling convention forces doubles to be aligned.
   static const bool misaligned_doubles_ok = true;
 
-  // Advertise here if the CPU requires explicit rounding operations to implement strictfp mode.
-  static const bool strict_fp_requires_explicit_rounding = false;
-
   // Do floats take an entire double register or just half?
   //
   // A float occupies a ppc64 double register. For the allocator, a

src/hotspot/cpu/ppc/ppc.ad

@@ -9537,28 +9537,6 @@ instruct sqrtF_reg(regF dst, regF src) %{
   ins_pipe(pipe_class_default);
 %}
 
-instruct roundDouble_nop(regD dst) %{
-  match(Set dst (RoundDouble dst));
-  ins_cost(0);
-
-  format %{ " -- \t// RoundDouble not needed - empty" %}
-  size(0);
-  // PPC results are already "rounded" (i.e., normal-format IEEE).
-  ins_encode( /*empty*/ );
-  ins_pipe(pipe_class_default);
-%}
-
-instruct roundFloat_nop(regF dst) %{
-  match(Set dst (RoundFloat dst));
-  ins_cost(0);
-
-  format %{ " -- \t// RoundFloat not needed - empty" %}
-  size(0);
-  // PPC results are already "rounded" (i.e., normal-format IEEE).
-  ins_encode( /*empty*/ );
-  ins_pipe(pipe_class_default);
-%}
-
 
 // Multiply-Accumulate
 // src1 * src2 + src3

src/hotspot/cpu/riscv/c1_Defs_riscv.hpp

@@ -32,11 +32,6 @@ enum {
   pd_hi_word_offset_in_bytes = BytesPerWord
 };
 
-// explicit rounding operations are required to implement the strictFP mode
-enum {
-  pd_strict_fp_requires_explicit_rounding = false
-};
-
 // registers
 enum {
   pd_nof_cpu_regs_frame_map = Register::number_of_registers,       // number of registers used during code emission