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8295967: RISC-V: Support negVI/negVL instructions for Vector API
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Reviewed-by: yadongwang, fyang
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DingliZhang authored and RealFYang committed Nov 4, 2022
1 parent 9d3b4ef commit c116ae7
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Showing 3 changed files with 29 additions and 0 deletions.
4 changes: 4 additions & 0 deletions src/hotspot/cpu/riscv/macroAssembler_riscv.cpp
Original file line number Diff line number Diff line change
Expand Up @@ -725,6 +725,10 @@ void MacroAssembler::vncvt_x_x_w(VectorRegister vd, VectorRegister vs, VectorMas
vnsrl_wx(vd, vs, x0, vm);
}

void MacroAssembler::vneg_v(VectorRegister vd, VectorRegister vs) {
vrsub_vx(vd, x0, vs);
}

void MacroAssembler::vfneg_v(VectorRegister vd, VectorRegister vs) {
vfsgnjn_vv(vd, vs, vs);
}
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1 change: 1 addition & 0 deletions src/hotspot/cpu/riscv/macroAssembler_riscv.hpp
Original file line number Diff line number Diff line change
Expand Up @@ -1192,6 +1192,7 @@ class MacroAssembler: public Assembler {
// vext
void vmnot_m(VectorRegister vd, VectorRegister vs);
void vncvt_x_x_w(VectorRegister vd, VectorRegister vs, VectorMask vm = unmasked);
void vneg_v(VectorRegister vd, VectorRegister vs);
void vfneg_v(VectorRegister vd, VectorRegister vs);


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24 changes: 24 additions & 0 deletions src/hotspot/cpu/riscv/riscv_v.ad
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Expand Up @@ -761,6 +761,30 @@ instruct vmulD(vReg dst, vReg src1, vReg src2) %{
ins_pipe(pipe_slow);
%}

// vector neg

instruct vnegI(vReg dst, vReg src) %{
match(Set dst (NegVI src));
ins_cost(VEC_COST);
format %{ "vrsub.vx $dst, $src, $src\t#@vnegI" %}
ins_encode %{
__ vsetvli(t0, x0, Assembler::e32);
__ vneg_v(as_VectorRegister($dst$$reg), as_VectorRegister($src$$reg));
%}
ins_pipe(pipe_slow);
%}

instruct vnegL(vReg dst, vReg src) %{
match(Set dst (NegVL src));
ins_cost(VEC_COST);
format %{ "vrsub.vx $dst, $src, $src\t#@vnegL" %}
ins_encode %{
__ vsetvli(t0, x0, Assembler::e64);
__ vneg_v(as_VectorRegister($dst$$reg), as_VectorRegister($src$$reg));
%}
ins_pipe(pipe_slow);
%}

// vector fneg

instruct vnegF(vReg dst, vReg src) %{
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