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8307907: [ppc] Remove RTM locking implementation
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Reviewed-by: mbaesken, rrich, stuefe
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TheRealMDoerr committed Jun 15, 2023
1 parent 4c0e164 commit de8aca2
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Showing 15 changed files with 22 additions and 864 deletions.
66 changes: 0 additions & 66 deletions src/hotspot/cpu/ppc/assembler_ppc.hpp
Original file line number Diff line number Diff line change
Expand Up @@ -337,15 +337,6 @@ class Assembler : public AbstractAssembler {
MFCTR_OPCODE = (MFSPR_OPCODE | 9 << SPR_0_4_SHIFT),

// Attention: Higher and lower half are inserted in reversed order.
MTTFHAR_OPCODE = (MTSPR_OPCODE | 4 << SPR_5_9_SHIFT | 0 << SPR_0_4_SHIFT),
MFTFHAR_OPCODE = (MFSPR_OPCODE | 4 << SPR_5_9_SHIFT | 0 << SPR_0_4_SHIFT),
MTTFIAR_OPCODE = (MTSPR_OPCODE | 4 << SPR_5_9_SHIFT | 1 << SPR_0_4_SHIFT),
MFTFIAR_OPCODE = (MFSPR_OPCODE | 4 << SPR_5_9_SHIFT | 1 << SPR_0_4_SHIFT),
MTTEXASR_OPCODE = (MTSPR_OPCODE | 4 << SPR_5_9_SHIFT | 2 << SPR_0_4_SHIFT),
MFTEXASR_OPCODE = (MFSPR_OPCODE | 4 << SPR_5_9_SHIFT | 2 << SPR_0_4_SHIFT),
MTTEXASRU_OPCODE = (MTSPR_OPCODE | 4 << SPR_5_9_SHIFT | 3 << SPR_0_4_SHIFT),
MFTEXASRU_OPCODE = (MFSPR_OPCODE | 4 << SPR_5_9_SHIFT | 3 << SPR_0_4_SHIFT),

MTVRSAVE_OPCODE = (MTSPR_OPCODE | 8 << SPR_5_9_SHIFT | 0 << SPR_0_4_SHIFT),
MFVRSAVE_OPCODE = (MFSPR_OPCODE | 8 << SPR_5_9_SHIFT | 0 << SPR_0_4_SHIFT),

Expand Down Expand Up @@ -766,17 +757,6 @@ class Assembler : public AbstractAssembler {
// Vector Permute and Xor (introduced with Power 8)
VPERMXOR_OPCODE = (4u << OPCODE_SHIFT | 45u),

// Transactional Memory instructions (introduced with Power 8)
TBEGIN_OPCODE = (31u << OPCODE_SHIFT | 654u << 1),
TEND_OPCODE = (31u << OPCODE_SHIFT | 686u << 1),
TABORT_OPCODE = (31u << OPCODE_SHIFT | 910u << 1),
TABORTWC_OPCODE = (31u << OPCODE_SHIFT | 782u << 1),
TABORTWCI_OPCODE = (31u << OPCODE_SHIFT | 846u << 1),
TABORTDC_OPCODE = (31u << OPCODE_SHIFT | 814u << 1),
TABORTDCI_OPCODE = (31u << OPCODE_SHIFT | 878u << 1),
TSR_OPCODE = (31u << OPCODE_SHIFT | 750u << 1),
TCHECK_OPCODE = (31u << OPCODE_SHIFT | 718u << 1),

// Icache and dcache related instructions
DCBA_OPCODE = (31u << OPCODE_SHIFT | 758u << 1),
DCBZ_OPCODE = (31u << OPCODE_SHIFT | 1014u << 1),
Expand Down Expand Up @@ -1814,33 +1794,6 @@ class Assembler : public AbstractAssembler {
// Data Stream Control Register
inline void mtdscr(Register s1);
inline void mfdscr(Register d );
// Transactional Memory Registers
inline void mftfhar(Register d);
inline void mftfiar(Register d);
inline void mftexasr(Register d);
inline void mftexasru(Register d);

// TEXASR bit description
enum transaction_failure_reason {
// Upper half (TEXASRU):
tm_failure_code = 0, // The Failure Code is copied from tabort or treclaim operand.
tm_failure_persistent = 7, // The failure is likely to recur on each execution.
tm_disallowed = 8, // The instruction is not permitted.
tm_nesting_of = 9, // The maximum transaction level was exceeded.
tm_footprint_of = 10, // The tracking limit for transactional storage accesses was exceeded.
tm_self_induced_cf = 11, // A self-induced conflict occurred in Suspended state.
tm_non_trans_cf = 12, // A conflict occurred with a non-transactional access by another processor.
tm_trans_cf = 13, // A conflict occurred with another transaction.
tm_translation_cf = 14, // A conflict occurred with a TLB invalidation.
tm_inst_fetch_cf = 16, // An instruction fetch was performed from a block that was previously written transactionally.
tm_tabort = 31, // Termination was caused by the execution of an abort instruction.
// Lower half:
tm_suspended = 32, // Failure was recorded in Suspended state.
tm_failure_summary = 36, // Failure has been detected and recorded.
tm_tfiar_exact = 37, // Value in the TFIAR is exact.
tm_rot = 38, // Rollback-only transaction.
tm_transaction_level = 52, // Transaction level (nesting depth + 1).
};

// PPC 1, section 2.4.1 Branch Instructions
inline void b( address a, relocInfo::relocType rt = relocInfo::none);
Expand Down Expand Up @@ -2452,25 +2405,6 @@ class Assembler : public AbstractAssembler {
// Vector Permute and Xor (introduced with Power 8)
inline void vpermxor( VectorRegister d, VectorRegister a, VectorRegister b, VectorRegister c);

// Transactional Memory instructions (introduced with Power 8)
inline void tbegin_(); // R=0
inline void tbeginrot_(); // R=1 Rollback-Only Transaction
inline void tend_(); // A=0
inline void tendall_(); // A=1
inline void tabort_();
inline void tabort_(Register a);
inline void tabortwc_(int t, Register a, Register b);
inline void tabortwci_(int t, Register a, int si);
inline void tabortdc_(int t, Register a, Register b);
inline void tabortdci_(int t, Register a, int si);
inline void tsuspend_(); // tsr with L=0
inline void tresume_(); // tsr with L=1
inline void tcheck(int f);

static bool is_tbegin(int x) {
return TBEGIN_OPCODE == (x & (0x3f << OPCODE_SHIFT | 0x3ff << 1));
}

// The following encoders use r0 as second operand. These instructions
// read r0 as '0'.
inline void lwzx( Register d, Register s2);
Expand Down
21 changes: 0 additions & 21 deletions src/hotspot/cpu/ppc/assembler_ppc.inline.hpp
Original file line number Diff line number Diff line change
Expand Up @@ -433,13 +433,7 @@ inline void Assembler::mftb(Register d ) { emit_int32(MFTB_OPCODE | rt
// Data Stream Control Register
inline void Assembler::mtdscr(Register s1) { emit_int32(MTDSCR_OPCODE | rs(s1)); }
inline void Assembler::mfdscr(Register d ) { emit_int32(MFDSCR_OPCODE | rt(d)); }
// Transactional Memory Registers
inline void Assembler::mftfhar(Register d ) { emit_int32(MFTFHAR_OPCODE | rt(d)); }
inline void Assembler::mftfiar(Register d ) { emit_int32(MFTFIAR_OPCODE | rt(d)); }
inline void Assembler::mftexasr(Register d ) { emit_int32(MFTEXASR_OPCODE | rt(d)); }
inline void Assembler::mftexasru(Register d ) { emit_int32(MFTEXASRU_OPCODE | rt(d)); }

// SAP JVM 2006-02-13 PPC branch instruction.
// PPC 1, section 2.4.1 Branch Instructions
inline void Assembler::b( address a, relocInfo::relocType rt) { emit_data(BXX_OPCODE| li(disp( intptr_t(a), intptr_t(pc()))) |aa(0)|lk(0), rt); }
inline void Assembler::b( Label& L) { b( target(L)); }
Expand Down Expand Up @@ -1048,21 +1042,6 @@ inline void Assembler::vpmsumw( VectorRegister d, VectorRegister a, VectorRegis
// Vector Permute and Xor (introduced with Power 8)
inline void Assembler::vpermxor( VectorRegister d, VectorRegister a, VectorRegister b, VectorRegister c) { emit_int32( VPERMXOR_OPCODE | vrt(d) | vra(a) | vrb(b) | vrc(c)); }

// Transactional Memory instructions (introduced with Power 8)
inline void Assembler::tbegin_() { emit_int32( TBEGIN_OPCODE | rc(1)); }
inline void Assembler::tbeginrot_() { emit_int32( TBEGIN_OPCODE | /*R=1*/ 1u << (31-10) | rc(1)); }
inline void Assembler::tend_() { emit_int32( TEND_OPCODE | rc(1)); }
inline void Assembler::tendall_() { emit_int32( TEND_OPCODE | /*A=1*/ 1u << (31-6) | rc(1)); }
inline void Assembler::tabort_() { emit_int32( TABORT_OPCODE | rc(1)); }
inline void Assembler::tabort_(Register a) { assert(a != R0, "r0 not allowed"); emit_int32( TABORT_OPCODE | ra(a) | rc(1)); }
inline void Assembler::tabortwc_(int t, Register a, Register b) { emit_int32( TABORTWC_OPCODE | to(t) | ra(a) | rb(b) | rc(1)); }
inline void Assembler::tabortwci_(int t, Register a, int si) { emit_int32( TABORTWCI_OPCODE | to(t) | ra(a) | sh1620(si) | rc(1)); }
inline void Assembler::tabortdc_(int t, Register a, Register b) { emit_int32( TABORTDC_OPCODE | to(t) | ra(a) | rb(b) | rc(1)); }
inline void Assembler::tabortdci_(int t, Register a, int si) { emit_int32( TABORTDCI_OPCODE | to(t) | ra(a) | sh1620(si) | rc(1)); }
inline void Assembler::tsuspend_() { emit_int32( TSR_OPCODE | rc(1)); }
inline void Assembler::tresume_() { emit_int32( TSR_OPCODE | /*L=1*/ 1u << (31-10) | rc(1)); }
inline void Assembler::tcheck(int f) { emit_int32( TCHECK_OPCODE | bf(f)); }

// Deliver A Random Number (introduced with POWER9)
inline void Assembler::darn(Register d, int l /* =1 */) { emit_int32( DARN_OPCODE | rt(d) | l14(l)); }

Expand Down
7 changes: 0 additions & 7 deletions src/hotspot/cpu/ppc/globalDefinitions_ppc.hpp
Original file line number Diff line number Diff line change
Expand Up @@ -45,13 +45,6 @@ const bool CCallingConventionRequiresIntsAsLongs = true;
// The expected size in bytes of a cache line, used to pad data structures.
#define DEFAULT_CACHE_LINE_SIZE 128

#if defined(COMPILER2) && (defined(AIX) || defined(LINUX))
// Include Transactional Memory lock eliding optimization
#define INCLUDE_RTM_OPT 1
#else
#define INCLUDE_RTM_OPT 0
#endif

#define SUPPORT_RESERVED_STACK_AREA

// If UseSIGTRAP is active, we only use the poll bit and no polling page.
Expand Down
45 changes: 1 addition & 44 deletions src/hotspot/cpu/ppc/globals_ppc.hpp
Original file line number Diff line number Diff line change
Expand Up @@ -151,50 +151,7 @@ define_pd_global(intx, InitArrayShortSize, 9*BytesPerLong);
"Trace all traps the signal handler handles.") \
\
develop(bool, ZapMemory, false, \
"Write 0x0101... to empty memory. Use this to ease debugging.") \
\
/* Use Restricted Transactional Memory for lock elision */ \
product(bool, UseRTMLocking, false, \
"Enable RTM lock eliding for inflated locks in compiled code") \
\
product(bool, UseRTMForStackLocks, false, EXPERIMENTAL, \
"Enable RTM lock eliding for stack locks in compiled code") \
\
product(bool, UseRTMDeopt, false, \
"Perform deopt and recompilation based on RTM abort ratio") \
\
product(int, RTMRetryCount, 5, \
"Number of RTM retries on lock abort or busy") \
range(0, max_jint) \
\
product(int, RTMSpinLoopCount, 100, EXPERIMENTAL, \
"Spin count for lock to become free before RTM retry") \
range(0, 32767) /* immediate operand limit on ppc */ \
\
product(int, RTMAbortThreshold, 1000, EXPERIMENTAL, \
"Calculate abort ratio after this number of aborts") \
range(0, max_jint) \
\
product(int, RTMLockingThreshold, 10000, EXPERIMENTAL, \
"Lock count at which to do RTM lock eliding without " \
"abort ratio calculation") \
range(0, max_jint) \
\
product(int, RTMAbortRatio, 50, EXPERIMENTAL, \
"Lock abort ratio at which to stop use RTM lock eliding") \
range(0, 100) /* natural range */ \
\
product(int, RTMTotalCountIncrRate, 64, EXPERIMENTAL, \
"Increment total RTM attempted lock count once every n times") \
range(1, 32767) /* immediate operand limit on ppc */ \
constraint(RTMTotalCountIncrRateConstraintFunc,AfterErgo) \
\
product(intx, RTMLockingCalculationDelay, 0, EXPERIMENTAL, \
"Number of milliseconds to wait before start calculating aborts " \
"for RTM locking") \
\
product(bool, UseRTMXendForLockBusy, true, EXPERIMENTAL, \
"Use RTM Xend instead of Xabort when lock busy")
"Write 0x0101... to empty memory. Use this to ease debugging.")

// end of ARCH_FLAGS

Expand Down

3 comments on commit de8aca2

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@rkennke
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/backport lilliput-jdk21u

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@openjdk openjdk bot commented on de8aca2 Mar 25, 2024

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@rkennke the backport was successfully created on the branch backport-rkennke-de8aca27 in my personal fork of openjdk/lilliput-jdk21u. To create a pull request with this backport targeting openjdk/lilliput-jdk21u:lilliput, just click the following link:

➡️ Create pull request

The title of the pull request is automatically filled in correctly and below you find a suggestion for the pull request body:

Hi all,

This pull request contains a backport of commit de8aca27 from the openjdk/jdk repository.

The commit being backported was authored by Martin Doerr on 15 Jun 2023 and was reviewed by Matthias Baesken, Richard Reingruber and Thomas Stuefe.

Thanks!

If you need to update the source branch of the pull then run the following commands in a local clone of your personal fork of openjdk/lilliput-jdk21u:

$ git fetch https://github.com/openjdk-bots/lilliput-jdk21u.git backport-rkennke-de8aca27:backport-rkennke-de8aca27
$ git checkout backport-rkennke-de8aca27
# make changes
$ git add paths/to/changed/files
$ git commit --message 'Describe additional changes made'
$ git push https://github.com/openjdk-bots/lilliput-jdk21u.git backport-rkennke-de8aca27

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