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author
Jatin Bhateja
committed
8351016: RA support for EVEX to REX/REX2 demotion to optimize NDD instructions
Reviewed-by: sviswanathan, dlunden, vlivanov, qamai
1 parent c7a489d commit e0311ec

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13 files changed

+268
-78
lines changed

13 files changed

+268
-78
lines changed

‎src/hotspot/cpu/aarch64/aarch64.ad‎

Lines changed: 4 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -2456,6 +2456,10 @@ bool Matcher::is_reg2reg_move(MachNode* m) {
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return false;
24572457
}
24582458

2459+
bool Matcher::is_register_biasing_candidate(const MachNode* mdef, int oper_index) {
2460+
return false;
2461+
}
2462+
24592463
bool Matcher::is_generic_vector(MachOper* opnd) {
24602464
return opnd->opcode() == VREG;
24612465
}

‎src/hotspot/cpu/arm/arm.ad‎

Lines changed: 4 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -1063,6 +1063,10 @@ bool Matcher::is_reg2reg_move(MachNode* m) {
10631063
return false;
10641064
}
10651065

1066+
bool Matcher::is_register_biasing_candidate(const MachNode* mdef, int oper_index) {
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return false;
1068+
}
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10661070
bool Matcher::is_generic_vector(MachOper* opnd) {
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ShouldNotReachHere(); // generic vector operands not supported
10681072
return false;

‎src/hotspot/cpu/ppc/ppc.ad‎

Lines changed: 4 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -2383,6 +2383,10 @@ bool Matcher::is_reg2reg_move(MachNode* m) {
23832383
return false;
23842384
}
23852385

2386+
bool Matcher::is_register_biasing_candidate(const MachNode* mdef, int oper_index) {
2387+
return false;
2388+
}
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bool Matcher::is_generic_vector(MachOper* opnd) {
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ShouldNotReachHere(); // generic vector operands not supported
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return false;

‎src/hotspot/cpu/riscv/riscv.ad‎

Lines changed: 4 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -2053,6 +2053,10 @@ bool Matcher::is_reg2reg_move(MachNode* m) {
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return false;
20542054
}
20552055

2056+
bool Matcher::is_register_biasing_candidate(const MachNode* mdef, int oper_index) {
2057+
return false;
2058+
}
2059+
20562060
bool Matcher::is_generic_vector(MachOper* opnd) {
20572061
ShouldNotReachHere(); // generic vector operands not supported
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return false;

‎src/hotspot/cpu/s390/s390.ad‎

Lines changed: 4 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -1865,6 +1865,10 @@ bool Matcher::is_reg2reg_move(MachNode* m) {
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return false;
18661866
}
18671867

1868+
bool Matcher::is_register_biasing_candidate(const MachNode* mdef, int oper_index) {
1869+
return false;
1870+
}
1871+
18681872
bool Matcher::is_generic_vector(MachOper* opnd) {
18691873
ShouldNotReachHere(); // generic vector operands not supported
18701874
return false;

‎src/hotspot/cpu/x86/x86.ad‎

Lines changed: 129 additions & 38 deletions
Large diffs are not rendered by default.

‎src/hotspot/share/opto/chaitin.cpp‎

Lines changed: 85 additions & 20 deletions
Original file line numberDiff line numberDiff line change
@@ -1471,6 +1471,65 @@ static OptoReg::Name find_first_set(LRG& lrg, RegMask& mask) {
14711471
return assigned;
14721472
}
14731473

1474+
OptoReg::Name PhaseChaitin::select_bias_lrg_color(LRG& lrg) {
1475+
uint bias_lrg1_idx = _lrg_map.find(lrg._copy_bias);
1476+
uint bias_lrg2_idx = _lrg_map.find(lrg._copy_bias2);
1477+
1478+
// If bias_lrg1 has a color
1479+
if (bias_lrg1_idx != 0 && !_ifg->_yanked->test(bias_lrg1_idx)) {
1480+
OptoReg::Name reg = lrgs(bias_lrg1_idx).reg();
1481+
// and it is legal for lrg
1482+
if (is_legal_reg(lrg, reg)) {
1483+
return reg;
1484+
}
1485+
}
1486+
1487+
// If bias_lrg2 has a color
1488+
if (bias_lrg2_idx != 0 && !_ifg->_yanked->test(bias_lrg2_idx)) {
1489+
OptoReg::Name reg = lrgs(bias_lrg2_idx).reg();
1490+
// and it is legal for lrg
1491+
if (is_legal_reg(lrg, reg)) {
1492+
return reg;
1493+
}
1494+
}
1495+
1496+
uint bias_lrg_idx = 0;
1497+
if (bias_lrg1_idx != 0 && bias_lrg2_idx != 0) {
1498+
// Since none of the bias live ranges are part of the IFG yet, constrain the
1499+
// definition mask with the bias live range with the least degrees of
1500+
// freedom. This will increase the chances of register sharing once the bias
1501+
// live range becomes part of the IFG.
1502+
lrgs(bias_lrg1_idx).compute_set_mask_size();
1503+
lrgs(bias_lrg2_idx).compute_set_mask_size();
1504+
bias_lrg_idx = lrgs(bias_lrg1_idx).degrees_of_freedom() >
1505+
lrgs(bias_lrg2_idx).degrees_of_freedom()
1506+
? bias_lrg2_idx
1507+
: bias_lrg1_idx;
1508+
} else if (bias_lrg1_idx != 0) {
1509+
bias_lrg_idx = bias_lrg1_idx;
1510+
} else if (bias_lrg2_idx != 0) {
1511+
bias_lrg_idx = bias_lrg2_idx;
1512+
}
1513+
1514+
// Register masks with offset excludes all mask bits before the offset.
1515+
// Such masks are mainly used for allocation from stack slots. Constrain the
1516+
// register mask of definition live range using bias mask only if
1517+
// both masks have zero offset.
1518+
if (bias_lrg_idx != 0 && !lrg.mask().is_offset() &&
1519+
!lrgs(bias_lrg_idx).mask().is_offset()) {
1520+
// Choose a color which is legal for bias_lrg
1521+
ResourceMark rm(C->regmask_arena());
1522+
RegMask tempmask(lrg.mask(), C->regmask_arena());
1523+
tempmask.and_with(lrgs(bias_lrg_idx).mask());
1524+
tempmask.clear_to_sets(lrg.num_regs());
1525+
OptoReg::Name reg = find_first_set(lrg, tempmask);
1526+
if (OptoReg::is_valid(reg)) {
1527+
return reg;
1528+
}
1529+
}
1530+
return OptoReg::Bad;
1531+
}
1532+
14741533
// Choose a color using the biasing heuristic
14751534
OptoReg::Name PhaseChaitin::bias_color(LRG& lrg) {
14761535

@@ -1492,25 +1551,10 @@ OptoReg::Name PhaseChaitin::bias_color(LRG& lrg) {
14921551
}
14931552
}
14941553

1495-
uint copy_lrg = _lrg_map.find(lrg._copy_bias);
1496-
if (copy_lrg != 0) {
1497-
// If he has a color,
1498-
if(!_ifg->_yanked->test(copy_lrg)) {
1499-
OptoReg::Name reg = lrgs(copy_lrg).reg();
1500-
// And it is legal for you,
1501-
if (is_legal_reg(lrg, reg)) {
1502-
return reg;
1503-
}
1504-
} else if (!lrg.mask().is_offset()) {
1505-
// Choose a color which is legal for him
1506-
ResourceMark rm(C->regmask_arena());
1507-
RegMask tempmask(lrg.mask(), C->regmask_arena());
1508-
tempmask.and_with(lrgs(copy_lrg).mask());
1509-
tempmask.clear_to_sets(lrg.num_regs());
1510-
OptoReg::Name reg = find_first_set(lrg, tempmask);
1511-
if (OptoReg::is_valid(reg))
1512-
return reg;
1513-
}
1554+
// Try biasing the color with non-interfering bias live range[s].
1555+
OptoReg::Name reg = select_bias_lrg_color(lrg);
1556+
if (OptoReg::is_valid(reg)) {
1557+
return reg;
15141558
}
15151559

15161560
// If no bias info exists, just go with the register selection ordering
@@ -1524,7 +1568,7 @@ OptoReg::Name PhaseChaitin::bias_color(LRG& lrg) {
15241568
// CNC - Fun hack. Alternate 1st and 2nd selection. Enables post-allocate
15251569
// copy removal to remove many more copies, by preventing a just-assigned
15261570
// register from being repeatedly assigned.
1527-
OptoReg::Name reg = lrg.mask().find_first_elem();
1571+
reg = lrg.mask().find_first_elem();
15281572
if( (++_alternate & 1) && OptoReg::is_valid(reg) ) {
15291573
// This 'Remove; find; Insert' idiom is an expensive way to find the
15301574
// SECOND element in the mask.
@@ -1640,6 +1684,27 @@ uint PhaseChaitin::Select( ) {
16401684
}
16411685
}
16421686
}
1687+
1688+
Node* def = lrg->_def;
1689+
if (lrg->is_singledef() && !lrg->_is_bound && def->is_Mach()) {
1690+
MachNode* mdef = def->as_Mach();
1691+
if (Matcher::is_register_biasing_candidate(mdef, 1)) {
1692+
Node* in1 = mdef->in(mdef->operand_index(1));
1693+
if (in1 != nullptr && lrg->_copy_bias == 0) {
1694+
lrg->_copy_bias = _lrg_map.find(in1);
1695+
}
1696+
}
1697+
1698+
// For commutative operations, def allocation can also be
1699+
// biased towards LRG of second input's def.
1700+
if (Matcher::is_register_biasing_candidate(mdef, 2)) {
1701+
Node* in2 = mdef->in(mdef->operand_index(2));
1702+
if (in2 != nullptr && lrg->_copy_bias2 == 0) {
1703+
lrg->_copy_bias2 = _lrg_map.find(in2);
1704+
}
1705+
}
1706+
}
1707+
16431708
//assert(is_infinite_stack == lrg->mask().is_infinite_stack(), "nbrs must not change InfiniteStackedness");
16441709
// Aligned pairs need aligned masks
16451710
assert(!lrg->_is_vector || !lrg->_fat_proj, "sanity");

‎src/hotspot/share/opto/chaitin.hpp‎

Lines changed: 3 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -63,6 +63,7 @@ class LRG : public ResourceObj {
6363

6464
uint _risk_bias; // Index of LRG which we want to avoid color
6565
uint _copy_bias; // Index of LRG which we want to share color
66+
uint _copy_bias2; // Index of second LRG which we want to share color
6667

6768
uint _next; // Index of next LRG in linked list
6869
uint _prev; // Index of prev LRG in linked list
@@ -703,6 +704,8 @@ class PhaseChaitin : public PhaseRegAlloc {
703704
OptoReg::Name choose_color(LRG& lrg);
704705
// Helper function which implements biasing heuristic
705706
OptoReg::Name bias_color(LRG& lrg);
707+
// Helper function which implements color biasing
708+
OptoReg::Name select_bias_lrg_color(LRG& lrg);
706709

707710
// Split uncolorable live ranges
708711
// Return new number of live ranges

‎src/hotspot/share/opto/idealGraphPrinter.cpp‎

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -88,6 +88,7 @@ void PrintProperties::print_lrg_properties(const LRG &lrg, const char *buffer) {
8888
print_property(true, "score", lrg.score());
8989
print_property((lrg._risk_bias != 0), "risk_bias", lrg._risk_bias);
9090
print_property((lrg._copy_bias != 0), "copy_bias", lrg._copy_bias);
91+
print_property((lrg._copy_bias2 != 0), "copy_bias2", lrg._copy_bias2);
9192
print_property(lrg.is_singledef(), "is_singledef");
9293
print_property(lrg.is_multidef(), "is_multidef");
9394
print_property(lrg._is_oop, "is_oop");

‎src/hotspot/share/opto/machnode.cpp‎

Lines changed: 7 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -460,6 +460,13 @@ int MachNode::operand_index(Node* def) const {
460460
return -1;
461461
}
462462

463+
int MachNode::operand_num_edges(uint oper_index) const {
464+
if (num_opnds() > oper_index) {
465+
return _opnds[oper_index]->num_edges();
466+
}
467+
return 0;
468+
}
469+
463470
//------------------------------peephole---------------------------------------
464471
// Apply peephole rule(s) to this instruction
465472
int MachNode::peephole(Block *block, int block_index, PhaseCFG* cfg_, PhaseRegAlloc *ra_) {

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