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8299817: [s390] AES-CTR mode intrinsic fails with multiple short update() calls
Reviewed-by: mbaesken, mdoerr
1 parent 5feb13b commit e144783

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5 files changed

+665
-210
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5 files changed

+665
-210
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‎src/hotspot/cpu/s390/assembler_s390.hpp

Lines changed: 24 additions & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -1,6 +1,6 @@
11
/*
2-
* Copyright (c) 2016, 2022, Oracle and/or its affiliates. All rights reserved.
3-
* Copyright (c) 2016, 2022 SAP SE. All rights reserved.
2+
* Copyright (c) 2016, 2023, Oracle and/or its affiliates. All rights reserved.
3+
* Copyright (c) 2016, 2023 SAP SE. All rights reserved.
44
* DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
55
*
66
* This code is free software; you can redistribute it and/or modify it
@@ -843,6 +843,10 @@ class Assembler : public AbstractAssembler {
843843
#define CY_ZOPC (unsigned long)(227L << 40 | 89L)
844844
#define CGF_ZOPC (unsigned long)(227L << 40 | 48L)
845845
#define CG_ZOPC (unsigned long)(227L << 40 | 32L)
846+
// MI, signed
847+
#define CHHSI_ZOPC (unsigned long)(0xe5L << 40 | 0x54L << 32)
848+
#define CHSI_ZOPC (unsigned long)(0xe5L << 40 | 0x5cL << 32)
849+
#define CGHSI_ZOPC (unsigned long)(0xe5L << 40 | 0x58L << 32)
846850
// RR, unsigned
847851
#define CLR_ZOPC (unsigned int)(21 << 8)
848852
#define CLGFR_ZOPC (unsigned int)(185 << 24 | 49 << 16)
@@ -855,6 +859,10 @@ class Assembler : public AbstractAssembler {
855859
#define CLY_ZOPC (unsigned long)(227L << 40 | 85L)
856860
#define CLGF_ZOPC (unsigned long)(227L << 40 | 49L)
857861
#define CLG_ZOPC (unsigned long)(227L << 40 | 33L)
862+
// MI, unsigned
863+
#define CLHHSI_ZOPC (unsigned long)(0xe5L << 40 | 0x55L << 32)
864+
#define CLFHSI_ZOPC (unsigned long)(0xe5L << 40 | 0x5dL << 32)
865+
#define CLGHSI_ZOPC (unsigned long)(0xe5L << 40 | 0x59L << 32)
858866
// RI, unsigned
859867
#define TMHH_ZOPC (unsigned int)(167 << 24 | 2 << 16)
860868
#define TMHL_ZOPC (unsigned int)(167 << 24 | 3 << 16)
@@ -1060,6 +1068,7 @@ class Assembler : public AbstractAssembler {
10601068
#define MVI_ZOPC (unsigned int)(0x92 << 24)
10611069
#define MVIY_ZOPC (unsigned long)(0xebL << 40 | 0x52L)
10621070
#define MVC_ZOPC (unsigned long)(0xd2L << 40)
1071+
#define MVCIN_ZOPC (unsigned long)(0xe8L << 40)
10631072
#define MVCL_ZOPC (unsigned int)(0x0e << 8)
10641073
#define MVCLE_ZOPC (unsigned int)(0xa8 << 24)
10651074

@@ -1708,21 +1717,21 @@ class Assembler : public AbstractAssembler {
17081717

17091718
// unsigned immediate, in low bits, nbits long
17101719
static long uimm(long x, int nbits) {
1711-
assert(Immediate::is_uimm(x, nbits), "unsigned constant out of range");
1720+
assert(Immediate::is_uimm(x, nbits), "unsigned immediate " INTPTR_FORMAT " out of range (%d bits)", x, nbits);
17121721
return x & fmask(nbits - 1, 0);
17131722
}
17141723

17151724
// Cast '1' to long to avoid sign extension if nbits = 32.
17161725
// signed immediate, in low bits, nbits long
17171726
static long simm(long x, int nbits) {
1718-
assert(Immediate::is_simm(x, nbits), "value out of range");
1727+
assert(Immediate::is_simm(x, nbits), "signed immediate " INTPTR_FORMAT " out of range (%d bits)", x, nbits);
17191728
return x & fmask(nbits - 1, 0);
17201729
}
17211730

17221731
static long imm(int64_t x, int nbits) {
17231732
// Assert that x can be represented with nbits bits ignoring the sign bits,
17241733
// i.e. the more higher bits should all be 0 or 1.
1725-
assert((x >> nbits) == 0 || (x >> nbits) == -1, "value out of range");
1734+
assert((x >> nbits) == 0 || (x >> nbits) == -1, "signed immediate " INTPTR_FORMAT " out of range (%d bits)", x, nbits);
17261735
return x & fmask(nbits-1, 0);
17271736
}
17281737

@@ -1734,7 +1743,7 @@ class Assembler : public AbstractAssembler {
17341743
// contents of the DH field to the left of the contents of
17351744
// the DL field.
17361745
static long simm20(int64_t ui20) {
1737-
assert(Immediate::is_simm(ui20, 20), "value out of range");
1746+
assert(Immediate::is_simm(ui20, 20), "signed displacement (disp20) " INTPTR_FORMAT " out of range", ui20);
17381747
return ( ((ui20 & 0xfffL) << (48-32)) | // DL
17391748
(((ui20 >> 12) & 0xffL) << (48-40))); // DH
17401749
}
@@ -1847,6 +1856,10 @@ class Assembler : public AbstractAssembler {
18471856
//inline void z_cgf(Register r1,int64_t d2, Register x2, Register b2);// compare (r1, *(d2_uimm12+x2+b2)) ; int64 <--> int32
18481857
inline void z_cg( Register r1, const Address &a); // compare (r1, *(a)) ; int64
18491858
inline void z_cg( Register r1, int64_t d2, Register x2, Register b2); // compare (r1, *(d2_imm20+x2+b2)) ; int64
1859+
// compare memory - immediate
1860+
inline void z_chhsi(int64_t d1, Register b1, int64_t i2); // compare (*d1(b1), i2_imm16) ; int16
1861+
inline void z_chsi( int64_t d1, Register b1, int64_t i2); // compare (*d1(b1), i2_imm16) ; int32
1862+
inline void z_cghsi(int64_t d1, Register b1, int64_t i2); // compare (*d1(b1), i2_imm16) ; int64
18501863

18511864
// compare logical instructions
18521865
// compare register
@@ -1862,6 +1875,10 @@ class Assembler : public AbstractAssembler {
18621875
inline void z_cly( Register r1, const Address& a); // compare (r1, *(a)) ; uint32
18631876
inline void z_clg( Register r1, const Address &a); // compare (r1, *(a) ; uint64
18641877
inline void z_clg( Register r1, int64_t d2, Register x2, Register b2);// compare (r1, *(d2_imm20+x2+b2) ; uint64
1878+
// compare memory - immediate
1879+
inline void z_clhhsi(int64_t d1, Register b1, int64_t i2); // compare (*d1(b1), i2_imm16) ; uint16
1880+
inline void z_clfhsi(int64_t d1, Register b1, int64_t i2); // compare (*d1(b1), i2_imm16) ; uint32
1881+
inline void z_clghsi(int64_t d1, Register b1, int64_t i2); // compare (*d1(b1), i2_imm16) ; uint64
18651882

18661883
// test under mask
18671884
inline void z_tmll(Register r1, int64_t i2); // test under mask, see docu
@@ -2435,6 +2452,7 @@ class Assembler : public AbstractAssembler {
24352452

24362453
inline void z_mvc(const Address& d, const Address& s, int64_t l); // move l bytes
24372454
inline void z_mvc(int64_t d1, int64_t l, Register b1, int64_t d2, Register b2); // move l+1 bytes
2455+
inline void z_mvcin(int64_t d1, int64_t l, Register b1, int64_t d2, Register b2); // move l+1 bytes
24382456
inline void z_mvcle(Register r1, Register r3, int64_t d2, Register b2=Z_R0); // move region of memory
24392457

24402458
inline void z_stfle(int64_t d2, Register b2); // store facility list extended

‎src/hotspot/cpu/s390/assembler_s390.inline.hpp

Lines changed: 11 additions & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -1,6 +1,6 @@
11
/*
2-
* Copyright (c) 2016, 2022, Oracle and/or its affiliates. All rights reserved.
3-
* Copyright (c) 2016, 2022 SAP SE. All rights reserved.
2+
* Copyright (c) 2016, 2023, Oracle and/or its affiliates. All rights reserved.
3+
* Copyright (c) 2016, 2023 SAP SE. All rights reserved.
44
* DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
55
*
66
* This code is free software; you can redistribute it and/or modify it
@@ -277,7 +277,8 @@ inline void Assembler::z_mvc(const Address& d, const Address& s, int64_t l) {
277277
assert(!d.has_index() && !s.has_index(), "Address operand can not be encoded.");
278278
z_mvc(d.disp(), l-1, d.base(), s.disp(), s.base());
279279
}
280-
inline void Assembler::z_mvc(int64_t d1, int64_t l, Register b1, int64_t d2, Register b2) { emit_48( MVC_ZOPC | uimm8(l, 8, 48) | rsmask_48(d1, b1) | rsmask_SS(d2, b2)); }
280+
inline void Assembler::z_mvc(int64_t d1, int64_t l, Register b1, int64_t d2, Register b2) { emit_48( MVC_ZOPC | uimm8(l, 8, 48) | rsmask_48(d1, b1) | rsmask_SS(d2, b2)); }
281+
inline void Assembler::z_mvcin(int64_t d1, int64_t l, Register b1, int64_t d2, Register b2) { emit_48( MVCIN_ZOPC | uimm8(l, 8, 48) | rsmask_48(d1, b1) | rsmask_SS(d2, b2)); }
281282
inline void Assembler::z_mvcle(Register r1, Register r3, int64_t d2, Register b2) { emit_32( MVCLE_ZOPC | reg(r1, 8, 32) | reg(r3, 12, 32) | rsmaskt_32(d2, b2)); }
282283

283284
inline void Assembler::z_mvhhi( int64_t d1, Register b1, int64_t i2) { emit_48( MVHHI_ZOPC | rsmask_48( d1, b1) | simm16(i2, 32, 48)); }
@@ -647,6 +648,9 @@ inline void Assembler::z_ch( Register r1, const Address &a) { z_ch(r1, a.disp()
647648
inline void Assembler::z_c( Register r1, const Address &a) { z_c( r1, a.disp(), a.indexOrR0(), a.baseOrR0()); }
648649
inline void Assembler::z_cy( Register r1, const Address &a) { z_cy(r1, a.disp(), a.indexOrR0(), a.baseOrR0()); }
649650
inline void Assembler::z_cg( Register r1, const Address &a) { z_cg(r1, a.disp(), a.indexOrR0(), a.baseOrR0()); }
651+
inline void Assembler::z_chhsi(int64_t d1, Register b1, int64_t i2) { emit_48( CHHSI_ZOPC | rsmask_48(d1, b1) | simm16(i2, 32, 48)); }
652+
inline void Assembler::z_chsi( int64_t d1, Register b1, int64_t i2) { emit_48( CHSI_ZOPC | rsmask_48(d1, b1) | simm16(i2, 32, 48)); }
653+
inline void Assembler::z_cghsi(int64_t d1, Register b1, int64_t i2) { emit_48( CGHSI_ZOPC | rsmask_48(d1, b1) | simm16(i2, 32, 48)); }
650654

651655

652656
inline void Assembler::z_clfi( Register r1, int64_t i2) { emit_48( CLFI_ZOPC | regt(r1, 8, 48) | uimm32(i2, 16, 48)); }
@@ -657,6 +661,9 @@ inline void Assembler::z_clg( Register r1, int64_t d2, Register x2, Register b2
657661
inline void Assembler::z_cl( Register r1, const Address &a) { z_cl( r1, a.disp(), a.indexOrR0(), a.baseOrR0()); }
658662
inline void Assembler::z_cly( Register r1, const Address &a) { z_cly(r1, a.disp(), a.indexOrR0(), a.baseOrR0()); }
659663
inline void Assembler::z_clg( Register r1, const Address &a) { z_clg(r1, a.disp(), a.indexOrR0(), a.baseOrR0()); }
664+
inline void Assembler::z_clhhsi(int64_t d1, Register b1, int64_t i2) { emit_48( CLHHSI_ZOPC | rsmask_48(d1, b1) | simm16(i2, 32, 48)); }
665+
inline void Assembler::z_clfhsi(int64_t d1, Register b1, int64_t i2) { emit_48( CLFHSI_ZOPC | rsmask_48(d1, b1) | simm16(i2, 32, 48)); }
666+
inline void Assembler::z_clghsi(int64_t d1, Register b1, int64_t i2) { emit_48( CLGHSI_ZOPC | rsmask_48(d1, b1) | simm16(i2, 32, 48)); }
660667

661668
inline void Assembler::z_clc(int64_t d1, int64_t l, Register b1, int64_t d2, Register b2) { emit_48( CLC_ZOPC | uimm8(l, 8, 48) | rsmask_48(d1, b1) | rsmask_SS(d2, b2)); }
662669
inline void Assembler::z_clcle(Register r1, Register r3, int64_t d2, Register b2) { emit_32( CLCLE_ZOPC | reg(r1, 8, 32) | reg(r3, 12, 32) | rsmaskt_32( d2, b2)); }
@@ -772,7 +779,6 @@ inline void Assembler::z_vleh( VectorRegister v1, int64_t d2, Register x2, Reg
772779
inline void Assembler::z_vlef( VectorRegister v1, int64_t d2, Register x2, Register b2, int64_t ix3){emit_48(VLEF_ZOPC | vreg(v1, 8) | rxmask_48(d2, x2, b2) | uimm4(ix3, 32, 48)); }
773780
inline void Assembler::z_vleg( VectorRegister v1, int64_t d2, Register x2, Register b2, int64_t ix3){emit_48(VLEG_ZOPC | vreg(v1, 8) | rxmask_48(d2, x2, b2) | uimm4(ix3, 32, 48)); }
774781

775-
776782
// Gather/Scatter
777783
inline void Assembler::z_vgef( VectorRegister v1, int64_t d2, VectorRegister vx2, Register b2, int64_t ix3) {emit_48(VGEF_ZOPC | vreg(v1, 8) | rvmask_48(d2, vx2, b2) | uimm4(ix3, 32, 48)); }
778784
inline void Assembler::z_vgeg( VectorRegister v1, int64_t d2, VectorRegister vx2, Register b2, int64_t ix3) {emit_48(VGEG_ZOPC | vreg(v1, 8) | rvmask_48(d2, vx2, b2) | uimm4(ix3, 32, 48)); }
@@ -1378,7 +1384,7 @@ inline void Assembler::z_brz( Label& L) { z_brc(bcondZero, target(L)); }
13781384
inline void Assembler::z_brnz( Label& L) { z_brc(bcondNotZero, target(L)); }
13791385
inline void Assembler::z_braz( Label& L) { z_brc(bcondAllZero, target(L)); }
13801386
inline void Assembler::z_brnaz( Label& L) { z_brc(bcondNotAllZero, target(L)); }
1381-
inline void Assembler::z_brnp( Label& L) { z_brc( bcondNotPositive, target( L)); }
1387+
inline void Assembler::z_brnp( Label& L) { z_brc(bcondNotPositive, target( L)); }
13821388
inline void Assembler::z_btrue( Label& L) { z_brc(bcondAllOne, target(L)); }
13831389
inline void Assembler::z_bfalse(Label& L) { z_brc(bcondAllZero, target(L)); }
13841390
inline void Assembler::z_bvat( Label& L) { z_brc(bcondVAlltrue, target(L)); }

‎src/hotspot/cpu/s390/macroAssembler_s390.cpp

Lines changed: 31 additions & 13 deletions
Original file line numberDiff line numberDiff line change
@@ -1,6 +1,6 @@
11
/*
22
* Copyright (c) 2016, 2023, Oracle and/or its affiliates. All rights reserved.
3-
* Copyright (c) 2016, 2022 SAP SE. All rights reserved.
3+
* Copyright (c) 2016, 2023 SAP SE. All rights reserved.
44
* DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
55
*
66
* This code is free software; you can redistribute it and/or modify it
@@ -1052,29 +1052,47 @@ int MacroAssembler::preset_reg(Register r, unsigned long pattern, int pattern_le
10521052
}
10531053
#endif
10541054

1055-
// addr: Address descriptor of memory to clear index register will not be used !
1055+
// addr: Address descriptor of memory to clear. Index register will not be used!
10561056
// size: Number of bytes to clear.
1057+
// condition code will not be preserved.
10571058
// !!! DO NOT USE THEM FOR ATOMIC MEMORY CLEARING !!!
10581059
// !!! Use store_const() instead !!!
1059-
void MacroAssembler::clear_mem(const Address& addr, unsigned size) {
1060-
guarantee(size <= 256, "MacroAssembler::clear_mem: size too large");
1061-
1062-
if (size == 1) {
1063-
z_mvi(addr, 0);
1064-
return;
1065-
}
1060+
void MacroAssembler::clear_mem(const Address& addr, unsigned int size) {
1061+
guarantee((addr.disp() + size) <= 4096, "MacroAssembler::clear_mem: size too large");
10661062

10671063
switch (size) {
1068-
case 2: z_mvhhi(addr, 0);
1064+
case 0:
10691065
return;
1070-
case 4: z_mvhi(addr, 0);
1066+
case 1:
1067+
z_mvi(addr, 0);
10711068
return;
1072-
case 8: z_mvghi(addr, 0);
1069+
case 2:
1070+
z_mvhhi(addr, 0);
1071+
return;
1072+
case 4:
1073+
z_mvhi(addr, 0);
1074+
return;
1075+
case 8:
1076+
z_mvghi(addr, 0);
10731077
return;
10741078
default: ; // Fallthru to xc.
10751079
}
10761080

1077-
z_xc(addr, size, addr);
1081+
// Caution: the emitter with Address operands does implicitly decrement the length
1082+
if (size <= 256) {
1083+
z_xc(addr, size, addr);
1084+
} else {
1085+
unsigned int offset = addr.disp();
1086+
unsigned int incr = 256;
1087+
for (unsigned int i = 0; i <= size-incr; i += incr) {
1088+
z_xc(offset, incr - 1, addr.base(), offset, addr.base());
1089+
offset += incr;
1090+
}
1091+
unsigned int rest = size - (offset - addr.disp());
1092+
if (size > 0) {
1093+
z_xc(offset, rest-1, addr.base(), offset, addr.base());
1094+
}
1095+
}
10781096
}
10791097

10801098
void MacroAssembler::align(int modulus) {

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