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Merge branch 'master' into 8264873.cha.split
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Vladimir Ivanov committed Apr 9, 2021
2 parents 071de4c + 76bd313 commit e38b995
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Showing 160 changed files with 4,736 additions and 1,479 deletions.
6 changes: 4 additions & 2 deletions make/Main.gmk
View file
@@ -1,5 +1,5 @@
#
# Copyright (c) 2011, 2020, Oracle and/or its affiliates. All rights reserved.
# Copyright (c) 2011, 2021, Oracle and/or its affiliates. All rights reserved.
# DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
#
# This code is free software; you can redistribute it and/or modify it
Expand Down Expand Up @@ -92,9 +92,11 @@ $(eval $(call SetupTarget, buildtools-modules, \
MAKEFILE := CompileModuleTools, \
))

# interim-langtools is needed by hotspot only when $(INCLUDE_GRAAL) is true
GRAAL_INTERIM_LANGTOOLS_true = interim-langtools
$(eval $(call SetupTarget, buildtools-hotspot, \
MAKEFILE := CompileToolsHotspot, \
DEPS := interim-langtools, \
DEPS := $(GRAAL_INTERIM_LANGTOOLS_$(INCLUDE_GRAAL)), \
))

################################################################################
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12 changes: 11 additions & 1 deletion make/autoconf/flags-other.m4
View file
@@ -1,5 +1,5 @@
#
# Copyright (c) 2011, 2020, Oracle and/or its affiliates. All rights reserved.
# Copyright (c) 2011, 2021, Oracle and/or its affiliates. All rights reserved.
# DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
#
# This code is free software; you can redistribute it and/or modify it
Expand Down Expand Up @@ -78,6 +78,16 @@ AC_DEFUN([FLAGS_SETUP_ASFLAGS],
[
if test "x$OPENJDK_TARGET_OS" = xmacosx; then
JVM_BASIC_ASFLAGS="-x assembler-with-cpp -mno-omit-leaf-frame-pointer -mstack-alignment=16"
# Fix linker warning.
# Code taken from make/autoconf/flags-cflags.m4 and adapted.
JVM_BASIC_ASFLAGS+="-DMAC_OS_X_VERSION_MIN_REQUIRED=$MACOSX_VERSION_MIN_NODOTS \
-mmacosx-version-min=$MACOSX_VERSION_MIN"
if test -n "$MACOSX_VERSION_MAX"; then
JVM_BASIC_ASFLAGS+="$OS_CFLAGS \
-DMAC_OS_X_VERSION_MAX_ALLOWED=$MACOSX_VERSION_MAX_NODOTS"
fi
fi
])

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5 changes: 4 additions & 1 deletion make/scripts/genExceptions.sh
View file
@@ -1,6 +1,6 @@
#! /bin/sh
#
# Copyright (c) 2000, 2019, Oracle and/or its affiliates. All rights reserved.
# Copyright (c) 2000, 2021, Oracle and/or its affiliates. All rights reserved.
# DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
#
# This code is free software; you can redistribute it and/or modify it
Expand Down Expand Up @@ -68,6 +68,9 @@ __END__

cat >>$out <<__END__
/**
* The $ARG_PHRASE.
*/
private $ARG_TYPE $ARG_ID;
/**
Expand Down
14 changes: 0 additions & 14 deletions src/hotspot/cpu/aarch64/aarch64.ad
View file
Expand Up @@ -1782,20 +1782,6 @@ int MachCallNativeNode::ret_addr_offset() {
}
}

// Indicate if the safepoint node needs the polling page as an input

// the shared code plants the oop data at the start of the generated
// code for the safepoint node and that needs ot be at the load
// instruction itself. so we cannot plant a mov of the safepoint poll
// address followed by a load. setting this to true means the mov is
// scheduled as a prior instruction. that's better for scheduling
// anyway.

bool SafePointNode::needs_polling_address_input()
{
return true;
}

//=============================================================================

#ifndef PRODUCT
Expand Down
45 changes: 45 additions & 0 deletions src/hotspot/cpu/aarch64/aarch64_neon.ad
View file
Expand Up @@ -2842,6 +2842,51 @@ instruct vnot2L(vecX dst, vecX src, immL_M1 m1)
ins_pipe(pipe_class_default);
%}

// ------------------------------ Vector and_not -------------------------------

instruct vand_not2I(vecD dst, vecD src1, vecD src2, immI_M1 m1)
%{
predicate(n->as_Vector()->length_in_bytes() == 8);
match(Set dst (AndV src1 (XorV src2 (ReplicateB m1))));
match(Set dst (AndV src1 (XorV src2 (ReplicateS m1))));
match(Set dst (AndV src1 (XorV src2 (ReplicateI m1))));
ins_cost(INSN_COST);
format %{ "bic $dst, T8B, $src1, $src2\t# vector (8B)" %}
ins_encode %{
__ bic(as_FloatRegister($dst$$reg), __ T8B,
as_FloatRegister($src1$$reg), as_FloatRegister($src2$$reg));
%}
ins_pipe(pipe_class_default);
%}

instruct vand_not4I(vecX dst, vecX src1, vecX src2, immI_M1 m1)
%{
predicate(n->as_Vector()->length_in_bytes() == 16);
match(Set dst (AndV src1 (XorV src2 (ReplicateB m1))));
match(Set dst (AndV src1 (XorV src2 (ReplicateS m1))));
match(Set dst (AndV src1 (XorV src2 (ReplicateI m1))));
ins_cost(INSN_COST);
format %{ "bic $dst, T16B, $src1, $src2\t# vector (16B)" %}
ins_encode %{
__ bic(as_FloatRegister($dst$$reg), __ T16B,
as_FloatRegister($src1$$reg), as_FloatRegister($src2$$reg));
%}
ins_pipe(pipe_class_default);
%}

instruct vand_not2L(vecX dst, vecX src1, vecX src2, immL_M1 m1)
%{
predicate(n->as_Vector()->length_in_bytes() == 16);
match(Set dst (AndV src1 (XorV src2 (ReplicateL m1))));
ins_cost(INSN_COST);
format %{ "bic $dst, T16B, $src1, $src2\t# vector (16B)" %}
ins_encode %{
__ bic(as_FloatRegister($dst$$reg), __ T16B,
as_FloatRegister($src1$$reg), as_FloatRegister($src2$$reg));
%}
ins_pipe(pipe_class_default);
%}

// ------------------------------ Vector max/min -------------------------------

instruct vmax8B(vecD dst, vecD src1, vecD src2)
Expand Down
32 changes: 29 additions & 3 deletions src/hotspot/cpu/aarch64/aarch64_neon_ad.m4
View file
Expand Up @@ -1036,6 +1036,32 @@ VECTOR_NOT(2, I, D, 8, 8B)
VECTOR_NOT(4, I, X, 16, 16B)
VECTOR_NOT(2, L, X, 16, 16B)
undefine(MATCH_RULE)
// ------------------------------ Vector and_not -------------------------------
dnl
define(`MATCH_RULE', `ifelse($1, I,
`match(Set dst (AndV src1 (XorV src2 (ReplicateB m1))));
match(Set dst (AndV src1 (XorV src2 (ReplicateS m1))));
match(Set dst (AndV src1 (XorV src2 (ReplicateI m1))));',
`match(Set dst (AndV src1 (XorV src2 (ReplicateL m1))));')')dnl
dnl
define(`VECTOR_AND_NOT', `
instruct vand_not$1$2`'(vec$3 dst, vec$3 src1, vec$3 src2, imm$2_M1 m1)
%{
predicate(n->as_Vector()->length_in_bytes() == $4);
MATCH_RULE($2)
ins_cost(INSN_COST);
format %{ "bic $dst, T$5, $src1, $src2\t# vector ($5)" %}
ins_encode %{
__ bic(as_FloatRegister($dst$$reg), __ T$5,
as_FloatRegister($src1$$reg), as_FloatRegister($src2$$reg));
%}
ins_pipe(pipe_class_default);
%}')dnl
dnl $1 $2 $3 $4 $5
VECTOR_AND_NOT(2, I, D, 8, 8B)
VECTOR_AND_NOT(4, I, X, 16, 16B)
VECTOR_AND_NOT(2, L, X, 16, 16B)
undefine(MATCH_RULE)
dnl
// ------------------------------ Vector max/min -------------------------------
dnl
Expand Down Expand Up @@ -1090,7 +1116,7 @@ instruct v$1`'2L`'(vecX dst, vecX src1, vecX src2)
%}
ins_pipe(vdop128);
%}')dnl
dnl $1 $2 $3 $4
dnl $1 $2 $3 $4
VECTOR_MAX_MIN_LONG(max, Max, src1, src2)
VECTOR_MAX_MIN_LONG(min, Min, src2, src1)
dnl
Expand Down Expand Up @@ -1871,7 +1897,7 @@ instruct vsqrt$2$3`'(vec$4 dst, vec$4 src)
%}
ins_pipe(v`'ifelse($2$3, 2F, unop, sqrt)_fp`'ifelse($4, D, 64, 128));
%}')dnl
dnl $1 $2 $3 $4 $5
dnl $1 $2 $3 $4 $5
VSQRT(fsqrt, 2, F, D, S)
VSQRT(fsqrt, 4, F, X, S)
VSQRT(fsqrt, 2, D, X, D)
Expand Down Expand Up @@ -1912,7 +1938,7 @@ instruct v$3$5$6`'(vec$7 dst, vec$7 src1, vec$7 src2)
%}')dnl

// --------------------------------- AND --------------------------------------
dnl $1 $2 $3 $4 $5 $6 $7
dnl $1 $2 $3 $4 $5 $6 $7
VLOGICAL(and, andr, and, And, 8, B, D)
VLOGICAL(and, andr, and, And, 16, B, X)

Expand Down
60 changes: 60 additions & 0 deletions src/hotspot/cpu/aarch64/aarch64_sve.ad
View file
Expand Up @@ -453,6 +453,66 @@ instruct vxor(vReg dst, vReg src1, vReg src2) %{
ins_pipe(pipe_slow);
%}

// vector not

instruct vnotI(vReg dst, vReg src, immI_M1 m1) %{
predicate(UseSVE > 0 && n->as_Vector()->length_in_bytes() >= 16);
match(Set dst (XorV src (ReplicateB m1)));
match(Set dst (XorV src (ReplicateS m1)));
match(Set dst (XorV src (ReplicateI m1)));
ins_cost(SVE_COST);
format %{ "sve_not $dst, $src\t# vector (sve) B/H/S" %}
ins_encode %{
__ sve_not(as_FloatRegister($dst$$reg), __ D,
ptrue, as_FloatRegister($src$$reg));
%}
ins_pipe(pipe_slow);
%}

instruct vnotL(vReg dst, vReg src, immL_M1 m1) %{
predicate(UseSVE > 0 && n->as_Vector()->length_in_bytes() >= 16);
match(Set dst (XorV src (ReplicateL m1)));
ins_cost(SVE_COST);
format %{ "sve_not $dst, $src\t# vector (sve) D" %}
ins_encode %{
__ sve_not(as_FloatRegister($dst$$reg), __ D,
ptrue, as_FloatRegister($src$$reg));
%}
ins_pipe(pipe_slow);
%}


// vector and_not

instruct vand_notI(vReg dst, vReg src1, vReg src2, immI_M1 m1) %{
predicate(UseSVE > 0 && n->as_Vector()->length_in_bytes() >= 16);
match(Set dst (AndV src1 (XorV src2 (ReplicateB m1))));
match(Set dst (AndV src1 (XorV src2 (ReplicateS m1))));
match(Set dst (AndV src1 (XorV src2 (ReplicateI m1))));
ins_cost(SVE_COST);
format %{ "sve_bic $dst, $src1, $src2\t# vector (sve) B/H/S" %}
ins_encode %{
__ sve_bic(as_FloatRegister($dst$$reg),
as_FloatRegister($src1$$reg),
as_FloatRegister($src2$$reg));
%}
ins_pipe(pipe_slow);
%}

instruct vand_notL(vReg dst, vReg src1, vReg src2, immL_M1 m1) %{
predicate(UseSVE > 0 && n->as_Vector()->length_in_bytes() >= 16);
match(Set dst (AndV src1 (XorV src2 (ReplicateL m1))));
ins_cost(SVE_COST);
format %{ "sve_bic $dst, $src1, $src2\t# vector (sve) D" %}
ins_encode %{
__ sve_bic(as_FloatRegister($dst$$reg),
as_FloatRegister($src1$$reg),
as_FloatRegister($src2$$reg));
%}
ins_pipe(pipe_slow);
%}


// vector float div

instruct vdivF(vReg dst_src1, vReg src2) %{
Expand Down
51 changes: 51 additions & 0 deletions src/hotspot/cpu/aarch64/aarch64_sve_ad.m4
View file
Expand Up @@ -316,6 +316,57 @@ BINARY_OP_UNSIZED(vor, OrV, 16, sve_orr)

// vector xor
BINARY_OP_UNSIZED(vxor, XorV, 16, sve_eor)

// vector not
dnl
define(`MATCH_RULE', `ifelse($1, I,
`match(Set dst (XorV src (ReplicateB m1)));
match(Set dst (XorV src (ReplicateS m1)));
match(Set dst (XorV src (ReplicateI m1)));',
`match(Set dst (XorV src (ReplicateL m1)));')')dnl
dnl
define(`VECTOR_NOT', `
instruct vnot$1`'(vReg dst, vReg src, imm$1_M1 m1) %{
predicate(UseSVE > 0 && n->as_Vector()->length_in_bytes() >= 16);
MATCH_RULE($1)
ins_cost(SVE_COST);
format %{ "sve_not $dst, $src\t# vector (sve) $2" %}
ins_encode %{
__ sve_not(as_FloatRegister($dst$$reg), __ D,
ptrue, as_FloatRegister($src$$reg));
%}
ins_pipe(pipe_slow);
%}')dnl
dnl $1,$2
VECTOR_NOT(I, B/H/S)
VECTOR_NOT(L, D)
undefine(MATCH_RULE)

// vector and_not
dnl
define(`MATCH_RULE', `ifelse($1, I,
`match(Set dst (AndV src1 (XorV src2 (ReplicateB m1))));
match(Set dst (AndV src1 (XorV src2 (ReplicateS m1))));
match(Set dst (AndV src1 (XorV src2 (ReplicateI m1))));',
`match(Set dst (AndV src1 (XorV src2 (ReplicateL m1))));')')dnl
dnl
define(`VECTOR_AND_NOT', `
instruct vand_not$1`'(vReg dst, vReg src1, vReg src2, imm$1_M1 m1) %{
predicate(UseSVE > 0 && n->as_Vector()->length_in_bytes() >= 16);
MATCH_RULE($1)
ins_cost(SVE_COST);
format %{ "sve_bic $dst, $src1, $src2\t# vector (sve) $2" %}
ins_encode %{
__ sve_bic(as_FloatRegister($dst$$reg),
as_FloatRegister($src1$$reg),
as_FloatRegister($src2$$reg));
%}
ins_pipe(pipe_slow);
%}')dnl
dnl $1,$2
VECTOR_AND_NOT(I, B/H/S)
VECTOR_AND_NOT(L, D)
undefine(MATCH_RULE)
dnl
dnl VDIVF($1, $2 , $3 )
dnl VDIVF(name_suffix, size, min_vec_len)
Expand Down
4 changes: 4 additions & 0 deletions src/hotspot/cpu/aarch64/assembler_aarch64.hpp
View file
Expand Up @@ -2392,6 +2392,7 @@ void mvnw(Register Rd, Register Rm,

INSN(addv, 0, 0b100001, true); // accepted arrangements: T8B, T16B, T4H, T8H, T2S, T4S, T2D
INSN(subv, 1, 0b100001, true); // accepted arrangements: T8B, T16B, T4H, T8H, T2S, T4S, T2D
INSN(uqsubv, 1, 0b001011, true); // accepted arrangements: T8B, T16B, T4H, T8H, T2S, T4S, T2D
INSN(mulv, 0, 0b100111, false); // accepted arrangements: T8B, T16B, T4H, T8H, T2S, T4S
INSN(mlav, 0, 0b100101, false); // accepted arrangements: T8B, T16B, T4H, T8H, T2S, T4S
INSN(mlsv, 1, 0b100101, false); // accepted arrangements: T8B, T16B, T4H, T8H, T2S, T4S
Expand All @@ -2406,6 +2407,7 @@ void mvnw(Register Rd, Register Rm,
INSN(cmeq, 1, 0b100011, true); // accepted arrangements: T8B, T16B, T4H, T8H, T2S, T4S, T2D
INSN(cmgt, 0, 0b001101, true); // accepted arrangements: T8B, T16B, T4H, T8H, T2S, T4S, T2D
INSN(cmge, 0, 0b001111, true); // accepted arrangements: T8B, T16B, T4H, T8H, T2S, T4S, T2D
INSN(cmhi, 1, 0b001101, true); // accepted arrangements: T8B, T16B, T4H, T8H, T2S, T4S, T2D

#undef INSN

Expand All @@ -2426,6 +2428,7 @@ void mvnw(Register Rd, Register Rm,
INSN(notr, 1, 0b100000010110, 0); // accepted arrangements: T8B, T16B
INSN(addv, 0, 0b110001101110, 1); // accepted arrangements: T8B, T16B, T4H, T8H, T4S
INSN(smaxv, 0, 0b110000101010, 1); // accepted arrangements: T8B, T16B, T4H, T8H, T4S
INSN(umaxv, 1, 0b110000101010, 1); // accepted arrangements: T8B, T16B, T4H, T8H, T4S
INSN(sminv, 0, 0b110001101010, 1); // accepted arrangements: T8B, T16B, T4H, T8H, T4S
INSN(uminv, 1, 0b110001101010, 1); // accepted arrangements: T8B, T16B, T4H, T8H, T4S
INSN(cls, 0, 0b100000010010, 2); // accepted arrangements: T8B, T16B, T4H, T8H, T2S, T4S
Expand Down Expand Up @@ -3060,6 +3063,7 @@ void mvnw(Register Rd, Register Rm,
INSN(sve_and, 0b00);
INSN(sve_eor, 0b10);
INSN(sve_orr, 0b01);
INSN(sve_bic, 0b11);
#undef INSN

// SVE shift immediate - unpredicated
Expand Down

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