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author
Jatin Bhateja
committed
8277239: SIGSEGV in vrshift_reg_maskedNode::emit
Reviewed-by: sviswanathan, dlong
1 parent 8683de5 commit e529865

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5 files changed

+130
-61
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5 files changed

+130
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‎src/hotspot/cpu/x86/x86.ad

Lines changed: 76 additions & 28 deletions
Original file line numberDiff line numberDiff line change
@@ -6196,7 +6196,7 @@ instruct vshiftcnt(vec dst, rRegI cnt) %{
61966196

61976197
// Byte vector shift
61986198
instruct vshiftB(vec dst, vec src, vec shift, vec tmp, rRegI scratch) %{
6199-
predicate(Matcher::vector_length(n) <= 8 && VectorNode::is_vshift_cnt(n->in(2)));
6199+
predicate(Matcher::vector_length(n) <= 8 && !n->as_ShiftV()->is_var_shift());
62006200
match(Set dst ( LShiftVB src shift));
62016201
match(Set dst ( RShiftVB src shift));
62026202
match(Set dst (URShiftVB src shift));
@@ -6216,7 +6216,7 @@ instruct vshiftB(vec dst, vec src, vec shift, vec tmp, rRegI scratch) %{
62166216
%}
62176217

62186218
instruct vshift16B(vec dst, vec src, vec shift, vec tmp1, vec tmp2, rRegI scratch) %{
6219-
predicate(Matcher::vector_length(n) == 16 && VectorNode::is_vshift_cnt(n->in(2)) &&
6219+
predicate(Matcher::vector_length(n) == 16 && !n->as_ShiftV()->is_var_shift() &&
62206220
UseAVX <= 1);
62216221
match(Set dst ( LShiftVB src shift));
62226222
match(Set dst ( RShiftVB src shift));
@@ -6241,7 +6241,7 @@ instruct vshift16B(vec dst, vec src, vec shift, vec tmp1, vec tmp2, rRegI scratc
62416241
%}
62426242

62436243
instruct vshift16B_avx(vec dst, vec src, vec shift, vec tmp, rRegI scratch) %{
6244-
predicate(Matcher::vector_length(n) == 16 && VectorNode::is_vshift_cnt(n->in(2)) &&
6244+
predicate(Matcher::vector_length(n) == 16 && !n->as_ShiftV()->is_var_shift() &&
62456245
UseAVX > 1);
62466246
match(Set dst ( LShiftVB src shift));
62476247
match(Set dst ( RShiftVB src shift));
@@ -6262,7 +6262,7 @@ instruct vshift16B_avx(vec dst, vec src, vec shift, vec tmp, rRegI scratch) %{
62626262
%}
62636263

62646264
instruct vshift32B_avx(vec dst, vec src, vec shift, vec tmp, rRegI scratch) %{
6265-
predicate(Matcher::vector_length(n) == 32 && VectorNode::is_vshift_cnt(n->in(2)));
6265+
predicate(Matcher::vector_length(n) == 32 && !n->as_ShiftV()->is_var_shift());
62666266
match(Set dst ( LShiftVB src shift));
62676267
match(Set dst ( RShiftVB src shift));
62686268
match(Set dst (URShiftVB src shift));
@@ -6287,7 +6287,7 @@ instruct vshift32B_avx(vec dst, vec src, vec shift, vec tmp, rRegI scratch) %{
62876287
%}
62886288

62896289
instruct vshift64B_avx(vec dst, vec src, vec shift, vec tmp1, vec tmp2, rRegI scratch) %{
6290-
predicate(Matcher::vector_length(n) == 64 && VectorNode::is_vshift_cnt(n->in(2)));
6290+
predicate(Matcher::vector_length(n) == 64 && !n->as_ShiftV()->is_var_shift());
62916291
match(Set dst ( LShiftVB src shift));
62926292
match(Set dst (RShiftVB src shift));
62936293
match(Set dst (URShiftVB src shift));
@@ -6320,7 +6320,7 @@ instruct vshift64B_avx(vec dst, vec src, vec shift, vec tmp1, vec tmp2, rRegI sc
63206320
// unsigned values.
63216321
// Shorts/Chars vector left shift
63226322
instruct vshiftS(vec dst, vec src, vec shift) %{
6323-
predicate(VectorNode::is_vshift_cnt(n->in(2)));
6323+
predicate(!n->as_ShiftV()->is_var_shift());
63246324
match(Set dst ( LShiftVS src shift));
63256325
match(Set dst ( RShiftVS src shift));
63266326
match(Set dst (URShiftVS src shift));
@@ -6351,7 +6351,7 @@ instruct vshiftS(vec dst, vec src, vec shift) %{
63516351

63526352
// Integers vector left shift
63536353
instruct vshiftI(vec dst, vec src, vec shift) %{
6354-
predicate(VectorNode::is_vshift_cnt(n->in(2)));
6354+
predicate(!n->as_ShiftV()->is_var_shift());
63556355
match(Set dst ( LShiftVI src shift));
63566356
match(Set dst ( RShiftVI src shift));
63576357
match(Set dst (URShiftVI src shift));
@@ -6405,7 +6405,7 @@ instruct vshiftI_imm(vec dst, vec src, immI8 shift) %{
64056405

64066406
// Longs vector shift
64076407
instruct vshiftL(vec dst, vec src, vec shift) %{
6408-
predicate(VectorNode::is_vshift_cnt(n->in(2)));
6408+
predicate(!n->as_ShiftV()->is_var_shift());
64096409
match(Set dst ( LShiftVL src shift));
64106410
match(Set dst (URShiftVL src shift));
64116411
effect(TEMP dst, USE src, USE shift);
@@ -6446,7 +6446,7 @@ instruct vshiftL_imm(vec dst, vec src, immI8 shift) %{
64466446
// -------------------ArithmeticRightShift -----------------------------------
64476447
// Long vector arithmetic right shift
64486448
instruct vshiftL_arith_reg(vec dst, vec src, vec shift, vec tmp, rRegI scratch) %{
6449-
predicate(VectorNode::is_vshift_cnt(n->in(2)) && UseAVX <= 2);
6449+
predicate(!n->as_ShiftV()->is_var_shift() && UseAVX <= 2);
64506450
match(Set dst (RShiftVL src shift));
64516451
effect(TEMP dst, TEMP tmp, TEMP scratch);
64526452
format %{ "vshiftq $dst,$src,$shift" %}
@@ -6475,7 +6475,7 @@ instruct vshiftL_arith_reg(vec dst, vec src, vec shift, vec tmp, rRegI scratch)
64756475
%}
64766476

64776477
instruct vshiftL_arith_reg_evex(vec dst, vec src, vec shift) %{
6478-
predicate(VectorNode::is_vshift_cnt(n->in(2)) && UseAVX > 2);
6478+
predicate(!n->as_ShiftV()->is_var_shift() && UseAVX > 2);
64796479
match(Set dst (RShiftVL src shift));
64806480
format %{ "vshiftq $dst,$src,$shift" %}
64816481
ins_encode %{
@@ -6489,7 +6489,7 @@ instruct vshiftL_arith_reg_evex(vec dst, vec src, vec shift) %{
64896489
// Byte variable shift
64906490
instruct vshift8B_var_nobw(vec dst, vec src, vec shift, vec vtmp, rRegP scratch) %{
64916491
predicate(Matcher::vector_length(n) <= 8 &&
6492-
!VectorNode::is_vshift_cnt(n->in(2)) &&
6492+
n->as_ShiftV()->is_var_shift() &&
64936493
!VM_Version::supports_avx512bw());
64946494
match(Set dst ( LShiftVB src shift));
64956495
match(Set dst ( RShiftVB src shift));
@@ -6509,7 +6509,7 @@ instruct vshift8B_var_nobw(vec dst, vec src, vec shift, vec vtmp, rRegP scratch)
65096509

65106510
instruct vshift16B_var_nobw(vec dst, vec src, vec shift, vec vtmp1, vec vtmp2, rRegP scratch) %{
65116511
predicate(Matcher::vector_length(n) == 16 &&
6512-
!VectorNode::is_vshift_cnt(n->in(2)) &&
6512+
n->as_ShiftV()->is_var_shift() &&
65136513
!VM_Version::supports_avx512bw());
65146514
match(Set dst ( LShiftVB src shift));
65156515
match(Set dst ( RShiftVB src shift));
@@ -6537,7 +6537,7 @@ instruct vshift16B_var_nobw(vec dst, vec src, vec shift, vec vtmp1, vec vtmp2, r
65376537

65386538
instruct vshift32B_var_nobw(vec dst, vec src, vec shift, vec vtmp1, vec vtmp2, vec vtmp3, vec vtmp4, rRegP scratch) %{
65396539
predicate(Matcher::vector_length(n) == 32 &&
6540-
!VectorNode::is_vshift_cnt(n->in(2)) &&
6540+
n->as_ShiftV()->is_var_shift() &&
65416541
!VM_Version::supports_avx512bw());
65426542
match(Set dst ( LShiftVB src shift));
65436543
match(Set dst ( RShiftVB src shift));
@@ -6573,7 +6573,7 @@ instruct vshift32B_var_nobw(vec dst, vec src, vec shift, vec vtmp1, vec vtmp2, v
65736573

65746574
instruct vshiftB_var_evex_bw(vec dst, vec src, vec shift, vec vtmp, rRegP scratch) %{
65756575
predicate(Matcher::vector_length(n) <= 32 &&
6576-
!VectorNode::is_vshift_cnt(n->in(2)) &&
6576+
n->as_ShiftV()->is_var_shift() &&
65776577
VM_Version::supports_avx512bw());
65786578
match(Set dst ( LShiftVB src shift));
65796579
match(Set dst ( RShiftVB src shift));
@@ -6592,7 +6592,7 @@ instruct vshiftB_var_evex_bw(vec dst, vec src, vec shift, vec vtmp, rRegP scratc
65926592

65936593
instruct vshift64B_var_evex_bw(vec dst, vec src, vec shift, vec vtmp1, vec vtmp2, rRegP scratch) %{
65946594
predicate(Matcher::vector_length(n) == 64 &&
6595-
!VectorNode::is_vshift_cnt(n->in(2)) &&
6595+
n->as_ShiftV()->is_var_shift() &&
65966596
VM_Version::supports_avx512bw());
65976597
match(Set dst ( LShiftVB src shift));
65986598
match(Set dst ( RShiftVB src shift));
@@ -6616,7 +6616,7 @@ instruct vshift64B_var_evex_bw(vec dst, vec src, vec shift, vec vtmp1, vec vtmp2
66166616
// Short variable shift
66176617
instruct vshift8S_var_nobw(vec dst, vec src, vec shift, vec vtmp, rRegP scratch) %{
66186618
predicate(Matcher::vector_length(n) <= 8 &&
6619-
!VectorNode::is_vshift_cnt(n->in(2)) &&
6619+
n->as_ShiftV()->is_var_shift() &&
66206620
!VM_Version::supports_avx512bw());
66216621
match(Set dst ( LShiftVS src shift));
66226622
match(Set dst ( RShiftVS src shift));
@@ -6641,7 +6641,7 @@ instruct vshift8S_var_nobw(vec dst, vec src, vec shift, vec vtmp, rRegP scratch)
66416641

66426642
instruct vshift16S_var_nobw(vec dst, vec src, vec shift, vec vtmp1, vec vtmp2, rRegP scratch) %{
66436643
predicate(Matcher::vector_length(n) == 16 &&
6644-
!VectorNode::is_vshift_cnt(n->in(2)) &&
6644+
n->as_ShiftV()->is_var_shift() &&
66456645
!VM_Version::supports_avx512bw());
66466646
match(Set dst ( LShiftVS src shift));
66476647
match(Set dst ( RShiftVS src shift));
@@ -6676,7 +6676,7 @@ instruct vshift16S_var_nobw(vec dst, vec src, vec shift, vec vtmp1, vec vtmp2, r
66766676
%}
66776677

66786678
instruct vshift16S_var_evex_bw(vec dst, vec src, vec shift) %{
6679-
predicate(!VectorNode::is_vshift_cnt(n->in(2)) &&
6679+
predicate(n->as_ShiftV()->is_var_shift() &&
66806680
VM_Version::supports_avx512bw());
66816681
match(Set dst ( LShiftVS src shift));
66826682
match(Set dst ( RShiftVS src shift));
@@ -6697,7 +6697,7 @@ instruct vshift16S_var_evex_bw(vec dst, vec src, vec shift) %{
66976697

66986698
//Integer variable shift
66996699
instruct vshiftI_var(vec dst, vec src, vec shift) %{
6700-
predicate(!VectorNode::is_vshift_cnt(n->in(2)));
6700+
predicate(n->as_ShiftV()->is_var_shift());
67016701
match(Set dst ( LShiftVI src shift));
67026702
match(Set dst ( RShiftVI src shift));
67036703
match(Set dst (URShiftVI src shift));
@@ -6714,7 +6714,7 @@ instruct vshiftI_var(vec dst, vec src, vec shift) %{
67146714

67156715
//Long variable shift
67166716
instruct vshiftL_var(vec dst, vec src, vec shift) %{
6717-
predicate(!VectorNode::is_vshift_cnt(n->in(2)));
6717+
predicate(n->as_ShiftV()->is_var_shift());
67186718
match(Set dst ( LShiftVL src shift));
67196719
match(Set dst (URShiftVL src shift));
67206720
format %{ "vector_varshift_long $dst,$src,$shift\t!" %}
@@ -6731,7 +6731,7 @@ instruct vshiftL_var(vec dst, vec src, vec shift) %{
67316731
//Long variable right shift arithmetic
67326732
instruct vshiftL_arith_var(vec dst, vec src, vec shift, vec vtmp) %{
67336733
predicate(Matcher::vector_length(n) <= 4 &&
6734-
!VectorNode::is_vshift_cnt(n->in(2)) &&
6734+
n->as_ShiftV()->is_var_shift() &&
67356735
UseAVX == 2);
67366736
match(Set dst (RShiftVL src shift));
67376737
effect(TEMP dst, TEMP vtmp);
@@ -6746,7 +6746,7 @@ instruct vshiftL_arith_var(vec dst, vec src, vec shift, vec vtmp) %{
67466746
%}
67476747

67486748
instruct vshiftL_arith_var_evex(vec dst, vec src, vec shift) %{
6749-
predicate(!VectorNode::is_vshift_cnt(n->in(2)) &&
6749+
predicate(n->as_ShiftV()->is_var_shift() &&
67506750
UseAVX > 2);
67516751
match(Set dst (RShiftVL src shift));
67526752
format %{ "vector_varfshift_long $dst,$src,$shift\t!" %}
@@ -9033,6 +9033,7 @@ instruct vlshift_imm_masked(vec dst, immI8 shift, kReg mask) %{
90339033
%}
90349034

90359035
instruct vlshift_reg_masked(vec dst, vec src2, kReg mask) %{
9036+
predicate(!n->as_ShiftV()->is_var_shift());
90369037
match(Set dst (LShiftVS (Binary dst src2) mask));
90379038
match(Set dst (LShiftVI (Binary dst src2) mask));
90389039
match(Set dst (LShiftVL (Binary dst src2) mask));
@@ -9041,9 +9042,24 @@ instruct vlshift_reg_masked(vec dst, vec src2, kReg mask) %{
90419042
int vlen_enc = vector_length_encoding(this);
90429043
BasicType bt = Matcher::vector_element_basic_type(this);
90439044
int opc = this->ideal_Opcode();
9044-
bool is_varshift = !VectorNode::is_vshift_cnt_opcode(in(2)->isa_Mach()->ideal_Opcode());
90459045
__ evmasked_op(opc, bt, $mask$$KRegister, $dst$$XMMRegister,
9046-
$dst$$XMMRegister, $src2$$XMMRegister, true, vlen_enc, is_varshift);
9046+
$dst$$XMMRegister, $src2$$XMMRegister, true, vlen_enc, false);
9047+
%}
9048+
ins_pipe( pipe_slow );
9049+
%}
9050+
9051+
instruct vlshiftv_reg_masked(vec dst, vec src2, kReg mask) %{
9052+
predicate(n->as_ShiftV()->is_var_shift());
9053+
match(Set dst (LShiftVS (Binary dst src2) mask));
9054+
match(Set dst (LShiftVI (Binary dst src2) mask));
9055+
match(Set dst (LShiftVL (Binary dst src2) mask));
9056+
format %{ "vplshiftv_masked $dst, $dst, $src2, $mask\t! lshift masked operation" %}
9057+
ins_encode %{
9058+
int vlen_enc = vector_length_encoding(this);
9059+
BasicType bt = Matcher::vector_element_basic_type(this);
9060+
int opc = this->ideal_Opcode();
9061+
__ evmasked_op(opc, bt, $mask$$KRegister, $dst$$XMMRegister,
9062+
$dst$$XMMRegister, $src2$$XMMRegister, true, vlen_enc, true);
90479063
%}
90489064
ins_pipe( pipe_slow );
90499065
%}
@@ -9079,6 +9095,7 @@ instruct vrshift_imm_masked(vec dst, immI8 shift, kReg mask) %{
90799095
%}
90809096

90819097
instruct vrshift_reg_masked(vec dst, vec src2, kReg mask) %{
9098+
predicate(!n->as_ShiftV()->is_var_shift());
90829099
match(Set dst (RShiftVS (Binary dst src2) mask));
90839100
match(Set dst (RShiftVI (Binary dst src2) mask));
90849101
match(Set dst (RShiftVL (Binary dst src2) mask));
@@ -9087,9 +9104,24 @@ instruct vrshift_reg_masked(vec dst, vec src2, kReg mask) %{
90879104
int vlen_enc = vector_length_encoding(this);
90889105
BasicType bt = Matcher::vector_element_basic_type(this);
90899106
int opc = this->ideal_Opcode();
9090-
bool is_varshift = !VectorNode::is_vshift_cnt_opcode(in(2)->isa_Mach()->ideal_Opcode());
90919107
__ evmasked_op(opc, bt, $mask$$KRegister, $dst$$XMMRegister,
9092-
$dst$$XMMRegister, $src2$$XMMRegister, true, vlen_enc, is_varshift);
9108+
$dst$$XMMRegister, $src2$$XMMRegister, true, vlen_enc, false);
9109+
%}
9110+
ins_pipe( pipe_slow );
9111+
%}
9112+
9113+
instruct vrshiftv_reg_masked(vec dst, vec src2, kReg mask) %{
9114+
predicate(n->as_ShiftV()->is_var_shift());
9115+
match(Set dst (RShiftVS (Binary dst src2) mask));
9116+
match(Set dst (RShiftVI (Binary dst src2) mask));
9117+
match(Set dst (RShiftVL (Binary dst src2) mask));
9118+
format %{ "vprshiftv_masked $dst, $dst, $src2, $mask\t! rshift masked operation" %}
9119+
ins_encode %{
9120+
int vlen_enc = vector_length_encoding(this);
9121+
BasicType bt = Matcher::vector_element_basic_type(this);
9122+
int opc = this->ideal_Opcode();
9123+
__ evmasked_op(opc, bt, $mask$$KRegister, $dst$$XMMRegister,
9124+
$dst$$XMMRegister, $src2$$XMMRegister, true, vlen_enc, true);
90939125
%}
90949126
ins_pipe( pipe_slow );
90959127
%}
@@ -9125,6 +9157,7 @@ instruct vurshift_imm_masked(vec dst, immI8 shift, kReg mask) %{
91259157
%}
91269158

91279159
instruct vurshift_reg_masked(vec dst, vec src2, kReg mask) %{
9160+
predicate(!n->as_ShiftV()->is_var_shift());
91289161
match(Set dst (URShiftVS (Binary dst src2) mask));
91299162
match(Set dst (URShiftVI (Binary dst src2) mask));
91309163
match(Set dst (URShiftVL (Binary dst src2) mask));
@@ -9133,9 +9166,24 @@ instruct vurshift_reg_masked(vec dst, vec src2, kReg mask) %{
91339166
int vlen_enc = vector_length_encoding(this);
91349167
BasicType bt = Matcher::vector_element_basic_type(this);
91359168
int opc = this->ideal_Opcode();
9136-
bool is_varshift = !VectorNode::is_vshift_cnt_opcode(in(2)->isa_Mach()->ideal_Opcode());
91379169
__ evmasked_op(opc, bt, $mask$$KRegister, $dst$$XMMRegister,
9138-
$dst$$XMMRegister, $src2$$XMMRegister, true, vlen_enc, is_varshift);
9170+
$dst$$XMMRegister, $src2$$XMMRegister, true, vlen_enc, false);
9171+
%}
9172+
ins_pipe( pipe_slow );
9173+
%}
9174+
9175+
instruct vurshiftv_reg_masked(vec dst, vec src2, kReg mask) %{
9176+
predicate(n->as_ShiftV()->is_var_shift());
9177+
match(Set dst (URShiftVS (Binary dst src2) mask));
9178+
match(Set dst (URShiftVI (Binary dst src2) mask));
9179+
match(Set dst (URShiftVL (Binary dst src2) mask));
9180+
format %{ "vpurshiftv_masked $dst, $dst, $src2, $mask\t! urshift masked operation" %}
9181+
ins_encode %{
9182+
int vlen_enc = vector_length_encoding(this);
9183+
BasicType bt = Matcher::vector_element_basic_type(this);
9184+
int opc = this->ideal_Opcode();
9185+
__ evmasked_op(opc, bt, $mask$$KRegister, $dst$$XMMRegister,
9186+
$dst$$XMMRegister, $src2$$XMMRegister, true, vlen_enc, true);
91399187
%}
91409188
ins_pipe( pipe_slow );
91419189
%}

‎src/hotspot/share/opto/node.hpp

Lines changed: 3 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -175,6 +175,7 @@ class VectorMaskCmpNode;
175175
class VectorUnboxNode;
176176
class VectorSet;
177177
class VectorReinterpretNode;
178+
class ShiftVNode;
178179

179180
// The type of all node counts and indexes.
180181
// It must hold at least 16 bits, but must also be fast to load and store.
@@ -711,6 +712,7 @@ class Node {
711712
DEFINE_CLASS_ID(VectorMaskCmp, Vector, 0)
712713
DEFINE_CLASS_ID(VectorUnbox, Vector, 1)
713714
DEFINE_CLASS_ID(VectorReinterpret, Vector, 2)
715+
DEFINE_CLASS_ID(ShiftV, Vector, 3)
714716

715717
DEFINE_CLASS_ID(Proj, Node, 3)
716718
DEFINE_CLASS_ID(CatchProj, Proj, 0)
@@ -945,6 +947,7 @@ class Node {
945947
DEFINE_CLASS_QUERY(LoadVectorGather)
946948
DEFINE_CLASS_QUERY(StoreVector)
947949
DEFINE_CLASS_QUERY(StoreVectorScatter)
950+
DEFINE_CLASS_QUERY(ShiftV)
948951
DEFINE_CLASS_QUERY(Unlock)
949952

950953
#undef DEFINE_CLASS_QUERY

‎src/hotspot/share/opto/vectorIntrinsics.cpp

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -526,7 +526,7 @@ bool LibraryCallKit::inline_vector_nary_operation(int n) {
526526
switch (n) {
527527
case 1:
528528
case 2: {
529-
operation = VectorNode::make(sopc, opd1, opd2, vt, is_vector_mask(vbox_klass));
529+
operation = VectorNode::make(sopc, opd1, opd2, vt, is_vector_mask(vbox_klass), VectorNode::is_shift_opcode(opc));
530530
break;
531531
}
532532
case 3: {

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