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8277239: SIGSEGV in vrshift_reg_maskedNode::emit
Reviewed-by: sviswanathan, dlong
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Jatin Bhateja committed Nov 22, 2021
1 parent 8683de5 commit e529865
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Showing 5 changed files with 130 additions and 61 deletions.
104 changes: 76 additions & 28 deletions src/hotspot/cpu/x86/x86.ad
Expand Up @@ -6196,7 +6196,7 @@ instruct vshiftcnt(vec dst, rRegI cnt) %{

// Byte vector shift
instruct vshiftB(vec dst, vec src, vec shift, vec tmp, rRegI scratch) %{
predicate(Matcher::vector_length(n) <= 8 && VectorNode::is_vshift_cnt(n->in(2)));
predicate(Matcher::vector_length(n) <= 8 && !n->as_ShiftV()->is_var_shift());
match(Set dst ( LShiftVB src shift));
match(Set dst ( RShiftVB src shift));
match(Set dst (URShiftVB src shift));
Expand All @@ -6216,7 +6216,7 @@ instruct vshiftB(vec dst, vec src, vec shift, vec tmp, rRegI scratch) %{
%}

instruct vshift16B(vec dst, vec src, vec shift, vec tmp1, vec tmp2, rRegI scratch) %{
predicate(Matcher::vector_length(n) == 16 && VectorNode::is_vshift_cnt(n->in(2)) &&
predicate(Matcher::vector_length(n) == 16 && !n->as_ShiftV()->is_var_shift() &&
UseAVX <= 1);
match(Set dst ( LShiftVB src shift));
match(Set dst ( RShiftVB src shift));
Expand All @@ -6241,7 +6241,7 @@ instruct vshift16B(vec dst, vec src, vec shift, vec tmp1, vec tmp2, rRegI scratc
%}

instruct vshift16B_avx(vec dst, vec src, vec shift, vec tmp, rRegI scratch) %{
predicate(Matcher::vector_length(n) == 16 && VectorNode::is_vshift_cnt(n->in(2)) &&
predicate(Matcher::vector_length(n) == 16 && !n->as_ShiftV()->is_var_shift() &&
UseAVX > 1);
match(Set dst ( LShiftVB src shift));
match(Set dst ( RShiftVB src shift));
Expand All @@ -6262,7 +6262,7 @@ instruct vshift16B_avx(vec dst, vec src, vec shift, vec tmp, rRegI scratch) %{
%}

instruct vshift32B_avx(vec dst, vec src, vec shift, vec tmp, rRegI scratch) %{
predicate(Matcher::vector_length(n) == 32 && VectorNode::is_vshift_cnt(n->in(2)));
predicate(Matcher::vector_length(n) == 32 && !n->as_ShiftV()->is_var_shift());
match(Set dst ( LShiftVB src shift));
match(Set dst ( RShiftVB src shift));
match(Set dst (URShiftVB src shift));
Expand All @@ -6287,7 +6287,7 @@ instruct vshift32B_avx(vec dst, vec src, vec shift, vec tmp, rRegI scratch) %{
%}

instruct vshift64B_avx(vec dst, vec src, vec shift, vec tmp1, vec tmp2, rRegI scratch) %{
predicate(Matcher::vector_length(n) == 64 && VectorNode::is_vshift_cnt(n->in(2)));
predicate(Matcher::vector_length(n) == 64 && !n->as_ShiftV()->is_var_shift());
match(Set dst ( LShiftVB src shift));
match(Set dst (RShiftVB src shift));
match(Set dst (URShiftVB src shift));
Expand Down Expand Up @@ -6320,7 +6320,7 @@ instruct vshift64B_avx(vec dst, vec src, vec shift, vec tmp1, vec tmp2, rRegI sc
// unsigned values.
// Shorts/Chars vector left shift
instruct vshiftS(vec dst, vec src, vec shift) %{
predicate(VectorNode::is_vshift_cnt(n->in(2)));
predicate(!n->as_ShiftV()->is_var_shift());
match(Set dst ( LShiftVS src shift));
match(Set dst ( RShiftVS src shift));
match(Set dst (URShiftVS src shift));
Expand Down Expand Up @@ -6351,7 +6351,7 @@ instruct vshiftS(vec dst, vec src, vec shift) %{

// Integers vector left shift
instruct vshiftI(vec dst, vec src, vec shift) %{
predicate(VectorNode::is_vshift_cnt(n->in(2)));
predicate(!n->as_ShiftV()->is_var_shift());
match(Set dst ( LShiftVI src shift));
match(Set dst ( RShiftVI src shift));
match(Set dst (URShiftVI src shift));
Expand Down Expand Up @@ -6405,7 +6405,7 @@ instruct vshiftI_imm(vec dst, vec src, immI8 shift) %{

// Longs vector shift
instruct vshiftL(vec dst, vec src, vec shift) %{
predicate(VectorNode::is_vshift_cnt(n->in(2)));
predicate(!n->as_ShiftV()->is_var_shift());
match(Set dst ( LShiftVL src shift));
match(Set dst (URShiftVL src shift));
effect(TEMP dst, USE src, USE shift);
Expand Down Expand Up @@ -6446,7 +6446,7 @@ instruct vshiftL_imm(vec dst, vec src, immI8 shift) %{
// -------------------ArithmeticRightShift -----------------------------------
// Long vector arithmetic right shift
instruct vshiftL_arith_reg(vec dst, vec src, vec shift, vec tmp, rRegI scratch) %{
predicate(VectorNode::is_vshift_cnt(n->in(2)) && UseAVX <= 2);
predicate(!n->as_ShiftV()->is_var_shift() && UseAVX <= 2);
match(Set dst (RShiftVL src shift));
effect(TEMP dst, TEMP tmp, TEMP scratch);
format %{ "vshiftq $dst,$src,$shift" %}
Expand Down Expand Up @@ -6475,7 +6475,7 @@ instruct vshiftL_arith_reg(vec dst, vec src, vec shift, vec tmp, rRegI scratch)
%}

instruct vshiftL_arith_reg_evex(vec dst, vec src, vec shift) %{
predicate(VectorNode::is_vshift_cnt(n->in(2)) && UseAVX > 2);
predicate(!n->as_ShiftV()->is_var_shift() && UseAVX > 2);
match(Set dst (RShiftVL src shift));
format %{ "vshiftq $dst,$src,$shift" %}
ins_encode %{
Expand All @@ -6489,7 +6489,7 @@ instruct vshiftL_arith_reg_evex(vec dst, vec src, vec shift) %{
// Byte variable shift
instruct vshift8B_var_nobw(vec dst, vec src, vec shift, vec vtmp, rRegP scratch) %{
predicate(Matcher::vector_length(n) <= 8 &&
!VectorNode::is_vshift_cnt(n->in(2)) &&
n->as_ShiftV()->is_var_shift() &&
!VM_Version::supports_avx512bw());
match(Set dst ( LShiftVB src shift));
match(Set dst ( RShiftVB src shift));
Expand All @@ -6509,7 +6509,7 @@ instruct vshift8B_var_nobw(vec dst, vec src, vec shift, vec vtmp, rRegP scratch)

instruct vshift16B_var_nobw(vec dst, vec src, vec shift, vec vtmp1, vec vtmp2, rRegP scratch) %{
predicate(Matcher::vector_length(n) == 16 &&
!VectorNode::is_vshift_cnt(n->in(2)) &&
n->as_ShiftV()->is_var_shift() &&
!VM_Version::supports_avx512bw());
match(Set dst ( LShiftVB src shift));
match(Set dst ( RShiftVB src shift));
Expand Down Expand Up @@ -6537,7 +6537,7 @@ instruct vshift16B_var_nobw(vec dst, vec src, vec shift, vec vtmp1, vec vtmp2, r

instruct vshift32B_var_nobw(vec dst, vec src, vec shift, vec vtmp1, vec vtmp2, vec vtmp3, vec vtmp4, rRegP scratch) %{
predicate(Matcher::vector_length(n) == 32 &&
!VectorNode::is_vshift_cnt(n->in(2)) &&
n->as_ShiftV()->is_var_shift() &&
!VM_Version::supports_avx512bw());
match(Set dst ( LShiftVB src shift));
match(Set dst ( RShiftVB src shift));
Expand Down Expand Up @@ -6573,7 +6573,7 @@ instruct vshift32B_var_nobw(vec dst, vec src, vec shift, vec vtmp1, vec vtmp2, v

instruct vshiftB_var_evex_bw(vec dst, vec src, vec shift, vec vtmp, rRegP scratch) %{
predicate(Matcher::vector_length(n) <= 32 &&
!VectorNode::is_vshift_cnt(n->in(2)) &&
n->as_ShiftV()->is_var_shift() &&
VM_Version::supports_avx512bw());
match(Set dst ( LShiftVB src shift));
match(Set dst ( RShiftVB src shift));
Expand All @@ -6592,7 +6592,7 @@ instruct vshiftB_var_evex_bw(vec dst, vec src, vec shift, vec vtmp, rRegP scratc

instruct vshift64B_var_evex_bw(vec dst, vec src, vec shift, vec vtmp1, vec vtmp2, rRegP scratch) %{
predicate(Matcher::vector_length(n) == 64 &&
!VectorNode::is_vshift_cnt(n->in(2)) &&
n->as_ShiftV()->is_var_shift() &&
VM_Version::supports_avx512bw());
match(Set dst ( LShiftVB src shift));
match(Set dst ( RShiftVB src shift));
Expand All @@ -6616,7 +6616,7 @@ instruct vshift64B_var_evex_bw(vec dst, vec src, vec shift, vec vtmp1, vec vtmp2
// Short variable shift
instruct vshift8S_var_nobw(vec dst, vec src, vec shift, vec vtmp, rRegP scratch) %{
predicate(Matcher::vector_length(n) <= 8 &&
!VectorNode::is_vshift_cnt(n->in(2)) &&
n->as_ShiftV()->is_var_shift() &&
!VM_Version::supports_avx512bw());
match(Set dst ( LShiftVS src shift));
match(Set dst ( RShiftVS src shift));
Expand All @@ -6641,7 +6641,7 @@ instruct vshift8S_var_nobw(vec dst, vec src, vec shift, vec vtmp, rRegP scratch)

instruct vshift16S_var_nobw(vec dst, vec src, vec shift, vec vtmp1, vec vtmp2, rRegP scratch) %{
predicate(Matcher::vector_length(n) == 16 &&
!VectorNode::is_vshift_cnt(n->in(2)) &&
n->as_ShiftV()->is_var_shift() &&
!VM_Version::supports_avx512bw());
match(Set dst ( LShiftVS src shift));
match(Set dst ( RShiftVS src shift));
Expand Down Expand Up @@ -6676,7 +6676,7 @@ instruct vshift16S_var_nobw(vec dst, vec src, vec shift, vec vtmp1, vec vtmp2, r
%}

instruct vshift16S_var_evex_bw(vec dst, vec src, vec shift) %{
predicate(!VectorNode::is_vshift_cnt(n->in(2)) &&
predicate(n->as_ShiftV()->is_var_shift() &&
VM_Version::supports_avx512bw());
match(Set dst ( LShiftVS src shift));
match(Set dst ( RShiftVS src shift));
Expand All @@ -6697,7 +6697,7 @@ instruct vshift16S_var_evex_bw(vec dst, vec src, vec shift) %{

//Integer variable shift
instruct vshiftI_var(vec dst, vec src, vec shift) %{
predicate(!VectorNode::is_vshift_cnt(n->in(2)));
predicate(n->as_ShiftV()->is_var_shift());
match(Set dst ( LShiftVI src shift));
match(Set dst ( RShiftVI src shift));
match(Set dst (URShiftVI src shift));
Expand All @@ -6714,7 +6714,7 @@ instruct vshiftI_var(vec dst, vec src, vec shift) %{

//Long variable shift
instruct vshiftL_var(vec dst, vec src, vec shift) %{
predicate(!VectorNode::is_vshift_cnt(n->in(2)));
predicate(n->as_ShiftV()->is_var_shift());
match(Set dst ( LShiftVL src shift));
match(Set dst (URShiftVL src shift));
format %{ "vector_varshift_long $dst,$src,$shift\t!" %}
Expand All @@ -6731,7 +6731,7 @@ instruct vshiftL_var(vec dst, vec src, vec shift) %{
//Long variable right shift arithmetic
instruct vshiftL_arith_var(vec dst, vec src, vec shift, vec vtmp) %{
predicate(Matcher::vector_length(n) <= 4 &&
!VectorNode::is_vshift_cnt(n->in(2)) &&
n->as_ShiftV()->is_var_shift() &&
UseAVX == 2);
match(Set dst (RShiftVL src shift));
effect(TEMP dst, TEMP vtmp);
Expand All @@ -6746,7 +6746,7 @@ instruct vshiftL_arith_var(vec dst, vec src, vec shift, vec vtmp) %{
%}

instruct vshiftL_arith_var_evex(vec dst, vec src, vec shift) %{
predicate(!VectorNode::is_vshift_cnt(n->in(2)) &&
predicate(n->as_ShiftV()->is_var_shift() &&
UseAVX > 2);
match(Set dst (RShiftVL src shift));
format %{ "vector_varfshift_long $dst,$src,$shift\t!" %}
Expand Down Expand Up @@ -9033,6 +9033,7 @@ instruct vlshift_imm_masked(vec dst, immI8 shift, kReg mask) %{
%}

instruct vlshift_reg_masked(vec dst, vec src2, kReg mask) %{
predicate(!n->as_ShiftV()->is_var_shift());
match(Set dst (LShiftVS (Binary dst src2) mask));
match(Set dst (LShiftVI (Binary dst src2) mask));
match(Set dst (LShiftVL (Binary dst src2) mask));
Expand All @@ -9041,9 +9042,24 @@ instruct vlshift_reg_masked(vec dst, vec src2, kReg mask) %{
int vlen_enc = vector_length_encoding(this);
BasicType bt = Matcher::vector_element_basic_type(this);
int opc = this->ideal_Opcode();
bool is_varshift = !VectorNode::is_vshift_cnt_opcode(in(2)->isa_Mach()->ideal_Opcode());
__ evmasked_op(opc, bt, $mask$$KRegister, $dst$$XMMRegister,
$dst$$XMMRegister, $src2$$XMMRegister, true, vlen_enc, is_varshift);
$dst$$XMMRegister, $src2$$XMMRegister, true, vlen_enc, false);
%}
ins_pipe( pipe_slow );
%}

instruct vlshiftv_reg_masked(vec dst, vec src2, kReg mask) %{
predicate(n->as_ShiftV()->is_var_shift());
match(Set dst (LShiftVS (Binary dst src2) mask));
match(Set dst (LShiftVI (Binary dst src2) mask));
match(Set dst (LShiftVL (Binary dst src2) mask));
format %{ "vplshiftv_masked $dst, $dst, $src2, $mask\t! lshift masked operation" %}
ins_encode %{
int vlen_enc = vector_length_encoding(this);
BasicType bt = Matcher::vector_element_basic_type(this);
int opc = this->ideal_Opcode();
__ evmasked_op(opc, bt, $mask$$KRegister, $dst$$XMMRegister,
$dst$$XMMRegister, $src2$$XMMRegister, true, vlen_enc, true);
%}
ins_pipe( pipe_slow );
%}
Expand Down Expand Up @@ -9079,6 +9095,7 @@ instruct vrshift_imm_masked(vec dst, immI8 shift, kReg mask) %{
%}

instruct vrshift_reg_masked(vec dst, vec src2, kReg mask) %{
predicate(!n->as_ShiftV()->is_var_shift());
match(Set dst (RShiftVS (Binary dst src2) mask));
match(Set dst (RShiftVI (Binary dst src2) mask));
match(Set dst (RShiftVL (Binary dst src2) mask));
Expand All @@ -9087,9 +9104,24 @@ instruct vrshift_reg_masked(vec dst, vec src2, kReg mask) %{
int vlen_enc = vector_length_encoding(this);
BasicType bt = Matcher::vector_element_basic_type(this);
int opc = this->ideal_Opcode();
bool is_varshift = !VectorNode::is_vshift_cnt_opcode(in(2)->isa_Mach()->ideal_Opcode());
__ evmasked_op(opc, bt, $mask$$KRegister, $dst$$XMMRegister,
$dst$$XMMRegister, $src2$$XMMRegister, true, vlen_enc, is_varshift);
$dst$$XMMRegister, $src2$$XMMRegister, true, vlen_enc, false);
%}
ins_pipe( pipe_slow );
%}

instruct vrshiftv_reg_masked(vec dst, vec src2, kReg mask) %{
predicate(n->as_ShiftV()->is_var_shift());
match(Set dst (RShiftVS (Binary dst src2) mask));
match(Set dst (RShiftVI (Binary dst src2) mask));
match(Set dst (RShiftVL (Binary dst src2) mask));
format %{ "vprshiftv_masked $dst, $dst, $src2, $mask\t! rshift masked operation" %}
ins_encode %{
int vlen_enc = vector_length_encoding(this);
BasicType bt = Matcher::vector_element_basic_type(this);
int opc = this->ideal_Opcode();
__ evmasked_op(opc, bt, $mask$$KRegister, $dst$$XMMRegister,
$dst$$XMMRegister, $src2$$XMMRegister, true, vlen_enc, true);
%}
ins_pipe( pipe_slow );
%}
Expand Down Expand Up @@ -9125,6 +9157,7 @@ instruct vurshift_imm_masked(vec dst, immI8 shift, kReg mask) %{
%}

instruct vurshift_reg_masked(vec dst, vec src2, kReg mask) %{
predicate(!n->as_ShiftV()->is_var_shift());
match(Set dst (URShiftVS (Binary dst src2) mask));
match(Set dst (URShiftVI (Binary dst src2) mask));
match(Set dst (URShiftVL (Binary dst src2) mask));
Expand All @@ -9133,9 +9166,24 @@ instruct vurshift_reg_masked(vec dst, vec src2, kReg mask) %{
int vlen_enc = vector_length_encoding(this);
BasicType bt = Matcher::vector_element_basic_type(this);
int opc = this->ideal_Opcode();
bool is_varshift = !VectorNode::is_vshift_cnt_opcode(in(2)->isa_Mach()->ideal_Opcode());
__ evmasked_op(opc, bt, $mask$$KRegister, $dst$$XMMRegister,
$dst$$XMMRegister, $src2$$XMMRegister, true, vlen_enc, is_varshift);
$dst$$XMMRegister, $src2$$XMMRegister, true, vlen_enc, false);
%}
ins_pipe( pipe_slow );
%}

instruct vurshiftv_reg_masked(vec dst, vec src2, kReg mask) %{
predicate(n->as_ShiftV()->is_var_shift());
match(Set dst (URShiftVS (Binary dst src2) mask));
match(Set dst (URShiftVI (Binary dst src2) mask));
match(Set dst (URShiftVL (Binary dst src2) mask));
format %{ "vpurshiftv_masked $dst, $dst, $src2, $mask\t! urshift masked operation" %}
ins_encode %{
int vlen_enc = vector_length_encoding(this);
BasicType bt = Matcher::vector_element_basic_type(this);
int opc = this->ideal_Opcode();
__ evmasked_op(opc, bt, $mask$$KRegister, $dst$$XMMRegister,
$dst$$XMMRegister, $src2$$XMMRegister, true, vlen_enc, true);
%}
ins_pipe( pipe_slow );
%}
Expand Down
3 changes: 3 additions & 0 deletions src/hotspot/share/opto/node.hpp
Expand Up @@ -175,6 +175,7 @@ class VectorMaskCmpNode;
class VectorUnboxNode;
class VectorSet;
class VectorReinterpretNode;
class ShiftVNode;

// The type of all node counts and indexes.
// It must hold at least 16 bits, but must also be fast to load and store.
Expand Down Expand Up @@ -711,6 +712,7 @@ class Node {
DEFINE_CLASS_ID(VectorMaskCmp, Vector, 0)
DEFINE_CLASS_ID(VectorUnbox, Vector, 1)
DEFINE_CLASS_ID(VectorReinterpret, Vector, 2)
DEFINE_CLASS_ID(ShiftV, Vector, 3)

DEFINE_CLASS_ID(Proj, Node, 3)
DEFINE_CLASS_ID(CatchProj, Proj, 0)
Expand Down Expand Up @@ -945,6 +947,7 @@ class Node {
DEFINE_CLASS_QUERY(LoadVectorGather)
DEFINE_CLASS_QUERY(StoreVector)
DEFINE_CLASS_QUERY(StoreVectorScatter)
DEFINE_CLASS_QUERY(ShiftV)
DEFINE_CLASS_QUERY(Unlock)

#undef DEFINE_CLASS_QUERY
Expand Down
2 changes: 1 addition & 1 deletion src/hotspot/share/opto/vectorIntrinsics.cpp
Expand Up @@ -526,7 +526,7 @@ bool LibraryCallKit::inline_vector_nary_operation(int n) {
switch (n) {
case 1:
case 2: {
operation = VectorNode::make(sopc, opd1, opd2, vt, is_vector_mask(vbox_klass));
operation = VectorNode::make(sopc, opd1, opd2, vt, is_vector_mask(vbox_klass), VectorNode::is_shift_opcode(opc));
break;
}
case 3: {
Expand Down

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