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zifeihanRealFYang
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8333964: RISC-V: C2: Check "requires_strict_order" flag for floating-point add reduction
Reviewed-by: fyang
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‎src/hotspot/cpu/riscv/riscv_v.ad

Lines changed: 46 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -2007,11 +2007,20 @@ instruct reduce_addL(iRegLNoSp dst, iRegL src1, vReg src2, vReg tmp) %{
20072007
ins_pipe(pipe_slow);
20082008
%}
20092009

2010-
instruct reduce_addF(fRegF dst, fRegF src1, vReg src2, vReg tmp) %{
2010+
// Distinguish two cases based on requires_strict_order
2011+
// 1. Non strictly-ordered AddReductionVF/D. For example, AddReductionVF/D
2012+
// generated by Vector API. It is more beneficial performance-wise to do
2013+
// an unordered FP reduction sum (vfredusum.vs).
2014+
// 2. Strictly-ordered AddReductionVF/D. For example, AddReductionVF/D
2015+
// generated by auto-vectorization. Must do an ordered FP reduction sum
2016+
// (vfredosum.vs).
2017+
2018+
instruct reduce_addF_ordered(fRegF dst, fRegF src1, vReg src2, vReg tmp) %{
2019+
predicate(n->as_Reduction()->requires_strict_order());
20112020
match(Set dst (AddReductionVF src1 src2));
20122021
effect(TEMP tmp);
20132022
ins_cost(VEC_COST);
2014-
format %{ "reduce_addF $dst, $src1, $src2\t# KILL $tmp" %}
2023+
format %{ "reduce_addF_ordered $dst, $src1, $src2\t# KILL $tmp" %}
20152024
ins_encode %{
20162025
__ vsetvli_helper(T_FLOAT, Matcher::vector_length(this, $src2));
20172026
__ vfmv_s_f(as_VectorRegister($tmp$$reg), $src1$$FloatRegister);
@@ -2022,11 +2031,28 @@ instruct reduce_addF(fRegF dst, fRegF src1, vReg src2, vReg tmp) %{
20222031
ins_pipe(pipe_slow);
20232032
%}
20242033

2025-
instruct reduce_addD(fRegD dst, fRegD src1, vReg src2, vReg tmp) %{
2034+
instruct reduce_addF_unordered(fRegF dst, fRegF src1, vReg src2, vReg tmp) %{
2035+
predicate(!n->as_Reduction()->requires_strict_order());
2036+
match(Set dst (AddReductionVF src1 src2));
2037+
effect(TEMP tmp);
2038+
ins_cost(VEC_COST);
2039+
format %{ "reduce_addF_unordered $dst, $src1, $src2\t# KILL $tmp" %}
2040+
ins_encode %{
2041+
__ vsetvli_helper(T_FLOAT, Matcher::vector_length(this, $src2));
2042+
__ vfmv_s_f(as_VectorRegister($tmp$$reg), $src1$$FloatRegister);
2043+
__ vfredusum_vs(as_VectorRegister($tmp$$reg), as_VectorRegister($src2$$reg),
2044+
as_VectorRegister($tmp$$reg));
2045+
__ vfmv_f_s($dst$$FloatRegister, as_VectorRegister($tmp$$reg));
2046+
%}
2047+
ins_pipe(pipe_slow);
2048+
%}
2049+
2050+
instruct reduce_addD_ordered(fRegD dst, fRegD src1, vReg src2, vReg tmp) %{
2051+
predicate(n->as_Reduction()->requires_strict_order());
20262052
match(Set dst (AddReductionVD src1 src2));
20272053
effect(TEMP tmp);
20282054
ins_cost(VEC_COST);
2029-
format %{ "reduce_addD $dst, $src1, $src2\t# KILL $tmp" %}
2055+
format %{ "reduce_addD_ordered $dst, $src1, $src2\t# KILL $tmp" %}
20302056
ins_encode %{
20312057
__ vsetvli_helper(T_DOUBLE, Matcher::vector_length(this, $src2));
20322058
__ vfmv_s_f(as_VectorRegister($tmp$$reg), $src1$$FloatRegister);
@@ -2037,6 +2063,22 @@ instruct reduce_addD(fRegD dst, fRegD src1, vReg src2, vReg tmp) %{
20372063
ins_pipe(pipe_slow);
20382064
%}
20392065

2066+
instruct reduce_addD_unordered(fRegD dst, fRegD src1, vReg src2, vReg tmp) %{
2067+
predicate(!n->as_Reduction()->requires_strict_order());
2068+
match(Set dst (AddReductionVD src1 src2));
2069+
effect(TEMP tmp);
2070+
ins_cost(VEC_COST);
2071+
format %{ "reduce_addD_unordered $dst, $src1, $src2\t# KILL $tmp" %}
2072+
ins_encode %{
2073+
__ vsetvli_helper(T_DOUBLE, Matcher::vector_length(this, $src2));
2074+
__ vfmv_s_f(as_VectorRegister($tmp$$reg), $src1$$FloatRegister);
2075+
__ vfredusum_vs(as_VectorRegister($tmp$$reg), as_VectorRegister($src2$$reg),
2076+
as_VectorRegister($tmp$$reg));
2077+
__ vfmv_f_s($dst$$FloatRegister, as_VectorRegister($tmp$$reg));
2078+
%}
2079+
ins_pipe(pipe_slow);
2080+
%}
2081+
20402082
// vector add reduction - predicated
20412083

20422084
instruct reduce_addI_masked(iRegINoSp dst, iRegIorL2I src1, vReg src2, vRegMask_V0 v0, vReg tmp) %{

‎test/hotspot/jtreg/compiler/loopopts/superword/TestVectorFPReduction.java

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -54,7 +54,7 @@ public static void main(String[] args) {
5454
applyIfCPUFeatureAnd = {"asimd", "true", "sve", "false"})
5555
@IR(counts = {"requires_strict_order", ">=1", IRNode.ADD_REDUCTION_VF, ">=1"},
5656
failOn = {"no_strict_order"},
57-
applyIfCPUFeatureOr = {"sve", "true", "sse2", "true"},
57+
applyIfCPUFeatureOr = {"sve", "true", "sse2", "true", "rvv", "true"},
5858
phase = CompilePhase.PRINT_IDEAL)
5959
private static void testAddReductionVF() {
6060
float result = 1;
@@ -69,7 +69,7 @@ private static void testAddReductionVF() {
6969
applyIfCPUFeatureAnd = {"asimd", "true", "sve", "false"})
7070
@IR(counts = {"requires_strict_order", ">=1", IRNode.ADD_REDUCTION_VD, ">=1"},
7171
failOn = {"no_strict_order"},
72-
applyIfCPUFeatureOr = {"sve", "true", "sse2", "true"},
72+
applyIfCPUFeatureOr = {"sve", "true", "sse2", "true", "rvv", "true"},
7373
phase = CompilePhase.PRINT_IDEAL)
7474
private static void testAddReductionVD() {
7575
double result = 1;

‎test/hotspot/jtreg/compiler/vectorapi/TestVectorAddMulReduction.java

Lines changed: 7 additions & 7 deletions
Original file line numberDiff line numberDiff line change
@@ -78,7 +78,7 @@ public static void testFloatAddKernel(VectorSpecies SPECIES, float[] f) {
7878
@Test
7979
@IR(counts = {IRNode.ADD_REDUCTION_VF, ">=1", "no_strict_order", ">=1"},
8080
failOn = {"requires_strict_order"},
81-
applyIfCPUFeatureOr = {"asimd", "true", "sse2", "true"},
81+
applyIfCPUFeatureOr = {"asimd", "true", "sse2", "true", "rvv", "true"},
8282
applyIf = {"MaxVectorSize", ">=8"},
8383
phase = CompilePhase.PRINT_IDEAL)
8484
public static void testFloatAdd_64() {
@@ -88,7 +88,7 @@ public static void testFloatAdd_64() {
8888
@Test
8989
@IR(counts = {IRNode.ADD_REDUCTION_VF, ">=1", "no_strict_order", ">=1"},
9090
failOn = {"requires_strict_order"},
91-
applyIfCPUFeatureOr = {"asimd", "true", "sse2", "true"},
91+
applyIfCPUFeatureOr = {"asimd", "true", "sse2", "true", "rvv", "true"},
9292
applyIf = {"MaxVectorSize", ">=16"},
9393
phase = CompilePhase.PRINT_IDEAL)
9494
public static void testFloatAdd_128() {
@@ -98,7 +98,7 @@ public static void testFloatAdd_128() {
9898
@Test
9999
@IR(counts = {IRNode.ADD_REDUCTION_VF, ">=1", "no_strict_order", ">=1"},
100100
failOn = {"requires_strict_order"},
101-
applyIfCPUFeatureOr = {"asimd", "true", "sse2", "true"},
101+
applyIfCPUFeatureOr = {"asimd", "true", "sse2", "true", "rvv", "true"},
102102
applyIf = {"MaxVectorSize", ">=32"},
103103
phase = CompilePhase.PRINT_IDEAL)
104104
public static void testFloatAdd_256() {
@@ -108,7 +108,7 @@ public static void testFloatAdd_256() {
108108
@Test
109109
@IR(counts = {IRNode.ADD_REDUCTION_VF, ">=1", "no_strict_order", ">=1"},
110110
failOn = {"requires_strict_order"},
111-
applyIfCPUFeatureOr = {"asimd", "true", "sse2", "true"},
111+
applyIfCPUFeatureOr = {"asimd", "true", "sse2", "true", "rvv", "true"},
112112
applyIf = {"MaxVectorSize", ">=64"},
113113
phase = CompilePhase.PRINT_IDEAL)
114114
public static void testFloatAdd_512() {
@@ -127,7 +127,7 @@ public static void testDoubleAddKernel(VectorSpecies SPECIES, double[] d) {
127127
@Test
128128
@IR(counts = {IRNode.ADD_REDUCTION_VD, ">=1", "no_strict_order", ">=1"},
129129
failOn = {"requires_strict_order"},
130-
applyIfCPUFeatureOr = {"asimd", "true", "sse2", "true"},
130+
applyIfCPUFeatureOr = {"asimd", "true", "sse2", "true", "rvv", "true"},
131131
applyIf = {"MaxVectorSize", ">=16"},
132132
phase = CompilePhase.PRINT_IDEAL)
133133
public static void testDoubleAdd_128() {
@@ -137,7 +137,7 @@ public static void testDoubleAdd_128() {
137137
@Test
138138
@IR(counts = {IRNode.ADD_REDUCTION_VD, ">=1", "no_strict_order", ">=1"},
139139
failOn = {"requires_strict_order"},
140-
applyIfCPUFeatureOr = {"asimd", "true", "sse2", "true"},
140+
applyIfCPUFeatureOr = {"asimd", "true", "sse2", "true", "rvv", "true"},
141141
applyIf = {"MaxVectorSize", ">=32"},
142142
phase = CompilePhase.PRINT_IDEAL)
143143
public static void testDoubleAdd_256() {
@@ -147,7 +147,7 @@ public static void testDoubleAdd_256() {
147147
@Test
148148
@IR(counts = {IRNode.ADD_REDUCTION_VD, ">=1", "no_strict_order", ">=1"},
149149
failOn = {"requires_strict_order"},
150-
applyIfCPUFeatureOr = {"asimd", "true", "sse2", "true"},
150+
applyIfCPUFeatureOr = {"asimd", "true", "sse2", "true", "rvv", "true"},
151151
applyIf = {"MaxVectorSize", ">=64"},
152152
phase = CompilePhase.PRINT_IDEAL)
153153
public static void testDoubleAdd_512() {

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