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Hao SunNingsheng Jian
Hao Sun
authored and
Ningsheng Jian
committed
8290169: adlc: Improve child constraints for vector unary operations
Reviewed-by: eliu, xgong, sviswanathan
1 parent 2057070 commit eeb625e

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5 files changed

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‎src/hotspot/cpu/aarch64/aarch64_vector.ad

+19-59
Original file line numberDiff line numberDiff line change
@@ -1496,7 +1496,6 @@ instruct vand_notL_masked(vReg dst_src1, vReg src2, immL_M1 m1, pRegGov pg) %{
14961496
// vector abs
14971497

14981498
instruct vabsB(vReg dst, vReg src) %{
1499-
predicate(!n->as_Vector()->is_predicated_vector());
15001499
match(Set dst (AbsVB src));
15011500
format %{ "vabsB $dst, $src" %}
15021501
ins_encode %{
@@ -1512,7 +1511,6 @@ instruct vabsB(vReg dst, vReg src) %{
15121511
%}
15131512

15141513
instruct vabsS(vReg dst, vReg src) %{
1515-
predicate(!n->as_Vector()->is_predicated_vector());
15161514
match(Set dst (AbsVS src));
15171515
format %{ "vabsS $dst, $src" %}
15181516
ins_encode %{
@@ -1528,7 +1526,6 @@ instruct vabsS(vReg dst, vReg src) %{
15281526
%}
15291527

15301528
instruct vabsI(vReg dst, vReg src) %{
1531-
predicate(!n->as_Vector()->is_predicated_vector());
15321529
match(Set dst (AbsVI src));
15331530
format %{ "vabsI $dst, $src" %}
15341531
ins_encode %{
@@ -1544,7 +1541,6 @@ instruct vabsI(vReg dst, vReg src) %{
15441541
%}
15451542

15461543
instruct vabsL(vReg dst, vReg src) %{
1547-
predicate(!n->as_Vector()->is_predicated_vector());
15481544
match(Set dst (AbsVL src));
15491545
format %{ "vabsL $dst, $src" %}
15501546
ins_encode %{
@@ -1560,7 +1556,6 @@ instruct vabsL(vReg dst, vReg src) %{
15601556
%}
15611557

15621558
instruct vabsF(vReg dst, vReg src) %{
1563-
predicate(!n->as_Vector()->is_predicated_vector());
15641559
match(Set dst (AbsVF src));
15651560
format %{ "vabsF $dst, $src" %}
15661561
ins_encode %{
@@ -1576,7 +1571,6 @@ instruct vabsF(vReg dst, vReg src) %{
15761571
%}
15771572

15781573
instruct vabsD(vReg dst, vReg src) %{
1579-
predicate(!n->as_Vector()->is_predicated_vector());
15801574
match(Set dst (AbsVD src));
15811575
format %{ "vabsD $dst, $src" %}
15821576
ins_encode %{
@@ -1658,8 +1652,7 @@ instruct vabsD_masked(vReg dst_src, pRegGov pg) %{
16581652
// vector fabs diff
16591653

16601654
instruct vfabd_neon(vReg dst, vReg src1, vReg src2) %{
1661-
predicate(VM_Version::use_neon_for_vector(Matcher::vector_length_in_bytes(n)) &&
1662-
!n->as_Vector()->is_predicated_vector());
1655+
predicate(VM_Version::use_neon_for_vector(Matcher::vector_length_in_bytes(n)));
16631656
match(Set dst (AbsVF (SubVF src1 src2)));
16641657
match(Set dst (AbsVD (SubVD src1 src2)));
16651658
format %{ "vfabd_neon $dst, $src1, $src2" %}
@@ -1671,8 +1664,7 @@ instruct vfabd_neon(vReg dst, vReg src1, vReg src2) %{
16711664
%}
16721665

16731666
instruct vfabd_sve(vReg dst_src1, vReg src2) %{
1674-
predicate(!VM_Version::use_neon_for_vector(Matcher::vector_length_in_bytes(n)) &&
1675-
!n->as_Vector()->is_predicated_vector());
1667+
predicate(!VM_Version::use_neon_for_vector(Matcher::vector_length_in_bytes(n)));
16761668
match(Set dst_src1 (AbsVF (SubVF dst_src1 src2)));
16771669
match(Set dst_src1 (AbsVD (SubVD dst_src1 src2)));
16781670
format %{ "vfabd_sve $dst_src1, $dst_src1, $src2" %}
@@ -1705,7 +1697,6 @@ instruct vfabd_masked(vReg dst_src1, vReg src2, pRegGov pg) %{
17051697
// vector neg
17061698

17071699
instruct vnegI(vReg dst, vReg src) %{
1708-
predicate(!n->as_Vector()->is_predicated_vector());
17091700
match(Set dst (NegVI src));
17101701
format %{ "vnegI $dst, $src" %}
17111702
ins_encode %{
@@ -1723,7 +1714,6 @@ instruct vnegI(vReg dst, vReg src) %{
17231714
%}
17241715

17251716
instruct vnegL(vReg dst, vReg src) %{
1726-
predicate(!n->as_Vector()->is_predicated_vector());
17271717
match(Set dst (NegVL src));
17281718
format %{ "vnegL $dst, $src" %}
17291719
ins_encode %{
@@ -1739,7 +1729,6 @@ instruct vnegL(vReg dst, vReg src) %{
17391729
%}
17401730

17411731
instruct vnegF(vReg dst, vReg src) %{
1742-
predicate(!n->as_Vector()->is_predicated_vector());
17431732
match(Set dst (NegVF src));
17441733
format %{ "vnegF $dst, $src" %}
17451734
ins_encode %{
@@ -1755,7 +1744,6 @@ instruct vnegF(vReg dst, vReg src) %{
17551744
%}
17561745

17571746
instruct vnegD(vReg dst, vReg src) %{
1758-
predicate(!n->as_Vector()->is_predicated_vector());
17591747
match(Set dst (NegVD src));
17601748
format %{ "vnegD $dst, $src" %}
17611749
ins_encode %{
@@ -1819,7 +1807,6 @@ instruct vnegD_masked(vReg dst_src, pRegGov pg) %{
18191807
// vector sqrt
18201808

18211809
instruct vsqrtF(vReg dst, vReg src) %{
1822-
predicate(!n->as_Vector()->is_predicated_vector());
18231810
match(Set dst (SqrtVF src));
18241811
format %{ "vsqrtF $dst, $src" %}
18251812
ins_encode %{
@@ -1835,7 +1822,6 @@ instruct vsqrtF(vReg dst, vReg src) %{
18351822
%}
18361823

18371824
instruct vsqrtD(vReg dst, vReg src) %{
1838-
predicate(!n->as_Vector()->is_predicated_vector());
18391825
match(Set dst (SqrtVD src));
18401826
format %{ "vsqrtD $dst, $src" %}
18411827
ins_encode %{
@@ -2190,9 +2176,8 @@ instruct vmls_masked(vReg dst_src1, vReg src2, vReg src3, pRegGov pg) %{
21902176
// vector fmls
21912177

21922178
// dst_src1 = dst_src1 + -src2 * src3
2193-
// The NegVF/NegVD must not be predicated.
21942179
instruct vfmls1(vReg dst_src1, vReg src2, vReg src3) %{
2195-
predicate(UseFMA && !n->in(2)->in(1)->as_Vector()->is_predicated_vector());
2180+
predicate(UseFMA);
21962181
match(Set dst_src1 (FmaVF dst_src1 (Binary (NegVF src2) src3)));
21972182
match(Set dst_src1 (FmaVD dst_src1 (Binary (NegVD src2) src3)));
21982183
format %{ "vfmls1 $dst_src1, $src2, $src3" %}
@@ -2212,9 +2197,8 @@ instruct vfmls1(vReg dst_src1, vReg src2, vReg src3) %{
22122197
%}
22132198

22142199
// dst_src1 = dst_src1 + src2 * -src3
2215-
// The NegVF/NegVD must not be predicated.
22162200
instruct vfmls2(vReg dst_src1, vReg src2, vReg src3) %{
2217-
predicate(UseFMA && !n->in(2)->in(2)->as_Vector()->is_predicated_vector());
2201+
predicate(UseFMA);
22182202
match(Set dst_src1 (FmaVF dst_src1 (Binary src2 (NegVF src3))));
22192203
match(Set dst_src1 (FmaVD dst_src1 (Binary src2 (NegVD src3))));
22202204
format %{ "vfmls2 $dst_src1, $src2, $src3" %}
@@ -2236,10 +2220,8 @@ instruct vfmls2(vReg dst_src1, vReg src2, vReg src3) %{
22362220
// vector fmsb - predicated
22372221

22382222
// dst_src1 = dst_src1 * -src2 + src3
2239-
// The NegVF/NegVD must not be predicated.
22402223
instruct vfmsb_masked(vReg dst_src1, vReg src2, vReg src3, pRegGov pg) %{
2241-
predicate(UseFMA && UseSVE > 0 &&
2242-
!n->in(1)->in(2)->as_Vector()->is_predicated_vector());
2224+
predicate(UseFMA && UseSVE > 0);
22432225
match(Set dst_src1 (FmaVF (Binary dst_src1 (NegVF src2)) (Binary src3 pg)));
22442226
match(Set dst_src1 (FmaVD (Binary dst_src1 (NegVD src2)) (Binary src3 pg)));
22452227
format %{ "vfmsb_masked $dst_src1, $pg, $src2, $src3" %}
@@ -2254,11 +2236,8 @@ instruct vfmsb_masked(vReg dst_src1, vReg src2, vReg src3, pRegGov pg) %{
22542236
// vector fnmla (sve)
22552237

22562238
// dst_src1 = -dst_src1 + -src2 * src3
2257-
// The NegVF/NegVD must not be predicated.
22582239
instruct vfnmla1(vReg dst_src1, vReg src2, vReg src3) %{
2259-
predicate(UseFMA && UseSVE > 0 &&
2260-
!n->in(1)->as_Vector()->is_predicated_vector() &&
2261-
!n->in(2)->in(1)->as_Vector()->is_predicated_vector());
2240+
predicate(UseFMA && UseSVE > 0);
22622241
match(Set dst_src1 (FmaVF (NegVF dst_src1) (Binary (NegVF src2) src3)));
22632242
match(Set dst_src1 (FmaVD (NegVD dst_src1) (Binary (NegVD src2) src3)));
22642243
format %{ "vfnmla1 $dst_src1, $src2, $src3" %}
@@ -2271,11 +2250,8 @@ instruct vfnmla1(vReg dst_src1, vReg src2, vReg src3) %{
22712250
%}
22722251

22732252
// dst_src1 = -dst_src1 + src2 * -src3
2274-
// The NegVF/NegVD must not be predicated.
22752253
instruct vfnmla2(vReg dst_src1, vReg src2, vReg src3) %{
2276-
predicate(UseFMA && UseSVE > 0 &&
2277-
!n->in(1)->as_Vector()->is_predicated_vector() &&
2278-
!n->in(2)->in(2)->as_Vector()->is_predicated_vector());
2254+
predicate(UseFMA && UseSVE > 0);
22792255
match(Set dst_src1 (FmaVF (NegVF dst_src1) (Binary src2 (NegVF src3))));
22802256
match(Set dst_src1 (FmaVD (NegVD dst_src1) (Binary src2 (NegVD src3))));
22812257
format %{ "vfnmla2 $dst_src1, $src2, $src3" %}
@@ -2290,11 +2266,8 @@ instruct vfnmla2(vReg dst_src1, vReg src2, vReg src3) %{
22902266
// vector fnmad - predicated
22912267

22922268
// dst_src1 = -src3 + dst_src1 * -src2
2293-
// The NegVF/NegVD must not be predicated.
22942269
instruct vfnmad_masked(vReg dst_src1, vReg src2, vReg src3, pRegGov pg) %{
2295-
predicate(UseFMA && UseSVE > 0 &&
2296-
!n->in(1)->in(2)->as_Vector()->is_predicated_vector() &&
2297-
!n->in(2)->in(1)->as_Vector()->is_predicated_vector());
2270+
predicate(UseFMA && UseSVE > 0);
22982271
match(Set dst_src1 (FmaVF (Binary dst_src1 (NegVF src2)) (Binary (NegVF src3) pg)));
22992272
match(Set dst_src1 (FmaVD (Binary dst_src1 (NegVD src2)) (Binary (NegVD src3) pg)));
23002273
format %{ "vfnmad_masked $dst_src1, $pg, $src2, $src3" %}
@@ -2309,10 +2282,8 @@ instruct vfnmad_masked(vReg dst_src1, vReg src2, vReg src3, pRegGov pg) %{
23092282
// vector fnmls (sve)
23102283

23112284
// dst_src1 = -dst_src1 + src2 * src3
2312-
// The NegVF/NegVD must not be predicated.
23132285
instruct vfnmls(vReg dst_src1, vReg src2, vReg src3) %{
2314-
predicate(UseFMA && UseSVE > 0 &&
2315-
!n->in(1)->as_Vector()->is_predicated_vector());
2286+
predicate(UseFMA && UseSVE > 0);
23162287
match(Set dst_src1 (FmaVF (NegVF dst_src1) (Binary src2 src3)));
23172288
match(Set dst_src1 (FmaVD (NegVD dst_src1) (Binary src2 src3)));
23182289
format %{ "vfnmls $dst_src1, $src2, $src3" %}
@@ -2327,10 +2298,8 @@ instruct vfnmls(vReg dst_src1, vReg src2, vReg src3) %{
23272298
// vector fnmsb - predicated
23282299

23292300
// dst_src1 = -src3 + dst_src1 * src2
2330-
// The NegVF/NegVD must not be predicated.
23312301
instruct vfnmsb_masked(vReg dst_src1, vReg src2, vReg src3, pRegGov pg) %{
2332-
predicate(UseFMA && UseSVE > 0 &&
2333-
!n->in(2)->in(1)->as_Vector()->is_predicated_vector());
2302+
predicate(UseFMA && UseSVE > 0);
23342303
match(Set dst_src1 (FmaVF (Binary dst_src1 src2) (Binary (NegVF src3) pg)));
23352304
match(Set dst_src1 (FmaVD (Binary dst_src1 src2) (Binary (NegVD src3) pg)));
23362305
format %{ "vfnmsb_masked $dst_src1, $pg, $src2, $src3" %}
@@ -4691,8 +4660,7 @@ instruct vloadmask_neon(vReg dst, vReg src) %{
46914660
%}
46924661

46934662
instruct vloadmaskB_sve(pRegGov dst, vReg src, rFlagsReg cr) %{
4694-
predicate(UseSVE > 0 && !n->is_predicated_vector() &&
4695-
Matcher::vector_element_basic_type(n) == T_BYTE);
4663+
predicate(UseSVE > 0 && Matcher::vector_element_basic_type(n) == T_BYTE);
46964664
match(Set dst (VectorLoadMask src));
46974665
effect(KILL cr);
46984666
format %{ "vloadmaskB_sve $dst, $src\t# KILL cr" %}
@@ -4704,8 +4672,7 @@ instruct vloadmaskB_sve(pRegGov dst, vReg src, rFlagsReg cr) %{
47044672
%}
47054673

47064674
instruct vloadmask_extend_sve(pRegGov dst, vReg src, vReg tmp, rFlagsReg cr) %{
4707-
predicate(UseSVE > 0 && !n->is_predicated_vector() &&
4708-
Matcher::vector_element_basic_type(n) != T_BYTE);
4675+
predicate(UseSVE > 0 && Matcher::vector_element_basic_type(n) != T_BYTE);
47094676
match(Set dst (VectorLoadMask src));
47104677
effect(TEMP tmp, KILL cr);
47114678
format %{ "vloadmask_extend_sve $dst, $src\t# KILL $tmp, cr" %}
@@ -4812,7 +4779,7 @@ instruct vstoremask_narrow_sve(vReg dst, pRegGov src, immI_gt_1 size, vReg tmp)
48124779

48134780
// VectorLoadMask+LoadVector, and the VectorLoadMask is unpredicated.
48144781
instruct vloadmask_loadV(pRegGov dst, indirect mem, vReg tmp, rFlagsReg cr) %{
4815-
predicate(UseSVE > 0 && !n->is_predicated_vector() &&
4782+
predicate(UseSVE > 0 &&
48164783
type2aelembytes(Matcher::vector_element_basic_type(n)) > 1);
48174784
match(Set dst (VectorLoadMask (LoadVector mem)));
48184785
effect(TEMP tmp, KILL cr);
@@ -4855,7 +4822,7 @@ instruct vloadmask_loadV_masked(pRegGov dst, indirect mem, pRegGov pg,
48554822

48564823
// VectorLoadMask+LoadVectorMasked, and the VectorLoadMask is unpredicated.
48574824
instruct vloadmask_loadVMasked(pRegGov dst, vmemA mem, pRegGov pg, vReg tmp, rFlagsReg cr) %{
4858-
predicate(UseSVE > 0 && !n->is_predicated_vector() &&
4825+
predicate(UseSVE > 0 &&
48594826
type2aelembytes(Matcher::vector_element_basic_type(n)) > 1);
48604827
match(Set dst (VectorLoadMask (LoadVectorMasked mem pg)));
48614828
effect(TEMP tmp, KILL cr);
@@ -5309,7 +5276,7 @@ instruct vmask_firsttrue_8or16e(iRegINoSp dst, vReg src) %{
53095276
// them are set.
53105277

53115278
instruct vmask_firsttrue_sve(iRegINoSp dst, pReg src, pReg ptmp) %{
5312-
predicate(UseSVE > 0 && !n->is_predicated_vector());
5279+
predicate(UseSVE > 0);
53135280
match(Set dst (VectorMaskFirstTrue src));
53145281
effect(TEMP ptmp);
53155282
format %{ "vmask_firsttrue_sve $dst, $src\t# KILL $ptmp" %}
@@ -5471,7 +5438,7 @@ instruct vmaskAll_immI(pRegGov dst, immI src, rFlagsReg cr) %{
54715438
%}
54725439

54735440
instruct vmaskAllI(pRegGov dst, iRegIorL2I src, vReg tmp, rFlagsReg cr) %{
5474-
predicate(UseSVE > 0 && !n->is_predicated_vector());
5441+
predicate(UseSVE > 0);
54755442
match(Set dst (MaskAll src));
54765443
effect(TEMP tmp, KILL cr);
54775444
format %{ "vmaskAllI $dst, $src\t# KILL $tmp, cr" %}
@@ -5520,7 +5487,7 @@ instruct vmaskAll_immL(pRegGov dst, immL src, rFlagsReg cr) %{
55205487
%}
55215488

55225489
instruct vmaskAllL(pRegGov dst, iRegL src, vReg tmp, rFlagsReg cr) %{
5523-
predicate(UseSVE > 0 && !n->is_predicated_vector());
5490+
predicate(UseSVE > 0);
55245491
match(Set dst (MaskAll src));
55255492
effect(TEMP tmp, KILL cr);
55265493
format %{ "vmaskAllL $dst, $src\t# KILL $tmp, cr" %}
@@ -5593,7 +5560,6 @@ instruct vmask_gen_imm(pRegGov pd, immL con, rFlagsReg cr) %{
55935560
// vector popcount - INT
55945561

55955562
instruct vpopcountI(vReg dst, vReg src) %{
5596-
predicate(!n->as_Vector()->is_predicated_vector());
55975563
match(Set dst (PopCountVI src));
55985564
format %{ "vpopcountI $dst, $src" %}
55995565
ins_encode %{
@@ -5631,8 +5597,7 @@ instruct vpopcountI(vReg dst, vReg src) %{
56315597
// vector popcount - LONG
56325598

56335599
instruct vpopcountL(vReg dst, vReg src) %{
5634-
predicate(Matcher::vector_element_basic_type(n) == T_LONG &&
5635-
!n->as_Vector()->is_predicated_vector());
5600+
predicate(Matcher::vector_element_basic_type(n) == T_LONG);
56365601
match(Set dst (PopCountVL src));
56375602
format %{ "vpopcountL $dst, $src" %}
56385603
ins_encode %{
@@ -5654,8 +5619,7 @@ instruct vpopcountL(vReg dst, vReg src) %{
56545619
// "vpopcountL" rule.
56555620

56565621
instruct vpopcountL_I(vReg dst, vReg src, vReg tmp) %{
5657-
predicate(Matcher::vector_element_basic_type(n) == T_INT &&
5658-
!n->as_Vector()->is_predicated_vector());
5622+
predicate(Matcher::vector_element_basic_type(n) == T_INT);
56595623
match(Set dst (PopCountVL src));
56605624
effect(TEMP_DEF dst, TEMP tmp);
56615625
format %{ "vpopcountL_I $dst, $src\t# KILL $tmp" %}
@@ -6106,7 +6070,6 @@ instruct scatter_storeD_masked(indirect mem, vReg src, vReg idx, pRegGov pg, vRe
61066070
// ------------------------------ CountLeadingZerosV ---------------------------
61076071

61086072
instruct vcountLeadingZeros(vReg dst, vReg src) %{
6109-
predicate(!n->as_Vector()->is_predicated_vector());
61106073
match(Set dst (CountLeadingZerosV src));
61116074
format %{ "vcountLeadingZeros $dst, $src" %}
61126075
ins_encode %{
@@ -6154,7 +6117,6 @@ instruct vcountLeadingZeros_masked(vReg dst_src, pRegGov pg) %{
61546117
// ------------------------------ CountTrailingZerosV --------------------------
61556118

61566119
instruct vcountTrailingZeros(vReg dst, vReg src) %{
6157-
predicate(!n->as_Vector()->is_predicated_vector());
61586120
match(Set dst (CountTrailingZerosV src));
61596121
format %{ "vcountTrailingZeros $dst, $src" %}
61606122
ins_encode %{
@@ -6216,7 +6178,6 @@ instruct vcountTrailingZeros_masked(vReg dst_src, pRegGov pg) %{
62166178
// ------------------------------ ReverseV -------------------------------------
62176179

62186180
instruct vreverse(vReg dst, vReg src) %{
6219-
predicate(!n->as_Vector()->is_predicated_vector());
62206181
match(Set dst (ReverseV src));
62216182
format %{ "vreverse $dst, $src" %}
62226183
ins_encode %{
@@ -6263,7 +6224,6 @@ instruct vreverse_masked(vReg dst_src, pRegGov pg) %{
62636224
// ------------------------------ ReverseBytesV --------------------------------
62646225

62656226
instruct vreverseBytes(vReg dst, vReg src) %{
6266-
predicate(!n->as_Vector()->is_predicated_vector());
62676227
match(Set dst (ReverseBytesV src));
62686228
format %{ "vreverseBytes $dst, $src" %}
62696229
ins_encode %{

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