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8347794: RISC-V: Add Zfhmin - Float cleanup
Reviewed-by: fyang, mli
1 parent 9b98cc0 commit fb43849

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8 files changed

+403
-233
lines changed

8 files changed

+403
-233
lines changed

‎src/hotspot/cpu/riscv/assembler_riscv.hpp‎

Lines changed: 386 additions & 224 deletions
Large diffs are not rendered by default.

‎src/hotspot/cpu/riscv/assembler_riscv.inline.hpp‎

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -38,6 +38,7 @@ inline bool Assembler::is_simm13(int64_t x) { return is_simm(x, 13); }
3838
inline bool Assembler::is_simm18(int64_t x) { return is_simm(x, 18); }
3939
inline bool Assembler::is_simm21(int64_t x) { return is_simm(x, 21); }
4040

41+
inline bool Assembler::is_uimm2(uint64_t x) { return is_uimm(x, 2); }
4142
inline bool Assembler::is_uimm3(uint64_t x) { return is_uimm(x, 3); }
4243
inline bool Assembler::is_uimm5(uint64_t x) { return is_uimm(x, 5); }
4344
inline bool Assembler::is_uimm6(uint64_t x) { return is_uimm(x, 6); }

‎src/hotspot/cpu/riscv/c2_MacroAssembler_riscv.cpp‎

Lines changed: 3 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -2058,7 +2058,7 @@ void C2_MacroAssembler::minmax_fp(FloatRegister dst, FloatRegister src1, FloatRe
20582058
is_double ? fclass_d(t1, src2)
20592059
: fclass_s(t1, src2);
20602060
orr(t0, t0, t1);
2061-
andi(t0, t0, fclass_mask::nan); // if src1 or src2 is quiet or signaling NaN then return NaN
2061+
andi(t0, t0, FClassBits::nan); // if src1 or src2 is quiet or signaling NaN then return NaN
20622062
beqz(t0, Compare);
20632063
is_double ? fadd_d(dst, src1, src2)
20642064
: fadd_s(dst, src1, src2);
@@ -2152,7 +2152,7 @@ void C2_MacroAssembler::signum_fp(FloatRegister dst, FloatRegister one, bool is_
21522152
: fclass_s(t0, dst);
21532153

21542154
// check if input is -0, +0, signaling NaN or quiet NaN
2155-
andi(t0, t0, fclass_mask::zero | fclass_mask::nan);
2155+
andi(t0, t0, FClassBits::zero | FClassBits::nan);
21562156

21572157
bnez(t0, done);
21582158

@@ -2368,7 +2368,7 @@ void C2_MacroAssembler::signum_fp_v(VectorRegister dst, VectorRegister one, Basi
23682368

23692369
// check if input is -0, +0, signaling NaN or quiet NaN
23702370
vfclass_v(v0, dst);
2371-
mv(t0, fclass_mask::zero | fclass_mask::nan);
2371+
mv(t0, FClassBits::zero | FClassBits::nan);
23722372
vand_vx(v0, v0, t0);
23732373
vmseq_vi(v0, v0, 0);
23742374

‎src/hotspot/cpu/riscv/globals_riscv.hpp‎

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -104,6 +104,7 @@ define_pd_global(intx, InlineSmallCode, 1000);
104104
product(bool, UseZbb, false, DIAGNOSTIC, "Use Zbb instructions") \
105105
product(bool, UseZbs, false, DIAGNOSTIC, "Use Zbs instructions") \
106106
product(bool, UseZfh, false, DIAGNOSTIC, "Use Zfh instructions") \
107+
product(bool, UseZfhmin, false, DIAGNOSTIC, "Use Zfhmin instructions") \
107108
product(bool, UseZacas, false, EXPERIMENTAL, "Use Zacas instructions") \
108109
product(bool, UseZcb, false, EXPERIMENTAL, "Use Zcb instructions") \
109110
product(bool, UseZic64b, false, EXPERIMENTAL, "Use Zic64b instructions") \

‎src/hotspot/cpu/riscv/macroAssembler_riscv.cpp‎

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -5886,7 +5886,7 @@ void MacroAssembler::FLOATCVT##_safe(Register dst, FloatRegister src, Register t
58865886
fclass_##FLOATSIG(tmp, src); \
58875887
mv(dst, zr); \
58885888
/* check if src is NaN */ \
5889-
andi(tmp, tmp, fclass_mask::nan); \
5889+
andi(tmp, tmp, FClassBits::nan); \
58905890
bnez(tmp, done); \
58915891
FLOATCVT(dst, src); \
58925892
bind(done); \

‎src/hotspot/cpu/riscv/riscv.ad‎

Lines changed: 5 additions & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -1918,7 +1918,7 @@ bool Matcher::match_rule_supported(int opcode) {
19181918

19191919
case Op_ConvHF2F:
19201920
case Op_ConvF2HF:
1921-
return UseZfh;
1921+
return UseZfh || UseZfhmin;
19221922
}
19231923

19241924
return true; // Per default match rules are supported.
@@ -7348,7 +7348,7 @@ instruct isInfiniteF_reg_reg(iRegINoSp dst, fRegF src)
73487348
format %{ "isInfinite $dst, $src" %}
73497349
ins_encode %{
73507350
__ fclass_s(as_Register($dst$$reg), as_FloatRegister($src$$reg));
7351-
__ andi(as_Register($dst$$reg), as_Register($dst$$reg), Assembler::fclass_mask::inf);
7351+
__ andi(as_Register($dst$$reg), as_Register($dst$$reg), Assembler::FClassBits::inf);
73527352
__ slt(as_Register($dst$$reg), zr, as_Register($dst$$reg));
73537353
%}
73547354

@@ -7363,7 +7363,7 @@ instruct isInfiniteD_reg_reg(iRegINoSp dst, fRegD src)
73637363
format %{ "isInfinite $dst, $src" %}
73647364
ins_encode %{
73657365
__ fclass_d(as_Register($dst$$reg), as_FloatRegister($src$$reg));
7366-
__ andi(as_Register($dst$$reg), as_Register($dst$$reg), Assembler::fclass_mask::inf);
7366+
__ andi(as_Register($dst$$reg), as_Register($dst$$reg), Assembler::FClassBits::inf);
73677367
__ slt(as_Register($dst$$reg), zr, as_Register($dst$$reg));
73687368
%}
73697369

@@ -7378,7 +7378,7 @@ instruct isFiniteF_reg_reg(iRegINoSp dst, fRegF src)
73787378
format %{ "isFinite $dst, $src" %}
73797379
ins_encode %{
73807380
__ fclass_s(as_Register($dst$$reg), as_FloatRegister($src$$reg));
7381-
__ andi(as_Register($dst$$reg), as_Register($dst$$reg), Assembler::fclass_mask::finite);
7381+
__ andi(as_Register($dst$$reg), as_Register($dst$$reg), Assembler::FClassBits::finite);
73827382
__ slt(as_Register($dst$$reg), zr, as_Register($dst$$reg));
73837383
%}
73847384

@@ -7393,7 +7393,7 @@ instruct isFiniteD_reg_reg(iRegINoSp dst, fRegD src)
73937393
format %{ "isFinite $dst, $src" %}
73947394
ins_encode %{
73957395
__ fclass_d(as_Register($dst$$reg), as_FloatRegister($src$$reg));
7396-
__ andi(as_Register($dst$$reg), as_Register($dst$$reg), Assembler::fclass_mask::finite);
7396+
__ andi(as_Register($dst$$reg), as_Register($dst$$reg), Assembler::FClassBits::finite);
73977397
__ slt(as_Register($dst$$reg), zr, as_Register($dst$$reg));
73987398
%}
73997399

‎src/hotspot/cpu/riscv/vm_version_riscv.hpp‎

Lines changed: 3 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -115,6 +115,7 @@ class VM_Version : public Abstract_VM_Version {
115115
// Zbs Single-bit instructions
116116
//
117117
// Zfh Half-Precision Floating-Point instructions
118+
// Zfhmin Minimal Half-Precision Floating-Point instructions
118119
//
119120
// Zicond Conditional operations
120121
//
@@ -157,6 +158,7 @@ class VM_Version : public Abstract_VM_Version {
157158
decl(ext_Zbs , "Zbs" , RV_NO_FLAG_BIT, true , UPDATE_DEFAULT(UseZbs)) \
158159
decl(ext_Zcb , "Zcb" , RV_NO_FLAG_BIT, true , UPDATE_DEFAULT(UseZcb)) \
159160
decl(ext_Zfh , "Zfh" , RV_NO_FLAG_BIT, true , UPDATE_DEFAULT(UseZfh)) \
161+
decl(ext_Zfhmin , "Zfhmin" , RV_NO_FLAG_BIT, true , UPDATE_DEFAULT(UseZfhmin)) \
160162
decl(ext_Zicsr , "Zicsr" , RV_NO_FLAG_BIT, true , NO_UPDATE_DEFAULT) \
161163
decl(ext_Zicntr , "Zicntr" , RV_NO_FLAG_BIT, true , NO_UPDATE_DEFAULT) \
162164
decl(ext_Zifencei , "Zifencei" , RV_NO_FLAG_BIT, true , NO_UPDATE_DEFAULT) \
@@ -224,6 +226,7 @@ class VM_Version : public Abstract_VM_Version {
224226
RV_ENABLE_EXTENSION(UseZbb) \
225227
RV_ENABLE_EXTENSION(UseZbs) \
226228
RV_ENABLE_EXTENSION(UseZcb) \
229+
RV_ENABLE_EXTENSION(UseZfhmin) \
227230
RV_ENABLE_EXTENSION(UseZic64b) \
228231
RV_ENABLE_EXTENSION(UseZicbom) \
229232
RV_ENABLE_EXTENSION(UseZicbop) \

‎src/hotspot/os_cpu/linux_riscv/riscv_hwprobe.cpp‎

Lines changed: 3 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -177,6 +177,9 @@ void RiscvHwprobe::add_features_from_query_result() {
177177
if (is_set(RISCV_HWPROBE_KEY_IMA_EXT_0, RISCV_HWPROBE_EXT_ZFH)) {
178178
VM_Version::ext_Zfh.enable_feature();
179179
}
180+
if (is_set(RISCV_HWPROBE_KEY_IMA_EXT_0, RISCV_HWPROBE_EXT_ZFHMIN)) {
181+
VM_Version::ext_Zfhmin.enable_feature();
182+
}
180183
if (is_set(RISCV_HWPROBE_KEY_IMA_EXT_0, RISCV_HWPROBE_EXT_ZVBC)) {
181184
VM_Version::ext_Zvbc.enable_feature();
182185
}

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