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Srinivas Vamsi ParasaSandhya Viswanathan
Srinivas Vamsi Parasa
authored and
Sandhya Viswanathan
committed
8351994: Enable Extended EVEX to REX2/REX demotion when src and dst are the same
Reviewed-by: sviswanathan, jbhateja, epeter
1 parent a3f9e22 commit fc3d3d9

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8 files changed

+3382
-2612
lines changed

8 files changed

+3382
-2612
lines changed

‎src/hotspot/cpu/x86/assembler_x86.cpp‎

Lines changed: 288 additions & 307 deletions
Large diffs are not rendered by default.

‎src/hotspot/cpu/x86/assembler_x86.hpp‎

Lines changed: 28 additions & 11 deletions
Original file line numberDiff line numberDiff line change
@@ -772,36 +772,53 @@ class Assembler : public AbstractAssembler {
772772
void evex_prefix(bool vex_r, bool vex_b, bool vex_x, bool evex_v, bool evex_r, bool evex_b,
773773
bool eevex_x, int nds_enc, VexSimdPrefix pre, VexOpcode opc, bool no_flags = false);
774774

775-
void evex_prefix_ndd(Address adr, int ndd_enc, int xreg_enc, VexSimdPrefix pre, VexOpcode opc,
776-
InstructionAttr *attributes, bool no_flags = false);
775+
void eevex_prefix_ndd(Address adr, int ndd_enc, int xreg_enc, VexSimdPrefix pre, VexOpcode opc,
776+
InstructionAttr *attributes, bool no_flags = false);
777777

778-
void evex_prefix_nf(Address adr, int ndd_enc, int xreg_enc, VexSimdPrefix pre, VexOpcode opc,
779-
InstructionAttr *attributes, bool no_flags = false);
778+
void eevex_prefix_nf(Address adr, int ndd_enc, int xreg_enc, VexSimdPrefix pre, VexOpcode opc,
779+
InstructionAttr *attributes, bool no_flags = false);
780780

781781
void vex_prefix(Address adr, int nds_enc, int xreg_enc, VexSimdPrefix pre, VexOpcode opc,
782782
InstructionAttr *attributes, bool nds_is_ndd = false, bool no_flags = false);
783783

784-
int vex_prefix_and_encode(int dst_enc, int nds_enc, int src_enc,
784+
int vex_prefix_and_encode(int dst_enc, int nds_enc, int src_enc,
785785
VexSimdPrefix pre, VexOpcode opc,
786786
InstructionAttr *attributes, bool src_is_gpr = false, bool nds_is_ndd = false, bool no_flags = false);
787787

788-
int evex_prefix_and_encode_ndd(int dst_enc, int nds_enc, int src_enc, VexSimdPrefix pre, VexOpcode opc,
789-
InstructionAttr *attributes, bool no_flags = false);
790-
791-
int evex_prefix_and_encode_nf(int dst_enc, int nds_enc, int src_enc, VexSimdPrefix pre, VexOpcode opc,
788+
int eevex_prefix_and_encode_nf(int dst_enc, int nds_enc, int src_enc, VexSimdPrefix pre, VexOpcode opc,
792789
InstructionAttr *attributes, bool no_flags = false);
793790

791+
int emit_eevex_prefix_ndd(int dst_enc, VexSimdPrefix pre, VexOpcode opc, InstructionAttr *attributes, bool no_flags = false);
792+
793+
int emit_eevex_prefix_or_demote_ndd(int dst_enc, int nds_enc, int src_enc, VexSimdPrefix pre, VexOpcode opc,
794+
InstructionAttr *attributes, bool no_flags = false, bool use_prefixq = false);
795+
796+
int emit_eevex_prefix_or_demote_ndd(int dst_enc, int nds_enc, VexSimdPrefix pre, VexOpcode opc,
797+
InstructionAttr *attributes, bool no_flags = false, bool use_prefixq = false);
798+
799+
void emit_eevex_prefix_or_demote_arith_ndd(Register dst, Register nds, int32_t imm32, VexSimdPrefix pre, VexOpcode opc,
800+
int size, int op1, int op2, bool no_flags);
801+
802+
void emit_eevex_or_demote(Register dst, Register src1, Address src2, VexSimdPrefix pre, VexOpcode opc,
803+
int size, int opcode_byte, bool no_flags = false, bool is_map1 = false);
804+
805+
void emit_eevex_or_demote(int dst_enc, int nds_enc, int src_enc, VexSimdPrefix pre, VexOpcode opc,
806+
int size, int opcode_byte, bool no_flags, bool is_map1 = false, bool swap = false);
807+
808+
void emit_eevex_or_demote(int dst_enc, int nds_enc, int src_enc, int8_t imm8, VexSimdPrefix pre, VexOpcode opc,
809+
int size, int opcode_byte, bool no_flags, bool is_map1 = false);
810+
794811
void simd_prefix(XMMRegister xreg, XMMRegister nds, Address adr, VexSimdPrefix pre,
795812
VexOpcode opc, InstructionAttr *attributes);
796813

797814
int simd_prefix_and_encode(XMMRegister dst, XMMRegister nds, XMMRegister src, VexSimdPrefix pre,
798815
VexOpcode opc, InstructionAttr *attributes, bool src_is_gpr = false);
799816

800817
// Helper functions for groups of instructions
818+
bool is_demotable(bool no_flags, int dst_enc, int nds_enc);
801819
void emit_arith_b(int op1, int op2, Register dst, int imm8);
802820

803-
void emit_arith(int op1, int op2, Register dst, int32_t imm32);
804-
void emit_arith_ndd(int op1, int op2, Register dst, int32_t imm32);
821+
void emit_arith(int op1, int op2, Register dst, int32_t imm32, bool optimize_rax_dst = true);
805822
// Force generation of a 4 byte immediate value even if it fits into 8bit
806823
void emit_arith_imm32(int op1, int op2, Register dst, int32_t imm32);
807824
void emit_arith(int op1, int op2, Register dst, Register src);

‎src/hotspot/cpu/x86/vm_version_x86.cpp‎

Lines changed: 6 additions & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -909,7 +909,7 @@ void VM_Version::get_processor_features() {
909909
}
910910

911911
// Check if processor has Intel Ecore
912-
if (FLAG_IS_DEFAULT(EnableX86ECoreOpts) && is_intel() && cpu_family() == 6 &&
912+
if (FLAG_IS_DEFAULT(EnableX86ECoreOpts) && is_intel() && is_intel_server_family() &&
913913
(_model == 0x97 || _model == 0xAA || _model == 0xAC || _model == 0xAF ||
914914
_model == 0xCC || _model == 0xDD)) {
915915
FLAG_SET_DEFAULT(EnableX86ECoreOpts, true);
@@ -1594,7 +1594,7 @@ void VM_Version::get_processor_features() {
15941594
if (FLAG_IS_DEFAULT(UseStoreImmI16)) {
15951595
UseStoreImmI16 = false; // don't use it on Intel cpus
15961596
}
1597-
if (cpu_family() == 6 || cpu_family() == 15) {
1597+
if (is_intel_server_family() || cpu_family() == 15) {
15981598
if (FLAG_IS_DEFAULT(UseAddressNop)) {
15991599
// Use it on all Intel cpus starting from PentiumPro
16001600
UseAddressNop = true;
@@ -1610,7 +1610,7 @@ void VM_Version::get_processor_features() {
16101610
UseXmmRegToRegMoveAll = false;
16111611
}
16121612
}
1613-
if (cpu_family() == 6 && supports_sse3()) { // New Intel cpus
1613+
if (is_intel_server_family() && supports_sse3()) { // New Intel cpus
16141614
#ifdef COMPILER2
16151615
if (FLAG_IS_DEFAULT(MaxLoopPad)) {
16161616
// For new Intel cpus do the next optimization:
@@ -1848,7 +1848,7 @@ void VM_Version::get_processor_features() {
18481848
FLAG_SET_DEFAULT(AllocatePrefetchDistance, allocate_prefetch_distance(use_watermark_prefetch));
18491849
}
18501850

1851-
if (is_intel() && cpu_family() == 6 && supports_sse3()) {
1851+
if (is_intel() && is_intel_server_family() && supports_sse3()) {
18521852
if (FLAG_IS_DEFAULT(AllocatePrefetchLines) &&
18531853
supports_sse4_2() && supports_ht()) { // Nehalem based cpus
18541854
FLAG_SET_DEFAULT(AllocatePrefetchLines, 4);
@@ -3262,15 +3262,15 @@ int VM_Version::allocate_prefetch_distance(bool use_watermark_prefetch) {
32623262
return 128; // Athlon
32633263
}
32643264
} else { // Intel
3265-
if (supports_sse3() && cpu_family() == 6) {
3265+
if (supports_sse3() && is_intel_server_family()) {
32663266
if (supports_sse4_2() && supports_ht()) { // Nehalem based cpus
32673267
return 192;
32683268
} else if (use_watermark_prefetch) { // watermark prefetching on Core
32693269
return 384;
32703270
}
32713271
}
32723272
if (supports_sse2()) {
3273-
if (cpu_family() == 6) {
3273+
if (is_intel_server_family()) {
32743274
return 256; // Pentium M, Core, Core2
32753275
} else {
32763276
return 512; // Pentium 4

‎src/hotspot/cpu/x86/vm_version_x86.hpp‎

Lines changed: 2 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -791,6 +791,7 @@ class VM_Version : public Abstract_VM_Version {
791791
static uint32_t cpu_stepping() { return _cpuid_info.cpu_stepping(); }
792792
static int cpu_family() { return _cpu;}
793793
static bool is_P6() { return cpu_family() >= 6; }
794+
static bool is_intel_server_family() { return cpu_family() == 6 || cpu_family() == 19; }
794795
static bool is_amd() { assert_is_initialized(); return _cpuid_info.std_vendor_name_0 == 0x68747541; } // 'htuA'
795796
static bool is_hygon() { assert_is_initialized(); return _cpuid_info.std_vendor_name_0 == 0x6F677948; } // 'ogyH'
796797
static bool is_amd_family() { return is_amd() || is_hygon(); }
@@ -946,7 +947,7 @@ class VM_Version : public Abstract_VM_Version {
946947
}
947948

948949
// Intel Core and newer cpus have fast IDIV instruction (excluding Atom).
949-
static bool has_fast_idiv() { return is_intel() && cpu_family() == 6 &&
950+
static bool has_fast_idiv() { return is_intel() && is_intel_server_family() &&
950951
supports_sse3() && _model != 0x1C; }
951952

952953
static bool supports_compare_and_exchange() { return true; }

‎src/hotspot/cpu/x86/x86_64.ad‎

Lines changed: 0 additions & 135 deletions
Original file line numberDiff line numberDiff line change
@@ -7052,21 +7052,6 @@ instruct addI_rReg_mem(rRegI dst, memory src, rFlagsReg cr)
70527052
ins_pipe(ialu_reg_mem);
70537053
%}
70547054

7055-
instruct addI_rReg_mem_rReg_ndd(rRegI dst, memory src1, rRegI src2, rFlagsReg cr)
7056-
%{
7057-
predicate(UseAPX);
7058-
match(Set dst (AddI (LoadI src1) src2));
7059-
effect(KILL cr);
7060-
flag(PD::Flag_sets_overflow_flag, PD::Flag_sets_sign_flag, PD::Flag_sets_zero_flag, PD::Flag_sets_carry_flag, PD::Flag_sets_parity_flag);
7061-
7062-
ins_cost(150);
7063-
format %{ "eaddl $dst, $src1, $src2\t# int ndd" %}
7064-
ins_encode %{
7065-
__ eaddl($dst$$Register, $src1$$Address, $src2$$Register, false);
7066-
%}
7067-
ins_pipe(ialu_reg_mem);
7068-
%}
7069-
70707055
instruct addI_rReg_rReg_mem_ndd(rRegI dst, rRegI src1, memory src2, rFlagsReg cr)
70717056
%{
70727057
predicate(UseAPX);
@@ -7370,21 +7355,6 @@ instruct addL_rReg_rReg_mem_ndd(rRegL dst, rRegL src1, memory src2, rFlagsReg cr
73707355
ins_pipe(ialu_reg_mem);
73717356
%}
73727357

7373-
instruct addL_rReg_mem_rReg_ndd(rRegL dst, memory src1, rRegL src2, rFlagsReg cr)
7374-
%{
7375-
predicate(UseAPX);
7376-
match(Set dst (AddL (LoadL src1) src2));
7377-
effect(KILL cr);
7378-
flag(PD::Flag_sets_overflow_flag, PD::Flag_sets_sign_flag, PD::Flag_sets_zero_flag, PD::Flag_sets_carry_flag, PD::Flag_sets_parity_flag);
7379-
7380-
ins_cost(150);
7381-
format %{ "eaddq $dst, $src1, $src2\t# long ndd" %}
7382-
ins_encode %{
7383-
__ eaddq($dst$$Register, $src1$$Address, $src2$$Register, false);
7384-
%}
7385-
ins_pipe(ialu_reg_mem);
7386-
%}
7387-
73887358
instruct addL_mem_rReg(memory dst, rRegL src, rFlagsReg cr)
73897359
%{
73907360
match(Set dst (StoreL dst (AddL (LoadL dst) src)));
@@ -8596,7 +8566,6 @@ instruct mulI_rReg_ndd(rRegI dst, rRegI src1, rRegI src2, rFlagsReg cr)
85968566

85978567
instruct mulI_rReg_imm(rRegI dst, rRegI src, immI imm, rFlagsReg cr)
85988568
%{
8599-
predicate(!UseAPX);
86008569
match(Set dst (MulI src imm));
86018570
effect(KILL cr);
86028571

@@ -8608,20 +8577,6 @@ instruct mulI_rReg_imm(rRegI dst, rRegI src, immI imm, rFlagsReg cr)
86088577
ins_pipe(ialu_reg_reg_alu0);
86098578
%}
86108579

8611-
instruct mulI_rReg_rReg_imm_ndd(rRegI dst, rRegI src1, immI src2, rFlagsReg cr)
8612-
%{
8613-
predicate(UseAPX);
8614-
match(Set dst (MulI src1 src2));
8615-
effect(KILL cr);
8616-
8617-
ins_cost(300);
8618-
format %{ "eimull $dst, $src1, $src2\t# int ndd" %}
8619-
ins_encode %{
8620-
__ eimull($dst$$Register, $src1$$Register, $src2$$constant, false);
8621-
%}
8622-
ins_pipe(ialu_reg_reg_alu0);
8623-
%}
8624-
86258580
instruct mulI_mem(rRegI dst, memory src, rFlagsReg cr)
86268581
%{
86278582
predicate(!UseAPX);
@@ -8652,7 +8607,6 @@ instruct mulI_rReg_rReg_mem_ndd(rRegI dst, rRegI src1, memory src2, rFlagsReg cr
86528607

86538608
instruct mulI_mem_imm(rRegI dst, memory src, immI imm, rFlagsReg cr)
86548609
%{
8655-
predicate(!UseAPX);
86568610
match(Set dst (MulI (LoadI src) imm));
86578611
effect(KILL cr);
86588612

@@ -8664,20 +8618,6 @@ instruct mulI_mem_imm(rRegI dst, memory src, immI imm, rFlagsReg cr)
86648618
ins_pipe(ialu_reg_mem_alu0);
86658619
%}
86668620

8667-
instruct mulI_rReg_mem_imm(rRegI dst, memory src1, immI src2, rFlagsReg cr)
8668-
%{
8669-
predicate(UseAPX);
8670-
match(Set dst (MulI (LoadI src1) src2));
8671-
effect(KILL cr);
8672-
8673-
ins_cost(300);
8674-
format %{ "eimull $dst, $src1, $src2\t# int ndd" %}
8675-
ins_encode %{
8676-
__ eimull($dst$$Register, $src1$$Address, $src2$$constant, false);
8677-
%}
8678-
ins_pipe(ialu_reg_mem_alu0);
8679-
%}
8680-
86818621
instruct mulAddS2I_rReg(rRegI dst, rRegI src1, rRegI src2, rRegI src3, rFlagsReg cr)
86828622
%{
86838623
match(Set dst (MulAddS2I (Binary dst src1) (Binary src2 src3)));
@@ -8718,7 +8658,6 @@ instruct mulL_rReg_ndd(rRegL dst, rRegL src1, rRegL src2, rFlagsReg cr)
87188658

87198659
instruct mulL_rReg_imm(rRegL dst, rRegL src, immL32 imm, rFlagsReg cr)
87208660
%{
8721-
predicate(!UseAPX);
87228661
match(Set dst (MulL src imm));
87238662
effect(KILL cr);
87248663

@@ -8730,20 +8669,6 @@ instruct mulL_rReg_imm(rRegL dst, rRegL src, immL32 imm, rFlagsReg cr)
87308669
ins_pipe(ialu_reg_reg_alu0);
87318670
%}
87328671

8733-
instruct mulL_rReg_rReg_imm_ndd(rRegL dst, rRegL src1, immL32 src2, rFlagsReg cr)
8734-
%{
8735-
predicate(UseAPX);
8736-
match(Set dst (MulL src1 src2));
8737-
effect(KILL cr);
8738-
8739-
ins_cost(300);
8740-
format %{ "eimulq $dst, $src1, $src2\t# long ndd" %}
8741-
ins_encode %{
8742-
__ eimulq($dst$$Register, $src1$$Register, $src2$$constant, false);
8743-
%}
8744-
ins_pipe(ialu_reg_reg_alu0);
8745-
%}
8746-
87478672
instruct mulL_mem(rRegL dst, memory src, rFlagsReg cr)
87488673
%{
87498674
predicate(!UseAPX);
@@ -8774,7 +8699,6 @@ instruct mulL_rReg_rReg_mem_ndd(rRegL dst, rRegL src1, memory src2, rFlagsReg cr
87748699

87758700
instruct mulL_mem_imm(rRegL dst, memory src, immL32 imm, rFlagsReg cr)
87768701
%{
8777-
predicate(!UseAPX);
87788702
match(Set dst (MulL (LoadL src) imm));
87798703
effect(KILL cr);
87808704

@@ -8786,20 +8710,6 @@ instruct mulL_mem_imm(rRegL dst, memory src, immL32 imm, rFlagsReg cr)
87868710
ins_pipe(ialu_reg_mem_alu0);
87878711
%}
87888712

8789-
instruct mulL_rReg_mem_imm_ndd(rRegL dst, memory src1, immL32 src2, rFlagsReg cr)
8790-
%{
8791-
predicate(UseAPX);
8792-
match(Set dst (MulL (LoadL src1) src2));
8793-
effect(KILL cr);
8794-
8795-
ins_cost(300);
8796-
format %{ "eimulq $dst, $src1, $src2\t# long ndd" %}
8797-
ins_encode %{
8798-
__ eimulq($dst$$Register, $src1$$Address, $src2$$constant, false);
8799-
%}
8800-
ins_pipe(ialu_reg_mem_alu0);
8801-
%}
8802-
88038713
instruct mulHiL_rReg(rdx_RegL dst, rRegL src, rax_RegL rax, rFlagsReg cr)
88048714
%{
88058715
match(Set dst (MulHiL src rax));
@@ -10689,21 +10599,6 @@ instruct xorI_rReg_rReg_mem_ndd(rRegI dst, rRegI src1, memory src2, rFlagsReg cr
1068910599
ins_pipe(ialu_reg_mem);
1069010600
%}
1069110601

10692-
instruct xorI_rReg_mem_rReg_ndd(rRegI dst, memory src1, rRegI src2, rFlagsReg cr)
10693-
%{
10694-
predicate(UseAPX);
10695-
match(Set dst (XorI (LoadI src1) src2));
10696-
effect(KILL cr);
10697-
flag(PD::Flag_sets_sign_flag, PD::Flag_sets_zero_flag, PD::Flag_sets_parity_flag, PD::Flag_clears_overflow_flag, PD::Flag_clears_carry_flag);
10698-
10699-
ins_cost(150);
10700-
format %{ "exorl $dst, $src1, $src2\t# int ndd" %}
10701-
ins_encode %{
10702-
__ exorl($dst$$Register, $src1$$Address, $src2$$Register, false);
10703-
%}
10704-
ins_pipe(ialu_reg_mem);
10705-
%}
10706-
1070710602
// Xor Memory with Register
1070810603
instruct xorB_mem_rReg(memory dst, rRegI src, rFlagsReg cr)
1070910604
%{
@@ -10883,21 +10778,6 @@ instruct andL_rReg_rReg_mem_ndd(rRegL dst, rRegL src1, memory src2, rFlagsReg cr
1088310778
ins_pipe(ialu_reg_mem);
1088410779
%}
1088510780

10886-
instruct andL_rReg_mem_rReg_ndd(rRegL dst, memory src1, rRegL src2, rFlagsReg cr)
10887-
%{
10888-
predicate(UseAPX);
10889-
match(Set dst (AndL (LoadL src1) src2));
10890-
effect(KILL cr);
10891-
flag(PD::Flag_sets_sign_flag, PD::Flag_sets_zero_flag, PD::Flag_sets_parity_flag, PD::Flag_clears_overflow_flag, PD::Flag_clears_carry_flag);
10892-
10893-
ins_cost(150);
10894-
format %{ "eandq $dst, $src1, $src2\t# long ndd" %}
10895-
ins_encode %{
10896-
__ eandq($dst$$Register, $src1$$Address, $src2$$Register, false);
10897-
%}
10898-
ins_pipe(ialu_reg_mem);
10899-
%}
10900-
1090110781
// And Memory with Register
1090210782
instruct andL_mem_rReg(memory dst, rRegL src, rFlagsReg cr)
1090310783
%{
@@ -11393,21 +11273,6 @@ instruct xorL_rReg_rReg_mem_ndd(rRegL dst, rRegL src1, memory src2, rFlagsReg cr
1139311273
ins_pipe(ialu_reg_mem);
1139411274
%}
1139511275

11396-
instruct xorL_rReg_mem_rReg_ndd(rRegL dst, memory src1, rRegL src2, rFlagsReg cr)
11397-
%{
11398-
predicate(UseAPX);
11399-
match(Set dst (XorL (LoadL src1) src2));
11400-
effect(KILL cr);
11401-
flag(PD::Flag_sets_sign_flag, PD::Flag_sets_zero_flag, PD::Flag_sets_parity_flag, PD::Flag_clears_overflow_flag, PD::Flag_clears_carry_flag);
11402-
11403-
ins_cost(150);
11404-
format %{ "exorq $dst, $src1, $src2\t# long ndd" %}
11405-
ins_encode %{
11406-
__ exorq($dst$$Register, $src1$$Address, $src2$$Register, false);
11407-
%}
11408-
ins_pipe(ialu_reg_mem);
11409-
%}
11410-
1141111276
// Xor Memory with Register
1141211277
instruct xorL_mem_rReg(memory dst, rRegL src, rFlagsReg cr)
1141311278
%{

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