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8293474: RISC-V: Unify the way of moving function pointer
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Reviewed-by: yadongwang, fjiang, shade
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RealFYang committed Sep 8, 2022
1 parent 2d13f53 commit fc5f97f
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Showing 3 changed files with 21 additions and 29 deletions.
Expand Up @@ -272,7 +272,7 @@ void ShenandoahBarrierSetAssembler::load_reference_barrier(MacroAssembler* masm,

// Test for in-cset
if (is_strong) {
__ li(t1, (uint64_t)ShenandoahHeap::in_cset_fast_test_addr());
__ mv(t1, ShenandoahHeap::in_cset_fast_test_addr());
__ srli(t0, x10, ShenandoahHeapRegion::region_size_bytes_shift_jint());
__ add(t1, t1, t0);
__ lbu(t1, Address(t1));
Expand All @@ -283,20 +283,20 @@ void ShenandoahBarrierSetAssembler::load_reference_barrier(MacroAssembler* masm,
__ push_call_clobbered_registers();
if (is_strong) {
if (is_narrow) {
__ li(ra, (int64_t)(uintptr_t)ShenandoahRuntime::load_reference_barrier_strong_narrow);
__ mv(ra, CAST_FROM_FN_PTR(address, ShenandoahRuntime::load_reference_barrier_strong_narrow));
} else {
__ li(ra, (int64_t)(uintptr_t)ShenandoahRuntime::load_reference_barrier_strong);
__ mv(ra, CAST_FROM_FN_PTR(address, ShenandoahRuntime::load_reference_barrier_strong));
}
} else if (is_weak) {
if (is_narrow) {
__ li(ra, (int64_t)(uintptr_t)ShenandoahRuntime::load_reference_barrier_weak_narrow);
__ mv(ra, CAST_FROM_FN_PTR(address, ShenandoahRuntime::load_reference_barrier_weak_narrow));
} else {
__ li(ra, (int64_t)(uintptr_t)ShenandoahRuntime::load_reference_barrier_weak);
__ mv(ra, CAST_FROM_FN_PTR(address, ShenandoahRuntime::load_reference_barrier_weak));
}
} else {
assert(is_phantom, "only remaining strength");
assert(!is_narrow, "phantom access cannot be narrow");
__ li(ra, (int64_t)(uintptr_t)ShenandoahRuntime::load_reference_barrier_weak);
__ mv(ra, CAST_FROM_FN_PTR(address, ShenandoahRuntime::load_reference_barrier_weak));
}
__ jalr(ra);
__ mv(t0, x10);
Expand Down Expand Up @@ -679,25 +679,25 @@ void ShenandoahBarrierSetAssembler::generate_c1_load_reference_barrier_runtime_s
bool is_native = ShenandoahBarrierSet::is_native_access(decorators);
if (is_strong) {
if (is_native) {
__ li(ra, (int64_t)(uintptr_t)ShenandoahRuntime::load_reference_barrier_strong);
__ mv(ra, CAST_FROM_FN_PTR(address, ShenandoahRuntime::load_reference_barrier_strong));
} else {
if (UseCompressedOops) {
__ li(ra, (int64_t)(uintptr_t)ShenandoahRuntime::load_reference_barrier_strong_narrow);
__ mv(ra, CAST_FROM_FN_PTR(address, ShenandoahRuntime::load_reference_barrier_strong_narrow));
} else {
__ li(ra, (int64_t)(uintptr_t)ShenandoahRuntime::load_reference_barrier_strong);
__ mv(ra, CAST_FROM_FN_PTR(address, ShenandoahRuntime::load_reference_barrier_strong));
}
}
} else if (is_weak) {
assert(!is_native, "weak must not be called off-heap");
if (UseCompressedOops) {
__ li(ra, (int64_t)(uintptr_t)ShenandoahRuntime::load_reference_barrier_weak_narrow);
__ mv(ra, CAST_FROM_FN_PTR(address, ShenandoahRuntime::load_reference_barrier_weak_narrow));
} else {
__ li(ra, (int64_t)(uintptr_t)ShenandoahRuntime::load_reference_barrier_weak);
__ mv(ra, CAST_FROM_FN_PTR(address, ShenandoahRuntime::load_reference_barrier_weak));
}
} else {
assert(is_phantom, "only remaining strength");
assert(is_native, "phantom must only be called off-heap");
__ li(ra, (int64_t)(uintptr_t)ShenandoahRuntime::load_reference_barrier_phantom);
__ mv(ra, CAST_FROM_FN_PTR(address, ShenandoahRuntime::load_reference_barrier_phantom));
}
__ jalr(ra);
__ mv(t0, x10);
Expand Down
19 changes: 6 additions & 13 deletions src/hotspot/cpu/riscv/macroAssembler_riscv.cpp
Expand Up @@ -379,7 +379,7 @@ void MacroAssembler::_verify_oop(Register reg, const char* s, const char* file,
// The length of the instruction sequence emitted should be independent
// of the value of the local char buffer address so that the size of mach
// nodes for scratch emit and normal emit matches.
mv(t0, (address)b);
movptr(t0, (address)b);

// call indirectly to solve generation ordering problem
int32_t offset = 0;
Expand Down Expand Up @@ -418,7 +418,7 @@ void MacroAssembler::_verify_oop_addr(Address addr, const char* s, const char* f
// The length of the instruction sequence emitted should be independent
// of the value of the local char buffer address so that the size of mach
// nodes for scratch emit and normal emit matches.
mv(t0, (address)b);
movptr(t0, (address)b);

// call indirectly to solve generation ordering problem
int32_t offset = 0;
Expand Down Expand Up @@ -1363,12 +1363,6 @@ void MacroAssembler::mv(Register Rd, Address dest) {
movptr(Rd, dest.target());
}

void MacroAssembler::mv(Register Rd, address addr) {
// Here in case of use with relocation, use fix length instruction
// movptr instead of li
movptr(Rd, addr);
}

void MacroAssembler::mv(Register Rd, RegisterOrConstant src) {
if (src.is_register()) {
mv(Rd, src.as_register());
Expand Down Expand Up @@ -2687,11 +2681,10 @@ void MacroAssembler::get_thread(Register thread) {
RegSet::range(x28, x31) + ra - thread;
push_reg(saved_regs, sp);

int32_t offset = 0;
movptr_with_offset(ra, CAST_FROM_FN_PTR(address, Thread::current), offset);
jalr(ra, ra, offset);
if (thread != x10) {
mv(thread, x10);
mv(ra, CAST_FROM_FN_PTR(address, Thread::current));
jalr(ra);
if (thread != c_rarg0) {
mv(thread, c_rarg0);
}

// restore pushed registers
Expand Down
7 changes: 3 additions & 4 deletions src/hotspot/cpu/riscv/macroAssembler_riscv.hpp
Expand Up @@ -513,15 +513,14 @@ class MacroAssembler: public Assembler {
}

// mv
void mv(Register Rd, address addr) { li(Rd, (int64_t)addr); }

template<typename T, ENABLE_IF(std::is_integral<T>::value)>
inline void mv(Register Rd, T o) {
li(Rd, (int64_t)o);
}
inline void mv(Register Rd, T o) { li(Rd, (int64_t)o); }

inline void mvw(Register Rd, int32_t imm32) { mv(Rd, imm32); }

void mv(Register Rd, Address dest);
void mv(Register Rd, address addr);
void mv(Register Rd, RegisterOrConstant src);

// logic
Expand Down

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