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8297235: ZGC: assert(regs[i] != regs[j]) failed: Multiple uses of register: rax #11410
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👋 Welcome back aboldtch! A progress list of the required criteria for merging this PR into |
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/label add hotspot-compiler |
@xmas92 |
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I think that changing memory to indirect in the mach node matching solves the conjoint register problem. The address then becomes a field, and the type of the expected value is an oop. For them to be the same register would be seemingly impossible.
Changed all nodes to |
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Looks good!
@xmas92 This change now passes all automated pre-integration checks. ℹ️ This project also has non-automated pre-integration requirements. Please see the file CONTRIBUTING.md for details. After integration, the commit message for the final commit will be:
You can use pull request commands such as /summary, /contributor and /issue to adjust it as needed. At the time when this comment was updated there had been 57 new commits pushed to the
As there are no conflicts, your changes will automatically be rebased on top of these commits when integrating. If you prefer to avoid this automatic rebasing, please check the documentation for the /integrate command for further details. ➡️ To integrate this PR with the above commit message to the |
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I agree with @fisk's analysis above: the proposed solution should be safe as long as the first CompareAndSwap operand (mem
) has a non-zero offset (which should at least be the case in the failing Unsafe-based patterns): the register allocator will then treat mem
and oldval
as two distinct, interfering values and assign them different registers.
I attached a minimal reproducer to the JBS issue, feel free to include it in this PR as a test case if you think it adds value.
I do not think there is a general way to express the constraint you want in .ad files, but I am not an expert in this area, maybe someone at Intel could comment on this (@sviswa7, @jatin-bhateja?). I also do not have a feeling for what would be the benefit vs. cost of implementing such construct. An alternative approach could be to enforce the constraint at the C2 IR level, by adding some kind of pseudo-node redefining the input to the first CompareAndSwap
operand so that it always interferes with oldval
.
Regarding the impact on other architectures, it seems they all follow the solution proposed here, so they should be as safe as in this case, that is, as long as C2 does not generate a CAS comparing the address of the field with its content. I cannot think how C2 could generate such pattern - which of course is not a guarantee that it will never do it ;).
/integrate |
Going to push as commit 042b706.
Your commit was automatically rebased without conflicts. |
/backport jdk20 |
@xmas92 the backport was successfully created on the branch xmas92-backport-042b7062 in my personal fork of openjdk/jdk20. To create a pull request with this backport targeting openjdk/jdk20:master, just click the following link: The title of the pull request is automatically filled in correctly and below you find a suggestion for the pull request body:
If you need to update the source branch of the pull then run the following commands in a local clone of your personal fork of openjdk/jdk20:
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This PR removed all entries from test/jdk/ProblemList-zgc.txt including this entry: jdk/internal/vm/Continuation/Fuzz.java#default 8298058 generic-x64 which has nothing to do with this bug fix. I'll restore that entry with a new bug shortly. |
Tests java/util/stream/test/org/openjdk/tests/java/util/* with -XX:+UseZGC -Xcomp -XX:-TieredCompilation crashes with
assert(regs[i] != regs[j]) failed: Multiple uses of register: rax
. More specifically compilation of java.util.concurrent.ForkJoinTask::awaitDone.The reason seems to be that the compare value and the memory input ends up sharing a register. (Uses Unsafe CAS which CAS an object reference into a field of that object,
oldval: rax
andmem: [rax+offset]
). The Z load barrier stub dispatch implementation require that the reference and reference address occupy distinct registers. In the loadP nodes this is established by marking all but the memory TEMP which results in no sharing.This is not possible for the CompareAndSwapP / CompareAndExchangeP nodes as the compare value is an input node.
The solution proposed here is less than ideal as it makes the CAS nodes require one extra TEMP register, which in the common case is unused. This puts unnecessary extra strain on the register allocation. The problem is that there is no way currently (that I can find) to express in .ad that a memory input must not share registers with a specific other input.
There is an alternative solution for this specific crash which does not use a second TEMP register (see commit: cfd5ced). It accomplish this by using the same trick that the aarch64 Z CAS node uses which is to specify the memory as indirect which results in the address being LEA into a register. However from what I can see this does not guarantee that the address and the reference does not share a register (
oldval: rax
andmem: [rax]
). So it is theoretically broken, (and so is the aarch64 implementation).It is unclear to me if there is ever a way for C2 to generation a CAS which compares the address of the field with its content.
I call on anyone with more knowledge about
adlc
andC2
for feedback. And specifically I want to open up a discussion with these points:Testing: linux-x64 zgc tagged tests tier 1-7 and some specific crashing tests with
-XX:+UseZGC -Xcomp -XX:-TieredCompilation
(in: java/util/stream/, java/util/concurrent/)Progress
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Update a local copy of the PR:
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