From e7ae82f266d63566dbbdec5d7bb78adb7114cac4 Mon Sep 17 00:00:00 2001 From: Fei Yang Date: Tue, 10 Jan 2023 16:52:05 +0800 Subject: [PATCH 1/4] 8299847: RISC-V: Incorrect branch condition code in PrintOptoAssembly output --- src/hotspot/cpu/riscv/riscv.ad | 67 +++++++++++++++++----------------- 1 file changed, 34 insertions(+), 33 deletions(-) diff --git a/src/hotspot/cpu/riscv/riscv.ad b/src/hotspot/cpu/riscv/riscv.ad index 735fbaa5d86dc..3f0ab95634d24 100644 --- a/src/hotspot/cpu/riscv/riscv.ad +++ b/src/hotspot/cpu/riscv/riscv.ad @@ -940,7 +940,7 @@ definitions %{ int_def LOAD_COST ( 300, 3 * DEFAULT_COST); // load, fpload int_def STORE_COST ( 100, 1 * DEFAULT_COST); // store, fpstore int_def XFER_COST ( 300, 3 * DEFAULT_COST); // mfc, mtc, fcvt, fmove, fcmp - int_def BRANCH_COST ( 100, 1 * DEFAULT_COST); // branch, jmp, call + int_def BRANCH_COST ( 200, 2 * DEFAULT_COST); // branch, jmp, call int_def IMUL_COST ( 1000, 10 * DEFAULT_COST); // imul int_def IDIVSI_COST ( 3400, 34 * DEFAULT_COST); // idivdi int_def IDIVDI_COST ( 6600, 66 * DEFAULT_COST); // idivsi @@ -3817,13 +3817,13 @@ operand cmpOpULtGe() format %{ "" %} interface(COND_INTER) %{ equal(0x0, "eq"); - greater(0x1, "gt"); + greater(0x1, "gtu"); overflow(0x2, "overflow"); - less(0x3, "lt"); + less(0x3, "ltu"); not_equal(0x4, "ne"); - less_equal(0x5, "le"); + less_equal(0x5, "leu"); no_overflow(0x6, "no_overflow"); - greater_equal(0x7, "ge"); + greater_equal(0x7, "geu"); %} %} @@ -3839,13 +3839,13 @@ operand cmpOpUEqNeLeGt() format %{ "" %} interface(COND_INTER) %{ equal(0x0, "eq"); - greater(0x1, "gt"); + greater(0x1, "gtu"); overflow(0x2, "overflow"); - less(0x3, "lt"); + less(0x3, "ltu"); not_equal(0x4, "ne"); - less_equal(0x5, "le"); + less_equal(0x5, "leu"); no_overflow(0x6, "no_overflow"); - greater_equal(0x7, "ge"); + greater_equal(0x7, "geu"); %} %} @@ -9888,10 +9888,10 @@ instruct cmovI_cmpI(iRegINoSp dst, iRegI src, iRegI op1, iRegI op2, cmpOp cop) % ins_cost(ALU_COST + BRANCH_COST); format %{ - "bneg$cop $op1, $op2, skip\t#@cmovI_cmpI\n\t" - "mv $dst, $src\n\t" - "skip:" - %} + "b$cop $op1, $op2, skip\t#@cmovI_cmpI\n\t" + "mv $dst, $src\n\t" + "skip:" + %} ins_encode %{ __ enc_cmove($cop$$cmpcode, @@ -9907,10 +9907,10 @@ instruct cmovI_cmpU(iRegINoSp dst, iRegI src, iRegI op1, iRegI op2, cmpOpU cop) ins_cost(ALU_COST + BRANCH_COST); format %{ - "bneg$cop $op1, $op2, skip\t#@cmovI_cmpU\n\t" - "mv $dst, $src\n\t" - "skip:" - %} + "b$cop $op1, $op2, skip\t#@cmovI_cmpU\n\t" + "mv $dst, $src\n\t" + "skip:" + %} ins_encode %{ __ enc_cmove($cop$$cmpcode | C2_MacroAssembler::unsigned_branch_mask, @@ -9926,10 +9926,10 @@ instruct cmovI_cmpL(iRegINoSp dst, iRegI src, iRegL op1, iRegL op2, cmpOp cop) % ins_cost(ALU_COST + BRANCH_COST); format %{ - "bneg$cop $op1, $op2, skip\t#@cmovI_cmpL\n\t" - "mv $dst, $src\n\t" - "skip:" - %} + "b$cop $op1, $op2, skip\t#@cmovI_cmpL\n\t" + "mv $dst, $src\n\t" + "skip:" + %} ins_encode %{ __ enc_cmove($cop$$cmpcode, @@ -9945,10 +9945,10 @@ instruct cmovL_cmpL(iRegLNoSp dst, iRegL src, iRegL op1, iRegL op2, cmpOp cop) % ins_cost(ALU_COST + BRANCH_COST); format %{ - "bneg$cop $op1, $op2, skip\t#@cmovL_cmpL\n\t" - "mv $dst, $src\n\t" - "skip:" - %} + "b$cop $op1, $op2, skip\t#@cmovL_cmpL\n\t" + "mv $dst, $src\n\t" + "skip:" + %} ins_encode %{ __ enc_cmove($cop$$cmpcode, @@ -9964,10 +9964,10 @@ instruct cmovL_cmpUL(iRegLNoSp dst, iRegL src, iRegL op1, iRegL op2, cmpOpU cop) ins_cost(ALU_COST + BRANCH_COST); format %{ - "bneg$cop $op1, $op2, skip\t#@cmovL_cmpUL\n\t" - "mv $dst, $src\n\t" - "skip:" - %} + "b$cop $op1, $op2, skip\t#@cmovL_cmpUL\n\t" + "mv $dst, $src\n\t" + "skip:" + %} ins_encode %{ __ enc_cmove($cop$$cmpcode | C2_MacroAssembler::unsigned_branch_mask, @@ -9981,11 +9981,12 @@ instruct cmovL_cmpUL(iRegLNoSp dst, iRegL src, iRegL op1, iRegL op2, cmpOpU cop) instruct cmovI_cmpUL(iRegINoSp dst, iRegI src, iRegL op1, iRegL op2, cmpOpU cop) %{ match(Set dst (CMoveI (Binary cop (CmpUL op1 op2)) (Binary dst src))); ins_cost(ALU_COST + BRANCH_COST); + format %{ - "bneg$cop $op1, $op2\t#@cmovI_cmpUL\n\t" - "mv $dst, $src\n\t" - "skip:" - %} + "b$cop $op1, $op2, skip\t#@cmovI_cmpUL\n\t" + "mv $dst, $src\n\t" + "skip:" + %} ins_encode %{ __ enc_cmove($cop$$cmpcode | C2_MacroAssembler::unsigned_branch_mask, From f28dbcbd4e7d16ba3d90d9776fa167e6373a4015 Mon Sep 17 00:00:00 2001 From: Fei Yang Date: Tue, 10 Jan 2023 21:32:49 +0800 Subject: [PATCH 2/4] Fix --- src/hotspot/cpu/riscv/riscv.ad | 24 ++++++------------------ 1 file changed, 6 insertions(+), 18 deletions(-) diff --git a/src/hotspot/cpu/riscv/riscv.ad b/src/hotspot/cpu/riscv/riscv.ad index 3f0ab95634d24..cb4ffcf4f1d89 100644 --- a/src/hotspot/cpu/riscv/riscv.ad +++ b/src/hotspot/cpu/riscv/riscv.ad @@ -9888,9 +9888,7 @@ instruct cmovI_cmpI(iRegINoSp dst, iRegI src, iRegI op1, iRegI op2, cmpOp cop) % ins_cost(ALU_COST + BRANCH_COST); format %{ - "b$cop $op1, $op2, skip\t#@cmovI_cmpI\n\t" - "mv $dst, $src\n\t" - "skip:" + "CMove $dst, ($op1 $cop $op2), $dst, $src\t#@cmovI_cmpI\n\t" %} ins_encode %{ @@ -9907,9 +9905,7 @@ instruct cmovI_cmpU(iRegINoSp dst, iRegI src, iRegI op1, iRegI op2, cmpOpU cop) ins_cost(ALU_COST + BRANCH_COST); format %{ - "b$cop $op1, $op2, skip\t#@cmovI_cmpU\n\t" - "mv $dst, $src\n\t" - "skip:" + "CMove $dst, ($op1 $cop $op2), $dst, $src\t#@cmovI_cmpU\n\t" %} ins_encode %{ @@ -9926,9 +9922,7 @@ instruct cmovI_cmpL(iRegINoSp dst, iRegI src, iRegL op1, iRegL op2, cmpOp cop) % ins_cost(ALU_COST + BRANCH_COST); format %{ - "b$cop $op1, $op2, skip\t#@cmovI_cmpL\n\t" - "mv $dst, $src\n\t" - "skip:" + "CMove $dst, ($op1 $cop $op2), $dst, $src\t#@cmovI_cmpL\n\t" %} ins_encode %{ @@ -9945,9 +9939,7 @@ instruct cmovL_cmpL(iRegLNoSp dst, iRegL src, iRegL op1, iRegL op2, cmpOp cop) % ins_cost(ALU_COST + BRANCH_COST); format %{ - "b$cop $op1, $op2, skip\t#@cmovL_cmpL\n\t" - "mv $dst, $src\n\t" - "skip:" + "CMove $dst, ($op1 $cop $op2), $dst, $src\t#@cmovL_cmpL\n\t" %} ins_encode %{ @@ -9964,9 +9956,7 @@ instruct cmovL_cmpUL(iRegLNoSp dst, iRegL src, iRegL op1, iRegL op2, cmpOpU cop) ins_cost(ALU_COST + BRANCH_COST); format %{ - "b$cop $op1, $op2, skip\t#@cmovL_cmpUL\n\t" - "mv $dst, $src\n\t" - "skip:" + "CMove $dst, ($op1 $cop $op2), $dst, $src\t#@cmovL_cmpUL\n\t" %} ins_encode %{ @@ -9983,9 +9973,7 @@ instruct cmovI_cmpUL(iRegINoSp dst, iRegI src, iRegL op1, iRegL op2, cmpOpU cop) ins_cost(ALU_COST + BRANCH_COST); format %{ - "b$cop $op1, $op2, skip\t#@cmovI_cmpUL\n\t" - "mv $dst, $src\n\t" - "skip:" + "CMove $dst, ($op1 $cop $op2), $dst, $src\t#@cmovI_cmpUL\n\t" %} ins_encode %{ From 8e4b4c593a1623e83741f041c6be08373475037c Mon Sep 17 00:00:00 2001 From: Fei Yang Date: Fri, 13 Jan 2023 12:54:39 +0800 Subject: [PATCH 3/4] Fix --- src/hotspot/cpu/riscv/riscv.ad | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) diff --git a/src/hotspot/cpu/riscv/riscv.ad b/src/hotspot/cpu/riscv/riscv.ad index cb4ffcf4f1d89..407ac043b79b4 100644 --- a/src/hotspot/cpu/riscv/riscv.ad +++ b/src/hotspot/cpu/riscv/riscv.ad @@ -9897,7 +9897,7 @@ instruct cmovI_cmpI(iRegINoSp dst, iRegI src, iRegI op1, iRegI op2, cmpOp cop) % as_Register($dst$$reg), as_Register($src$$reg)); %} - ins_pipe(pipe_slow); + ins_pipe(pipe_class_default); %} instruct cmovI_cmpU(iRegINoSp dst, iRegI src, iRegI op1, iRegI op2, cmpOpU cop) %{ @@ -9914,7 +9914,7 @@ instruct cmovI_cmpU(iRegINoSp dst, iRegI src, iRegI op1, iRegI op2, cmpOpU cop) as_Register($dst$$reg), as_Register($src$$reg)); %} - ins_pipe(pipe_slow); + ins_pipe(pipe_class_default); %} instruct cmovI_cmpL(iRegINoSp dst, iRegI src, iRegL op1, iRegL op2, cmpOp cop) %{ @@ -9931,7 +9931,7 @@ instruct cmovI_cmpL(iRegINoSp dst, iRegI src, iRegL op1, iRegL op2, cmpOp cop) % as_Register($dst$$reg), as_Register($src$$reg)); %} - ins_pipe(pipe_slow); + ins_pipe(pipe_class_default); %} instruct cmovL_cmpL(iRegLNoSp dst, iRegL src, iRegL op1, iRegL op2, cmpOp cop) %{ @@ -9948,7 +9948,7 @@ instruct cmovL_cmpL(iRegLNoSp dst, iRegL src, iRegL op1, iRegL op2, cmpOp cop) % as_Register($dst$$reg), as_Register($src$$reg)); %} - ins_pipe(pipe_slow); + ins_pipe(pipe_class_default); %} instruct cmovL_cmpUL(iRegLNoSp dst, iRegL src, iRegL op1, iRegL op2, cmpOpU cop) %{ @@ -9965,7 +9965,7 @@ instruct cmovL_cmpUL(iRegLNoSp dst, iRegL src, iRegL op1, iRegL op2, cmpOpU cop) as_Register($dst$$reg), as_Register($src$$reg)); %} - ins_pipe(pipe_slow); + ins_pipe(pipe_class_default); %} instruct cmovI_cmpUL(iRegINoSp dst, iRegI src, iRegL op1, iRegL op2, cmpOpU cop) %{ @@ -9982,7 +9982,7 @@ instruct cmovI_cmpUL(iRegINoSp dst, iRegI src, iRegL op1, iRegL op2, cmpOpU cop) as_Register($dst$$reg), as_Register($src$$reg)); %} - ins_pipe(pipe_slow); + ins_pipe(pipe_class_default); %} From 08318af8584b3553bdce3be63c139088f0fc24cb Mon Sep 17 00:00:00 2001 From: Fei Yang Date: Mon, 16 Jan 2023 20:56:34 +0800 Subject: [PATCH 4/4] Comment --- src/hotspot/cpu/riscv/riscv.ad | 14 +++++++------- 1 file changed, 7 insertions(+), 7 deletions(-) diff --git a/src/hotspot/cpu/riscv/riscv.ad b/src/hotspot/cpu/riscv/riscv.ad index b5c2bb3238a0b..c8c581eb6718d 100644 --- a/src/hotspot/cpu/riscv/riscv.ad +++ b/src/hotspot/cpu/riscv/riscv.ad @@ -4373,7 +4373,7 @@ pipe_class istore_reg_reg(iRegI dst, iRegI src) LDST : MEM; %} -//------- Store pipeline operations ----------------------- +//------- Control transfer pipeline operations ------------ // Branch pipe_class pipe_branch() @@ -9899,7 +9899,7 @@ instruct cmovI_cmpI(iRegINoSp dst, iRegI src, iRegI op1, iRegI op2, cmpOp cop) % as_Register($dst$$reg), as_Register($src$$reg)); %} - ins_pipe(pipe_class_default); + ins_pipe(pipe_class_compare); %} instruct cmovI_cmpU(iRegINoSp dst, iRegI src, iRegI op1, iRegI op2, cmpOpU cop) %{ @@ -9916,7 +9916,7 @@ instruct cmovI_cmpU(iRegINoSp dst, iRegI src, iRegI op1, iRegI op2, cmpOpU cop) as_Register($dst$$reg), as_Register($src$$reg)); %} - ins_pipe(pipe_class_default); + ins_pipe(pipe_class_compare); %} instruct cmovI_cmpL(iRegINoSp dst, iRegI src, iRegL op1, iRegL op2, cmpOp cop) %{ @@ -9933,7 +9933,7 @@ instruct cmovI_cmpL(iRegINoSp dst, iRegI src, iRegL op1, iRegL op2, cmpOp cop) % as_Register($dst$$reg), as_Register($src$$reg)); %} - ins_pipe(pipe_class_default); + ins_pipe(pipe_class_compare); %} instruct cmovL_cmpL(iRegLNoSp dst, iRegL src, iRegL op1, iRegL op2, cmpOp cop) %{ @@ -9950,7 +9950,7 @@ instruct cmovL_cmpL(iRegLNoSp dst, iRegL src, iRegL op1, iRegL op2, cmpOp cop) % as_Register($dst$$reg), as_Register($src$$reg)); %} - ins_pipe(pipe_class_default); + ins_pipe(pipe_class_compare); %} instruct cmovL_cmpUL(iRegLNoSp dst, iRegL src, iRegL op1, iRegL op2, cmpOpU cop) %{ @@ -9967,7 +9967,7 @@ instruct cmovL_cmpUL(iRegLNoSp dst, iRegL src, iRegL op1, iRegL op2, cmpOpU cop) as_Register($dst$$reg), as_Register($src$$reg)); %} - ins_pipe(pipe_class_default); + ins_pipe(pipe_class_compare); %} instruct cmovI_cmpUL(iRegINoSp dst, iRegI src, iRegL op1, iRegL op2, cmpOpU cop) %{ @@ -9984,7 +9984,7 @@ instruct cmovI_cmpUL(iRegINoSp dst, iRegI src, iRegL op1, iRegL op2, cmpOpU cop) as_Register($dst$$reg), as_Register($src$$reg)); %} - ins_pipe(pipe_class_default); + ins_pipe(pipe_class_compare); %}