From c7c18f15fcad20c8b0cd8f167bfaba68c75fa060 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Erik=20=C3=96sterlund?= Date: Mon, 30 Jan 2023 17:19:07 +0000 Subject: [PATCH] 8301371: Interpreter store barriers on x86_64 don't have disjoint temp registers --- src/hotspot/cpu/x86/templateTable_x86.cpp | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/src/hotspot/cpu/x86/templateTable_x86.cpp b/src/hotspot/cpu/x86/templateTable_x86.cpp index 0281522c0e2c9..4961ec22ae2df 100644 --- a/src/hotspot/cpu/x86/templateTable_x86.cpp +++ b/src/hotspot/cpu/x86/templateTable_x86.cpp @@ -152,7 +152,10 @@ static void do_oop_store(InterpreterMacroAssembler* _masm, Register val, DecoratorSet decorators = 0) { assert(val == noreg || val == rax, "parameter is just for looks"); - __ store_heap_oop(dst, val, rdx, rbx, LP64_ONLY(r8) NOT_LP64(rsi), decorators); + __ store_heap_oop(dst, val, + NOT_LP64(rdx) LP64_ONLY(rscratch2), + NOT_LP64(rbx) LP64_ONLY(r9), + NOT_LP64(rsi) LP64_ONLY(r8), decorators); } static void do_oop_load(InterpreterMacroAssembler* _masm,