8305728: RISC-V: Use bexti instruction to do single-bit testing#13368
8305728: RISC-V: Use bexti instruction to do single-bit testing#13368feilongjiang wants to merge 1 commit intoopenjdk:masterfrom
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👋 Welcome back fjiang! A progress list of the required criteria for merging this PR into |
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/label remove shenandoah |
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/label remove hotspot |
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@feilongjiang This change now passes all automated pre-integration checks. ℹ️ This project also has non-automated pre-integration requirements. Please see the file CONTRIBUTING.md for details. After integration, the commit message for the final commit will be: You can use pull request commands such as /summary, /contributor and /issue to adjust it as needed. At the time when this comment was updated there had been 30 new commits pushed to the
As there are no conflicts, your changes will automatically be rebased on top of these commits when integrating. If you prefer to avoid this automatic rebasing, please check the documentation for the /integrate command for further details. As you do not have Committer status in this project an existing Committer must agree to sponsor your change. Possible candidates are the reviewers of this PR (@RealFYang) but any other Committer may sponsor as well. ➡️ To flag this PR as ready for integration with the above commit message, type |
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hotspot/jdk tier2-3 are also good w/ |
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@feilongjiang |
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/sponsor |
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Going to push as commit 1375130.
Your commit was automatically rebased without conflicts. |
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@RealFYang @feilongjiang Pushed as commit 1375130. 💡 You may see a message that your pull request was closed with unmerged commits. This can be safely ignored. |
Current RISC-V port tests bit masks with
andiinstruction. But for those mask values not in the range ofsimm12(andionly accepts sign-extended 12-bit immediate [1]), we need an extra temp register (
t0as default forandi) to store the mask value [2].Since we now support Zbs extension of Bit-Manipulation, we have a more convenient way to test power-of-two bit
masks with the single instruction
bexti[3] without any temp register.jdk/src/hotspot/cpu/riscv/macroAssembler_riscv.cpp
Lines 1852 to 1860 in ce6e746
Testing:
hotspot_tier1,jdk_tier1on QEMU-User w/ and w/oUseZbs(release build)UseZbs(release build)Progress
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gitCheckout this PR locally:
$ git fetch https://git.openjdk.org/jdk.git pull/13368/head:pull/13368$ git checkout pull/13368Update a local copy of the PR:
$ git checkout pull/13368$ git pull https://git.openjdk.org/jdk.git pull/13368/headUsing Skara CLI tools
Checkout this PR locally:
$ git pr checkout 13368View PR using the GUI difftool:
$ git pr show -t 13368Using diff file
Download this PR as a diff file:
https://git.openjdk.org/jdk/pull/13368.diff
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