From 39e1a67de9ce49381083820508b2015d546f9771 Mon Sep 17 00:00:00 2001
From: jiangfeilong <jiangfeilong@huawei.com>
Date: Mon, 1 May 2023 12:10:57 +0800
Subject: [PATCH] RISC-V: Remove remaining StoreLoad barrier with
 UseCondCardMark for Serial/Parallel GC

---
 .../cpu/riscv/gc/shared/cardTableBarrierSetAssembler_riscv.cpp   | 1 -
 1 file changed, 1 deletion(-)

diff --git a/src/hotspot/cpu/riscv/gc/shared/cardTableBarrierSetAssembler_riscv.cpp b/src/hotspot/cpu/riscv/gc/shared/cardTableBarrierSetAssembler_riscv.cpp
index 070ec8e6338dd..2ad44400687f2 100644
--- a/src/hotspot/cpu/riscv/gc/shared/cardTableBarrierSetAssembler_riscv.cpp
+++ b/src/hotspot/cpu/riscv/gc/shared/cardTableBarrierSetAssembler_riscv.cpp
@@ -49,7 +49,6 @@ void CardTableBarrierSetAssembler::store_check(MacroAssembler* masm, Register ob
 
   if (UseCondCardMark) {
     Label L_already_dirty;
-    __ membar(MacroAssembler::StoreLoad);
     __ lbu(t1,  Address(tmp));
     __ beqz(t1, L_already_dirty);
     __ sb(zr, Address(tmp));