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8310949: RISC-V: Initialize UseUnalignedAccesses #14676

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luhenry
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@luhenry luhenry commented Jun 27, 2023


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  • JDK-8310949: RISC-V: Initialize UseUnalignedAccesses (Enhancement - P4)

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@luhenry luhenry force-pushed the dev/ludovic/initialize-useunalignedaccesses branch from bd44845 to 9384cb4 Compare June 27, 2023 13:12
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@luhenry Please do not rebase or force-push to an active PR as it invalidates existing review comments. Note for future reference, the bots always squash all changes into a single commit automatically as part of the integration. See OpenJDK Developers’ Guide for more information.

@openjdk openjdk bot removed the rfr Pull request is ready for review label Jun 27, 2023
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Looks good to me!

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@luhenry This change now passes all automated pre-integration checks.

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After integration, the commit message for the final commit will be:

8310949: RISC-V: Initialize UseUnalignedAccesses

Reviewed-by: rehn, vkempik, fyang

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RealFYang commented Jun 28, 2023

We will need some performance numbers to validate this change. We witnessed some obvious regressions of Unsafe.Put*Unaligned methods when enabling UseUnalignedAccesses on some platforms like HiFive Unmatched with slow unaligned accesses. My guess is that we might want enable UseUnalignedAccesses for platforms like T-Head with fast unaligned accesses (RISCV_HWPROBE_MISALIGNED_FAST). But that will still depend on the measured JMH numbers.

PS: JMH test for reference: https://cr.openjdk.org/~dzhang/TestUseUnalignedAccesses/

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luhenry commented Jun 28, 2023

@RealFYang the issue I see with UseUnalignedAccesses is that there are two ways to interpret it:

  1. unaligned accesses are supported
  2. unaligned accesses are fast

The benchmark you're using tend towards "unaligned accesses are fast". However, I don't necessarily agree that it is what this UseUnalignedAccesses means as I would verge more towards "unaligned accesses are supported". Some applications out there will fail if java.nio.Bits.unaligned() returns false (some Apache projects for example), and that property is set from Unsafe.unalignedAccess() which itself is set with UseUnalignedAccesses.

The core of the issue is that x86 does support unaligned accesses out-of-the-box, so many applications and frameworks have taken the assumption that it holds true, and that not holding true is unexpected / an exception.

@theRealAph @shipilev is it something you've run into on AArch64 as well?

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shipilev commented Jun 28, 2023

The unaligned accesses paths were originally introduced to support faster word-sized accesses, where possible: https://bugs.openjdk.org/browse/JDK-8026049. So UseUnalignedAccesses means "unaligned accesses are supported and faster than groups of byte-sized accesses". If this is not true on some RISC-V implementations, we should not enable +UseUnalignedAccesses there, I think.

It would not be unusual to default to +UseUnalignedAccesses, and then make a few exceptions for known-slow platforms. Assuming we can sense them, of course. See how x86 code sometimes excepts configurations based on CPU family or microarchitecture.

Edit: I am seeing here https://cr.openjdk.org/~dzhang/TestUseUnalignedAccesses/TestUseUnalignedAccesses_result.txt -- that on Unmatched, we have 30x..40x regression with +UseUnalignedAccesses, wow. That looks like a showstopper!

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Hey, there is a block before this in the same file:

 if (FLAG_IS_DEFAULT(AvoidUnalignedAccesses)) {
    if (unaligned_access.value() != MISALIGNED_FAST) {
      FLAG_SET_DEFAULT(AvoidUnalignedAccesses, true);
    } else {
      FLAG_SET_DEFAULT(AvoidUnalignedAccesses, false);
    }
}

...which needs to be reconciled with this one? At very least, it shows that it is possible to sense MISALIGNED_FAST.

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luhenry commented Jun 28, 2023

@shipilev sounds good! Let's only enable UseUnalignedAccesses on platform that support fast unaligned accesses. We should use unaligned_access.value() == MISALIGNED_FAST to set it up IMO.

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Yes, that would be my suggestion. But @RealFYang's point still stands: we would still need to confirm that actually works well on Unmatched and other known RISC-V boards.

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Yes, that would be my suggestion. But @RealFYang's point still stands: we would still need to confirm that actually works well on Unmatched and other known RISC-V boards.

unmatched has misaligned emulator and slow
thead c910 core has fast misaligned access but it's stuck on linux 5.10 from vendor which don't have new hw_prober syscall

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Yes, that would be my suggestion. But @RealFYang's point still stands: we would still need to confirm that actually works well on Unmatched and other known RISC-V boards.

unmatched has misaligned emulator and slow thead c910 core has fast misaligned access but it's stuck on linux 5.10 from vendor which don't have new hw_prober syscall

Is there a board/image that has the hw_prober implemented, and it returns MISALIGNED_FAST there?

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VladimirKempik commented Jun 28, 2023

Yes, that would be my suggestion. But @RealFYang's point still stands: we would still need to confirm that actually works well on Unmatched and other known RISC-V boards.

unmatched has misaligned emulator and slow thead c910 core has fast misaligned access but it's stuck on linux 5.10 from vendor which don't have new hw_prober syscall

Is there a board/image that has the hw_prober implemented, and it returns MISALIGNED_FAST there?

Doubt so, my fpga board with custom scr cores ( both with misaligned_emu and misglined_fast) might get kernel 6.4 ( with hw_prober) later this summer.

Thead-c910 core is not friendly when one needs to identify it, cpuinfo only has this:

processor	: 0
hart		: 0
isa		: rv64imafdcsu
mmu		: sv39
cpu-freq	: 1.2Ghz
cpu-icache	: 64KB
cpu-dcache	: 64KB
cpu-l2cache	: 2MB
cpu-tlb		: 1024 4-ways
cpu-cacheline	: 64Bytes
cpu-vector	: 0.7.1

so basically c910 is left with the need to manually disable AvoidUnalignedAccesses

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One case to consider:
lets say I have a system with X big cores ( which support MISALIGNED_FAST) and X small cores ( with MISALIGNED_EMU)

if I run some java workload on all cores, what should hw_prober return ? obvious result here is to use +AvoidUnallignedAccesses.

If I run same java workload but use taskset to run it only on big cores, how will jdk's hw_prober code work ? should it work properly and disable AvoidUnallignedAccesses or it's too much and one need to manually set -XX:-AvoidUnallignedAccesses ?

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robehn commented Jun 28, 2023

One case to consider: lets say I have a system with X big cores ( which support MISALIGNED_FAST) and X small cores ( with MISALIGNED_EMU)

if I run some java workload on all cores, what should hw_prober return ? obvious result here is to use +AvoidUnallignedAccesses.

If I run same java workload but use taskset to run it only on big cores, how will jdk's hw_prober code work ? should it work properly and disable AvoidUnallignedAccesses or it's too much and one need to manually set -XX:-AvoidUnallignedAccesses ?

FYI:
The only way today using hwprobe in example above is to query each cpu individually to find the cpu set that have fast and the cpu set have emulated. (or vector or any other extension which may differ)
I have proposed that hwprobe should be able to also return a cpu set for some set of features.
To either inform user of what affinity they should use, or if we want change the affinity of the VM automagically.

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palmer-dabbelt commented Jun 28, 2023

One case to consider: lets say I have a system with X big cores ( which support MISALIGNED_FAST) and X small cores ( with MISALIGNED_EMU)
if I run some java workload on all cores, what should hw_prober return ? obvious result here is to use +AvoidUnallignedAccesses.
If I run same java workload but use taskset to run it only on big cores, how will jdk's hw_prober code work ? should it work properly and disable AvoidUnallignedAccesses or it's too much and one need to manually set -XX:-AvoidUnallignedAccesses ?

FYI: The only way today using hwprobe in example above is to query each cpu individually to find the cpu set that have fast and the cpu set have emulated. (or vector or any other extension which may differ) I have proposed that hwprobe should be able to also return a cpu set for some set of features. To either inform user of what affinity they should use, or if we want change the affinity of the VM automagically.

I think Robbin brought this up at some meeting type thing, but IMO that's a pretty reasonable ask. We hadn't thought of it when writing the syscall, but we've got some flags for extensibility so I think we could make it work.

Another option might be to tie this to some hueristics in userspace, maybe probing along the CPU topology or something. There's been some vague discussions about having a hwprobe userspace library to handle things like bit->string mappings, maybe we should just have it do this too?

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Hello @palmer-dabbelt, I meant I don't know how this thing should work "properly" when we have cpus with different capabilities (regarding misaligned access) and affinity manually set to misaligned_fast cores.

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Hello @palmer-dabbelt, I meant I don't know how this thing should work "properly" when we have cpus with different capabilities (regarding misaligned access) and affinity manually set to misaligned_fast cores.

Sorry, I'm kind of lost here. There's some kernel docs for how riscv_hwprobe() works, it's got a CPU set argument to control which cores are being probed. That argument is meant to line up with how the other scheduling controls work, so it's semi-transparent when userspace doesn't care that much.

I guess I'd need to go read the docs, but we might have a grey area for the misaligned access speed: if we say it's slow, is that slow on one core or slow on all cores. For the other features it's for all cores, but not sure if we were explicit enough in the docs for the performance stuff. Probably worth a read of the docs to see if we can improve them, this is all pretty new so I wouldn't be surprised if that's the case.

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luhenry commented Jul 6, 2023

@VladimirKempik the riscv_hwprobe is going to return the intersection of the features supported by all cores. In the case of a big.LITTLE set of cores, if the LITTLE cores don't support fast unaligned accesses, then riscv_hwprobe will return SLOW or UNSUPPORTED and UseUnalignedAccesses will then be false.

That keeps us in the safer case where we will not generate unaligned accesses if we are not guaranteed that all cores support fast unaligned accesses.

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@VladimirKempik the riscv_hwprobe is going to return the intersection of the features supported by all cores. In the case of a big.LITTLE set of cores, if the LITTLE cores don't support fast unaligned accesses, then riscv_hwprobe will return SLOW or UNSUPPORTED and UseUnalignedAccesses will then be false.

That keeps us in the safer case where we will not generate unaligned accesses if we are not guaranteed that all cores support fast unaligned accesses.

Hello Ludovic, that sounds good, thanks.

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luhenry commented Jul 13, 2023

@robehn @VladimirKempik @RealFYang could I please get another review? Thanks!

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RealFYang commented Jul 13, 2023

Hello, could you please provide some JMH numbers on platforms like T-Head? (-XX:+UseUnalignedAccesses vs -XX:-UseUnalignedAccesses)? I haven't seen such numbers yet. We only tested on Unmatched before: https://cr.openjdk.org/~dzhang/TestUseUnalignedAccesses/

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VladimirKempik commented Jul 13, 2023

Can we deduct UseUnalignedAccesses based on the value of AvoidUnalignedAccess or vice-versa?, We currently have two flags which is confusing.

But maybe we need to get rid of AvoidUnaligned flag at all and replace its usage by UseUnalignedAccesses in a separate PR

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Results on T-Head board
-XX:-UseUnalignedAccesses :

Benchmark                                       (size)   Mode  Cnt     Score   Error   Units
TestUseUnalignedAccesses.testPutIntUnaligned       100  thrpt   15  1907.338 ± 6.943  ops/ms
TestUseUnalignedAccesses.testPutLongUnaligned      100  thrpt   15  1200.164 ± 2.577  ops/ms
TestUseUnalignedAccesses.testPutShortUnaligned     100  thrpt   15  2005.762 ± 8.693  ops/ms

XX:+UseUnalignedAccesses:

Benchmark                                       (size)   Mode  Cnt     Score    Error   Units
TestUseUnalignedAccesses.testPutIntUnaligned       100  thrpt   15  2997.842 ± 11.228  ops/ms
TestUseUnalignedAccesses.testPutLongUnaligned      100  thrpt   15  3058.505 ± 11.970  ops/ms
TestUseUnalignedAccesses.testPutShortUnaligned     100  thrpt   15  3157.681 ± 39.818  ops/ms

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luhenry commented Jul 14, 2023

@RealFYang I expect the T-Head to return that it supports fast unaligned memory accesses, as that's clearly the case.

@VladimirKempik agreed that 1 flag could be used instead of 2. However, these 2 flags are there on all other platforms already. I would then do a follow-up change to merge them across all platforms and not just RISC-V.

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@RealFYang I expect the T-Head to return that it supports fast unaligned memory accesses, as that's clearly the case.

Don't expect thead to be equipped with 6.4+ kernel any time soon

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luhenry commented Jul 14, 2023

Don't expect thead to be equipped with 6.4+ kernel any time soon

Absolutely, and until that's the case, the behaviour stays the same as it currently is, so no regressions.

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luhenry commented Jul 15, 2023

/integrate

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openjdk bot commented Jul 15, 2023

Going to push as commit e8f66bf.
Since your change was applied there have been 187 commits pushed to the master branch:

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