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8311862: RISC-V: small improvements to shift immediate instructions #14823
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👋 Welcome back Ilyagavrilin! A progress list of the required criteria for merging this PR into |
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LGTM
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Looks good, with one nit:
if (UseZba) { | ||
_slli_uw(Rd, Rs, shamt); | ||
} else { | ||
slli(Rd, Rs, shamt+32); |
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slli(Rd, Rs, shamt+32); | |
slli(Rd, Rs, shamt + 32); |
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Thank you for your suggestion
_slli_uw(Rd, Rs, shamt); | ||
} else { | ||
slli(Rd, Rs, shamt + 32); | ||
srli(Rd, Rd, 32); |
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I don't think this code in else block will work in the case when shamt
>= 32. Note that the slli.uw
instruction is the same as slli
with zext.w
performed on the least-significant word of Rs
before shifting. So you might want to do a combination of 32-bit zero extension and slli
on Rs
instead.
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slli.uw with shamt >= 32 will be same as add Rd, X0, X0
, isn't it ?
He can just add handling for that special case then
that was wrong.
PS: I think we should also change the JBS title as I see this not only touches |
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Two nits remain. Looks good otherwise.
if (shamt != 0) { \ | ||
_slli(Rd, Rs1, shamt); \ | ||
} else { \ | ||
if(Rd != Rs1) { \ |
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Nit: s/if(Rd != Rs1) {/if (Rd != Rs1) {/
if (shamt != 0) { \ | ||
NORMAL_NAME(Rd, Rs1, shamt); \ | ||
} else { \ | ||
if(Rd != Rs1) { \ |
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Nit: s/if(Rd != Rs1) {/if (Rd != Rs1) {/
@Ilyagavrilin This change now passes all automated pre-integration checks. ℹ️ This project also has non-automated pre-integration requirements. Please see the file CONTRIBUTING.md for details. After integration, the commit message for the final commit will be:
You can use pull request commands such as /summary, /contributor and /issue to adjust it as needed. At the time when this comment was updated there had been 49 new commits pushed to the
As there are no conflicts, your changes will automatically be rebased on top of these commits when integrating. If you prefer to avoid this automatic rebasing, please check the documentation for the /integrate command for further details. As you do not have Committer status in this project an existing Committer must agree to sponsor your change. Possible candidates are the reviewers of this PR (@luhenry, @RealFYang) but any other Committer may sponsor as well. ➡️ To flag this PR as ready for integration with the above commit message, type |
/integrate |
@Ilyagavrilin |
/sponsor |
Going to push as commit f3b96f6.
Your commit was automatically rebased without conflicts. |
@VladimirKempik @Ilyagavrilin Pushed as commit f3b96f6. 💡 You may see a message that your pull request was closed with unmerged commits. This can be safely ignored. |
/backport jdk21u |
/backport jdk17u-dev |
@Ilyagavrilin To use the |
@Ilyagavrilin To use the |
Please review this small change for slli srli and srai
slli change allows to replace slli Rd, Rs, 0 with addi Rd, Rs, 0 (and no operation emited if Rd == Rs)
addi with 0 has higher chances to be just a register renaming and not utilise ALU at all
We have observed small positive effect on hifive (and no change on thead).
testing: tier1 and tier2 on hifive, also hotspot/jtreg/compiler/intrinsics/string tests on Qemu with UseZba
performance on hifive, before:
with patch:
Progress
Issue
Reviewers
Reviewing
Using
git
Checkout this PR locally:
$ git fetch https://git.openjdk.org/jdk.git pull/14823/head:pull/14823
$ git checkout pull/14823
Update a local copy of the PR:
$ git checkout pull/14823
$ git pull https://git.openjdk.org/jdk.git pull/14823/head
Using Skara CLI tools
Checkout this PR locally:
$ git pr checkout 14823
View PR using the GUI difftool:
$ git pr show -t 14823
Using diff file
Download this PR as a diff file:
https://git.openjdk.org/jdk/pull/14823.diff
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