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8318953: RISC-V: Small refactoring for MacroAssembler::test_bit #16391

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@zifeihan zifeihan commented Oct 27, 2023

Hi, The current test_bit assembly function needs to accept a temporary register because it needs one if it goes to the andi else branch. However, in this case we can actually avoid calling andi and accomplish the same thing by logically shifting to the right and testing the lowest bit. The advantage is that it makes the test_bit function much simpler. Also, to reduce the number of instructions in a given case (consider the mv function), mv actually calls the li function, which generates more than one instruction when the parameter imm exceeds the 32-bit range.

void MacroAssembler::andi(Register Rd, Register Rn, int64_t imm, Register tmp) {
if (is_simm12(imm)) {
and_imm12(Rd, Rn, imm);
} else {
assert_different_registers(Rn, tmp);
mv(tmp, imm);
andr(Rd, Rn, tmp);
}
}

inline void mv(Register Rd, T o) { li(Rd, (int64_t)o); }

void MacroAssembler::li(Register Rd, int64_t imm) {
// int64_t is in range 0x8000 0000 0000 0000 ~ 0x7fff ffff ffff ffff
// li -> c.li
if (do_compress() && (is_simm6(imm) && Rd != x0)) {
c_li(Rd, imm);
return;
}
int shift = 12;
int64_t upper = imm, lower = imm;
// Split imm to a lower 12-bit sign-extended part and the remainder,
// because addi will sign-extend the lower imm.
lower = ((int32_t)imm << 20) >> 20;
upper -= lower;
// Test whether imm is a 32-bit integer.
if (!(((imm) & ~(int64_t)0x7fffffff) == 0 ||
(((imm) & ~(int64_t)0x7fffffff) == ~(int64_t)0x7fffffff))) {
while (((upper >> shift) & 1) == 0) { shift++; }
upper >>= shift;
li(Rd, upper);
slli(Rd, Rd, shift);
if (lower != 0) {
addi(Rd, Rd, lower);
}
} else {
// 32-bit integer
Register hi_Rd = zr;
if (upper != 0) {
lui(Rd, (int32_t)upper);
hi_Rd = Rd;
}
if (lower != 0 || hi_Rd == zr) {
addiw(Rd, hi_Rd, lower);
}
}
}

Testing:

qemu 8.1.50:

  • Tier1 tests (fastdebug)
  • Tier2 tests (release)
  • Tier3 tests (release)

Progress

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  • Change must not contain extraneous whitespace
  • Commit message must refer to an issue

Issue

  • JDK-8318953: RISC-V: Small refactoring for MacroAssembler::test_bit (Enhancement - P4)

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Using git

Checkout this PR locally:
$ git fetch https://git.openjdk.org/jdk.git pull/16391/head:pull/16391
$ git checkout pull/16391

Update a local copy of the PR:
$ git checkout pull/16391
$ git pull https://git.openjdk.org/jdk.git pull/16391/head

Using Skara CLI tools

Checkout this PR locally:
$ git pr checkout 16391

View PR using the GUI difftool:
$ git pr show -t 16391

Using diff file

Download this PR as a diff file:
https://git.openjdk.org/jdk/pull/16391.diff

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bridgekeeper bot commented Oct 27, 2023

👋 Welcome back gcao! A progress list of the required criteria for merging this PR into master will be added to the body of your pull request. There are additional pull request commands available for use with this pull request.

@openjdk openjdk bot added the rfr Pull request is ready for review label Oct 27, 2023
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openjdk bot commented Oct 27, 2023

@zifeihan The following label will be automatically applied to this pull request:

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When this pull request is ready to be reviewed, an "RFR" email will be sent to the corresponding mailing list. If you would like to change these labels, use the /label pull request command.

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mlbridge bot commented Oct 27, 2023

Webrevs

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Looks good.

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openjdk bot commented Oct 27, 2023

@zifeihan This change now passes all automated pre-integration checks.

ℹ️ This project also has non-automated pre-integration requirements. Please see the file CONTRIBUTING.md for details.

After integration, the commit message for the final commit will be:

8318953: RISC-V: Small refactoring for MacroAssembler::test_bit

Reviewed-by: fyang, fjiang, luhenry

You can use pull request commands such as /summary, /contributor and /issue to adjust it as needed.

At the time when this comment was updated there had been 16 new commits pushed to the master branch:

  • ce0ca47: 8319067: ProblemList serviceability/AsyncGetCallTrace/MyPackage/ASGCTBaseTest.java on linux-aarch64 in Xcomp mode
  • db34025: 8318827: RISC-V: Improve readability of fclass result testing
  • 1ec0d02: 8318225: RISC-V: C2 UModI
  • 96bec35: 8316996: Catalog API Enhancement: add a factory method
  • d226014: 8318850: Duplicate code in the LCMSImageLayout
  • c593f8b: 8318091: Remove empty initIDs functions
  • 4f9f195: 8318753: hsdis binutils may place libs in lib64
  • 2915d74: 8318837: javac generates wrong ldc instruction for dynamic constant loads
  • ddd0716: 8317661: [REDO] store/load order not preserved when handling memory pool due to weakly ordered memory architecture of aarch64
  • 141dae8: 8318811: Compiler directives parser swallows a character after line comments
  • ... and 6 more: https://git.openjdk.org/jdk/compare/9123961aaa47aa58ec436640590d2cceedb8cbb1...master

As there are no conflicts, your changes will automatically be rebased on top of these commits when integrating. If you prefer to avoid this automatic rebasing, please check the documentation for the /integrate command for further details.

As you do not have Committer status in this project an existing Committer must agree to sponsor your change. Possible candidates are the reviewers of this PR (@RealFYang, @feilongjiang, @luhenry) but any other Committer may sponsor as well.

➡️ To flag this PR as ready for integration with the above commit message, type /integrate in a new comment. (Afterwards, your sponsor types /sponsor in a new comment to perform the integration).

@openjdk openjdk bot added the ready Pull request is ready to be integrated label Oct 27, 2023
@VladimirKempik
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Hello, do you have plans to backport this to 21u and 17u afterwards ?

@zifeihan
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Hello, do you have plans to backport this to 21u and 17u afterwards ?

Yes, we'll do a backport later.

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Looks good, thanks!

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tier1-3 test passed.
/integrate

@openjdk openjdk bot added the sponsor Pull request is ready to be sponsored label Oct 29, 2023
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openjdk bot commented Oct 29, 2023

@zifeihan
Your change (at version a6e85a1) is now ready to be sponsored by a Committer.

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/sponsor

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openjdk bot commented Oct 30, 2023

Going to push as commit 988e1df.
Since your change was applied there have been 16 commits pushed to the master branch:

  • ce0ca47: 8319067: ProblemList serviceability/AsyncGetCallTrace/MyPackage/ASGCTBaseTest.java on linux-aarch64 in Xcomp mode
  • db34025: 8318827: RISC-V: Improve readability of fclass result testing
  • 1ec0d02: 8318225: RISC-V: C2 UModI
  • 96bec35: 8316996: Catalog API Enhancement: add a factory method
  • d226014: 8318850: Duplicate code in the LCMSImageLayout
  • c593f8b: 8318091: Remove empty initIDs functions
  • 4f9f195: 8318753: hsdis binutils may place libs in lib64
  • 2915d74: 8318837: javac generates wrong ldc instruction for dynamic constant loads
  • ddd0716: 8317661: [REDO] store/load order not preserved when handling memory pool due to weakly ordered memory architecture of aarch64
  • 141dae8: 8318811: Compiler directives parser swallows a character after line comments
  • ... and 6 more: https://git.openjdk.org/jdk/compare/9123961aaa47aa58ec436640590d2cceedb8cbb1...master

Your commit was automatically rebased without conflicts.

@openjdk openjdk bot added the integrated Pull request has been integrated label Oct 30, 2023
@openjdk openjdk bot closed this Oct 30, 2023
@openjdk openjdk bot removed ready Pull request is ready to be integrated rfr Pull request is ready for review sponsor Pull request is ready to be sponsored labels Oct 30, 2023
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openjdk bot commented Oct 30, 2023

@RealFYang @zifeihan Pushed as commit 988e1df.

💡 You may see a message that your pull request was closed with unmerged commits. This can be safely ignored.

@zifeihan zifeihan deleted the JDK-8318953 branch January 2, 2024 06:43
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