8318218: RISC-V: C2 CompressBits #16481

Hamlin-Li · 2023-11-02T16:50:50Z

Hi,
Can you review the change to add intrinsic for CompressBits for Long & Integer?
Thanks!

## Test
pass jtreg test:
test/jdk/java/lang/CompressExpand*.java

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Issue

JDK-8318218: RISC-V: C2 CompressBits (Sub-task - P4)

Reviewers

Fei Yang (@RealFYang - Reviewer)
Feilong Jiang (@feilongjiang - Committer)

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bridgekeeper · 2023-11-02T16:51:52Z

👋 Welcome back mli! A progress list of the required criteria for merging this PR into master will be added to the body of your pull request. There are additional pull request commands available for use with this pull request.

openjdk · 2023-11-02T16:54:09Z

@Hamlin-Li The following label will be automatically applied to this pull request:

hotspot

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mlbridge · 2023-11-02T16:57:24Z

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Hamlin-Li · 2023-11-02T17:31:22Z

I made a mistake, UseRVVForCompressBitsIntrinsics is only defined in riscv global.hpp.
I think I can resolve the issue by defining it in global global.hpp, but seems it's not a good idea either.
Any suggestions?

src/hotspot/cpu/riscv/macroAssembler_riscv.cpp

src/hotspot/cpu/riscv/macroAssembler_riscv.hpp

feilongjiang · 2023-11-03T01:33:43Z

I made a mistake, UseRVVForCompressBitsIntrinsics is only defined in riscv global.hpp. I think I can resolve the issue by defining it in global global.hpp, but seems it's not a good idea either. Any suggestions?

Maybe bool Matcher::match_rule_supported(int opcode) { in riscv.ad is a good place, and just returning UseRVV would be enough for Op_CompressBits?:

jdk/src/hotspot/cpu/riscv/riscv.ad

Lines 1896 to 1897 in c788160

    
           case Op_EncodeISOArray: 
        
             return UseRVV && SpecialEncodeISOArray;

robehn · 2023-11-03T08:19:28Z

Personally I'm against these 'micro' options .e.g. UseRVVForXX.
Even if it was possible to test out all combinations of options, no end-user will actually do it.
I'm perfectly fine with just removing those and just have RVV in this cases.

theRealAph · 2023-11-03T08:42:46Z

Personally I'm against these 'micro' options .e.g. UseRVVForXX. Even if it was possible to test out all combinations of options, no end-user will actually do it. I'm perfectly fine with just removing those and just have RVV in this cases.

Indeed. We already can turn on and off individual intrinsics.

…; move code to riscv_v.ad and C2_MacroAssembler

Hamlin-Li · 2023-11-03T12:17:16Z

Thanks @feilongjiang for pointing at the postion.

@robehn @theRealAph I agree, thanks for discussion

src/hotspot/cpu/riscv/riscv.ad

RealFYang · 2023-11-08T05:53:56Z

src/hotspot/cpu/riscv/riscv_v.ad

+// CompressBits of Long & Integer
+
+instruct compressBitsI(iRegINoSp dst, iRegIorL2I src, iRegIorL2I mask, iRegPNoSp tmp, vRegMask_V0 v0, vReg_V4 v4, vReg_V8 v8) %{
+  predicate(UseRVV && (MaxVectorSize >= 16));


Can we simply remote the (MaxVectorSize >= 16) condition as that has already been ensured on JVM startup?

RealFYang · 2023-11-08T05:54:09Z

src/hotspot/cpu/riscv/riscv_v.ad

+%}
+
+instruct compressBitsL(iRegLNoSp dst, iRegL src, iRegL mask, iRegPNoSp tmp, vRegMask_V0 v0, vReg_V4 v4, vReg_V8 v8) %{
+  predicate(UseRVV && (MaxVectorSize >= 16));


Same as above.

Yes, seems it's redundant to check it here again, as we already have a check in Matcher::match_rule_supported where it's necessary to avoid silent failure in case restrictions on MaxVectorSize is changed in the future.
It's removed here.

src/hotspot/cpu/riscv/riscv.ad

RealFYang · 2023-11-08T07:32:34Z

src/hotspot/cpu/riscv/c2_MacroAssembler_riscv.cpp

@@ -1681,6 +1681,44 @@ void C2_MacroAssembler::signum_fp(FloatRegister dst, FloatRegister src, FloatReg
  bind(done);
 }

+void C2_MacroAssembler::compress_bits_v(Register dst, Register src, Register mask, Register tmp, bool is_long) {


Seems that this is quite similar to the implementation of CompressM node in riscv_v.ad [1] which I think should be more efficient. The only difference is that we only need to move src into a vector register beforehand and change to perform vcpop_m under the given mask. Please consider.

[1] https://github.com/openjdk/jdk/blob/master/src/hotspot/cpu/riscv/riscv_v.ad#L3506-L3518

Ah, I see the difference now. The active 0 bits are still kept back here in this case [1].

[1] https://github.com/openjdk/jdk/blob/master/src/hotspot/share/opto/intrinsicnode.cpp#L300-L310

src/hotspot/cpu/riscv/c2_MacroAssembler_riscv.cpp

RealFYang · 2023-11-10T09:09:33Z

src/hotspot/cpu/riscv/c2_MacroAssembler_riscv.cpp

+  vsetivli(x0, 1, sew, lmul);
+  vmv_s_x(v0, src);
+  // reset the src data(in bytes) to zero.
+  mv(tmp, len);


Can we use scratch register t0 instead of tmp in this function?

src/hotspot/cpu/riscv/riscv_v.ad

RealFYang · 2023-11-10T14:55:53Z

@Hamlin-Li : Thanks for the update. But I am still not satisfied with current approach. The issue is that we will be wasting vector registers when running on hardwares equipped with RVV registers of bigger width, say 256-bits. We are reserving more vector registers than needed in that case, which might mean some extra vector register spilling/reloading under high register pressure. We should consider this issue.

Hamlin-Li · 2023-11-10T15:07:51Z

Yes, that's the potential possible issues.
Or maybe we can tighten the matcher rule to enable the intrinsic: for example, return UseRVV && (MaxVectorSize >= 32) (or even 64) in Matcher::match_rule_supported, so for Long it will be v2(v3), v4(v5), for Integer, it will v2, v4, just any 2 vector regs if we tighten the match rule to >=64. Does this make sense?

RealFYang · 2023-11-13T06:27:18Z

src/hotspot/cpu/riscv/c2_MacroAssembler_riscv.cpp

+  long len = is_long ? 64 : 32;
+
+  // load the src data(in bits) to be compressed.
+  vsetivli(x0, 1, sew, lmul);


A default lmul of m1 is enough to perform the succeeding vmv_s_x instuction as specified by the RVV spec.

The integer scalar read/write instructions transfer a single value between a scalar x register and element 0 of a vector register. The instructions ignore LMUL and vector register groups.

Seems it make no difference at run time, as The instructions ignore LMUL and vector register groups..
But it makes sense to modify it as you suggested, it's more clear.

RealFYang · 2023-11-13T06:31:33Z

src/hotspot/cpu/riscv/c2_MacroAssembler_riscv.cpp

+  vmv_v_i(v8, 0);
+  // load the mask data(in bits).
+  vsetivli(x0, 1, sew, lmul);
+  vmv_v_x(v0, mask);


Shouldn't this be vmv_s_x(v0, mask) instead of vmv_v_x(v0, mask)? The vcompress.vm instruction is expecting a vector mask register. Also the preceding vsetivli should be changed to use a default lmul of m1 at the same time.

Good catch!

RealFYang · 2023-11-13T06:33:13Z

src/hotspot/cpu/riscv/c2_MacroAssembler_riscv.cpp

+  // convert the dst data from bytes to bits.
+  vmseq_vi(v0, v8, 1);
+  // store result back.
+  vsetivli(x0, 1, sew, lmul);


Similar here. This vsetivli instruction should be changed to use a default lmul of m1

RealFYang · 2023-11-13T06:46:17Z

Yes, that's the potential possible issues. Or maybe we can tighten the matcher rule to enable the intrinsic: for example, return UseRVV && (MaxVectorSize >= 32) (or even 64) in Matcher::match_rule_supported, so for Long it will be v2(v3), v4(v5), for Integer, it will v2, v4, just any 2 vector regs if we tighten the match rule to >=64. Does this make sense?

I see chip vendors are shipping products with RVV VLEN of 128 bits. So I think it's more reasonable to go with the current implementation for now. While it seems that this would win in respect of number if instruction executed compared with the scalar version, we still need to revisit/bechmark this change when we have access to the real RVV hardware.

RealFYang · 2023-11-13T14:44:44Z

src/hotspot/cpu/riscv/c2_MacroAssembler_riscv.cpp

@@ -1700,14 +1700,14 @@ void C2_MacroAssembler::compress_bits_v(Register dst, Register src, Register mas
  vmv_v_i(v8, 0);
  // load the mask data(in bits).
  vsetivli(x0, 1, sew, lmul);


Please also change line into "vsetivli(x0, 1, sew, Assembler::m1)" for consistency. Otherwise LGTM.

RealFYang

Ah ... We still have two copy-paste issues.

RealFYang · 2023-11-13T15:08:21Z

src/hotspot/cpu/riscv/riscv_v.ad

+// CompressBits of Long & Integer
+
+instruct compressBitsI(iRegINoSp dst, iRegIorL2I src, iRegIorL2I mask, vRegMask_V0 v0,
+                       vReg_V4 v4, vReg_V4 v5, vReg_V8 v8, vReg_V4 v9) %{


Just noticed that this should be vReg_V4 v4, vReg_V5 v5, vReg_V8 v8, vReg_V9 v9.

My bad, thanks for catching these typos!

RealFYang · 2023-11-13T15:09:42Z

src/hotspot/cpu/riscv/riscv_v.ad

+
+instruct compressBitsL(iRegLNoSp dst, iRegL src, iRegL mask, vRegMask_V0 v0,
+                       vReg_V4 v4, vReg_V4 v5, vReg_V4 v6, vReg_V4 v7,
+                       vReg_V8 v8, vReg_V4 v9, vReg_V4 v10, vReg_V4 v11) %{


Similar issue here for v5-v7 and v9-v11.

openjdk · 2023-11-14T07:13:22Z

@Hamlin-Li This change now passes all automated pre-integration checks.

ℹ️ This project also has non-automated pre-integration requirements. Please see the file CONTRIBUTING.md for details.

After integration, the commit message for the final commit will be:

8318218: RISC-V: C2 CompressBits

Reviewed-by: fyang, fjiang

You can use pull request commands such as /summary, /contributor and /issue to adjust it as needed.

At the time when this comment was updated there had been 77 new commits pushed to the master branch:

fe0ccdf: 8319640: ClassicFormat::parseObject (from DateTimeFormatter) does not conform to the javadoc and may leak DateTimeException
1802cb5: 8319570: Change to GCC 13.2.0 for building on Linux at Oracle
d992033: 8317562: [JFR] Compilation queue statistics
965ae72: 8319753: Duration javadoc has "period" instead of "duration" in several places
115b074: 8319944: Remove DynamicDumpSharedSpaces
c0507af: 8319818: Address GCC 13.2.0 warnings (stringop-overflow and dangling-pointer)
3684b4b: 8306116: Update CLDR to Version 44.0
88ccd64: 8296250: Update ICU4J to Version 74.1
03db828: 8319650: Improve heap dump performance with class metadata caching
b41b00a: 8319820: Use unnamed variables in the FFM implementation
... and 67 more: https://git.openjdk.org/jdk/compare/74f1889b58c6ad1cdc7401e7cbb9f614acf0c171...master

As there are no conflicts, your changes will automatically be rebased on top of these commits when integrating. If you prefer to avoid this automatic rebasing, please check the documentation for the /integrate command for further details.

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Hamlin-Li · 2023-11-14T09:57:41Z

Thanks everyone for your review and discussion!

/integrate

openjdk · 2023-11-14T09:59:10Z

Going to push as commit cb7875d.
Since your change was applied there have been 83 commits pushed to the master branch:

1535528: 8318479: [jmh] the test security.CacheBench failed for multiple threads run
95bd92a: 8210807: Printing a JTable with a JScrollPane prints table without rows populated
21cda19: 8309203: C2: remove copy-by-value of GrowableArray for InterfaceSet
b120a05: 8319406: x86: Shorter movptr(reg, imm) for 32-bit immediates
7df73a2: 8318817: Could not reserve enough space in CodeHeap 'profiled nmethods' (0K)
07eaea8: 8303920: Avoid calling out to python in DataDescriptorSignatureMissing test
fe0ccdf: 8319640: ClassicFormat::parseObject (from DateTimeFormatter) does not conform to the javadoc and may leak DateTimeException
1802cb5: 8319570: Change to GCC 13.2.0 for building on Linux at Oracle
d992033: 8317562: [JFR] Compilation queue statistics
965ae72: 8319753: Duration javadoc has "period" instead of "duration" in several places
... and 73 more: https://git.openjdk.org/jdk/compare/74f1889b58c6ad1cdc7401e7cbb9f614acf0c171...master

Your commit was automatically rebased without conflicts.

openjdk · 2023-11-14T09:59:16Z

@Hamlin-Li Pushed as commit cb7875d.

💡 You may see a message that your pull request was closed with unmerged commits. This can be safely ignored.

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remove the new vm option, using Matcher::match_rule_supported instead…

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…; move code to riscv_v.ad and C2_MacroAssembler

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Hamlin-Li added 2 commits November 7, 2023 09:53

Match Op_CompressBits based on UseRVV only

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Merge branch 'master' into compress-bits

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Remove redundant check

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remove extra new line

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reserve all used v register; use t0 directly

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8319781: RISC-V: Refactor UseRVV related checks #16580

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8318219: RISC-V: C2 ExpandBits #16658

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