-
Notifications
You must be signed in to change notification settings - Fork 5.7k
New issue
Have a question about this project? Sign up for a free GitHub account to open an issue and contact its maintainers and the community.
By clicking “Sign up for GitHub”, you agree to our terms of service and privacy statement. We’ll occasionally send you account related emails.
Already on GitHub? Sign in to your account
JDK-8320892: AArch64: Restore FPU control state after JNI #16851
Conversation
👋 Welcome back aph! A progress list of the required criteria for merging this PR into |
@theRealAph The following label will be automatically applied to this pull request:
When this pull request is ready to be reviewed, an "RFR" email will be sent to the corresponding mailing list. If you would like to change these labels, use the /label pull request command. |
Webrevs
|
// don't want non-IEEE rounding modes or floating-point traps. | ||
bfi(tmp1, zr, 22, 4); // Clear DN, FZ, and Rmode | ||
bfi(tmp1, zr, 8, 5); // Clear exception-control bits (8-12) | ||
eor(tmp1, tmp1, tmp2); |
There was a problem hiding this comment.
Choose a reason for hiding this comment
The reason will be displayed to describe this comment to others. Learn more.
Hmm? So . . .
- We ensure tmp1 has the bits we want by clearing DN FZ Rmode and Exception bits
- we XOR tmp1 with the original bits (saved in tmp2) and put the 'difference' in tmp1 (?)
- If the difference is zero we skip
- Otherwise we write tmp1 (i.e. the 'difference' bits) to fpcr (???)
Should this not be
get_fpcr(tmp1);
mov(tmp2, tmp1);
bfi(tmp1, zr, 22, 4);
bfi(tmp1, zr, 8, 5);
eor(tmp2, tmp1, tmp2)
cbz(tmp2, OK);
set_fpcr(tmp1);
bind(OK);
There was a problem hiding this comment.
Choose a reason for hiding this comment
The reason will be displayed to describe this comment to others. Learn more.
Argh, yes. The curse of the last-minute change...
Good catch.
There was a problem hiding this comment.
Choose a reason for hiding this comment
The reason will be displayed to describe this comment to others. Learn more.
Looks good.
@theRealAph This change now passes all automated pre-integration checks. ℹ️ This project also has non-automated pre-integration requirements. Please see the file CONTRIBUTING.md for details. After integration, the commit message for the final commit will be:
You can use pull request commands such as /summary, /contributor and /issue to adjust it as needed. At the time when this comment was updated there had been 173 new commits pushed to the
As there are no conflicts, your changes will automatically be rebased on top of these commits when integrating. If you prefer to avoid this automatic rebasing, please check the documentation for the /integrate command for further details. ➡️ To integrate this PR with the above commit message to the |
bfi(tmp1, zr, 22, 4); // Clear DN, FZ, and Rmode | ||
bfi(tmp1, zr, 8, 5); // Clear exception-control bits (8-12) | ||
eor(tmp2, tmp1, tmp2); | ||
cbz(tmp2, OK); // Only reset FPCR if it's wrong |
There was a problem hiding this comment.
Choose a reason for hiding this comment
The reason will be displayed to describe this comment to others. Learn more.
should we maybe do the same in generate_call_stub, too (likely faster)?
There was a problem hiding this comment.
Choose a reason for hiding this comment
The reason will be displayed to describe this comment to others. Learn more.
Sure, it would be. I didn't think it was worthwhile, but we have the code now.
x86 also has a restore call in DowncallLinker::StubGenerator::generate so you might consider adding there as well. |
Regarding the flag name you could introduce a better name and alias to it RestoreMXCSROnJNICalls. Reusing the same name it definitely confusing. At a minimum you need to update the documentation for RestoreMXCSROnJNICalls to indicate that it also does something on aarch64 or generalize the language to something like |
Ah, I did not know that flag aliases were possible. I'll have a look at something generic.
I'll go digging. |
I think it's there. |
Yes it's there. Sorry I guess I was scanning too quickly. |
I was also going to suggest adding a new flag and creating an alias. The new flag will need a CSR request of course. |
Given that it's new and it's diagnostic flag I'm a bit surprised at that. I was trying for a quick fix. Anyway, how do you create an alias? I can't see any examples, and I haven't found a way through the maze of twisty |
@theRealAph the Aliased flags are setup in arguments.cpp by editing this:
|
Also from arguments.cpp
|
Ah, thanks,
OK. How about we split this into two, this first part without a CSR, and the second part, which creates the generic alias, with one? That way we can mitigate a live problem in this release. |
Please? One day left. |
There was a problem hiding this comment.
Choose a reason for hiding this comment
The reason will be displayed to describe this comment to others. Learn more.
Looks good.
I looked at https://help.totalview.io/previous_releases/2019/HTML/index.html#page/Reference_Guide%2FPowerFPSCRRegister_2.html%23, and there seems to be another exception bit, bit 15, the "Input denormal exception enable". That one is okay to be modified?
// Set FPCR to the state we need. We do want Round to Nearest. We | ||
// don't want non-IEEE rounding modes or floating-point traps. | ||
bfi(tmp1, zr, 22, 4); // Clear DN, FZ, and Rmode | ||
bfi(tmp1, zr, 8, 5); // Clear exception-control bits (8-12) |
There was a problem hiding this comment.
Choose a reason for hiding this comment
The reason will be displayed to describe this comment to others. Learn more.
(Related to both this PR and #16637)
Shouldn't also explicit flushing inputs to zero, i.e. when AH:FIZ is (1:1), be protected against?
Also, is it necessary to clear DN? When looking at the spec, I think this should be allowed.
There was a problem hiding this comment.
Choose a reason for hiding this comment
The reason will be displayed to describe this comment to others. Learn more.
(Related to both this PR and #16637)
Shouldn't also explicit flushing inputs to zero, i.e. when AH:FIZ is (1:1), be protected against?
I've avoided touching ArmV8.7 ALT_FP, but you might be right. AH:FIZ are both RES0, so it is safe to do so.
Also, is it necessary to clear DN? When looking at the spec, I think this should be allowed.
I think it's wise to clear DN. We save and restore all of the FPCR at entry to Java, clearing DN, and it's not unreasonable to expect a JNI call not to mess with FPCR. Also, I think replacing NaN payload bits with the default NaN is pointless, and violates the principle of least surprise if not the spec of longBitsToDouble
.
I'm fine with splitting it if needed, but I also re-evaluated this as a P3 so it can still go into 22 after RDP 1. |
/integrate |
Going to push as commit 50f3124.
Your commit was automatically rebased without conflicts. |
@theRealAph Pushed as commit 50f3124. 💡 You may see a message that your pull request was closed with unmerged commits. This can be safely ignored. |
@theRealAph IMHO we should add a new flag aliasing the old. Then deprecate MXCSR flag. |
Some buggy libraries corrupt the floating-point control register. Provide something similar to the x86 RestoreMXCSROnJNICalls.
I realize that using the x86ish name "RestoreMXCSROnJNICalls" might be a little controversial, but it is a global flag, not a CPU-specific one. And it's clearly intended for this purpose. It might have been better if that flag had been given a better name twentyish years ago, but we can't change it now.
Progress
Issue
Reviewers
Reviewing
Using
git
Checkout this PR locally:
$ git fetch https://git.openjdk.org/jdk.git pull/16851/head:pull/16851
$ git checkout pull/16851
Update a local copy of the PR:
$ git checkout pull/16851
$ git pull https://git.openjdk.org/jdk.git pull/16851/head
Using Skara CLI tools
Checkout this PR locally:
$ git pr checkout 16851
View PR using the GUI difftool:
$ git pr show -t 16851
Using diff file
Download this PR as a diff file:
https://git.openjdk.org/jdk/pull/16851.diff
Webrev
Link to Webrev Comment