8332533: RISC-V: Enable vector variable shift instructions for machines with RVV

[zifeihan]

Hi, I noticed the following warning in the Opto JIT Code for the Vector API in the test/jdk/jdk/incubator/vector/Byte256VectorTests.java: ASHRByte256VectorTests test:

--------------------------------------------------------------------------------
  ** Rejected vector op (RShiftVB,byte,32) because architecture does not support variable vector shifts
  ** not supported: arity=2 opc=405 vlen=32 etype=byte ismask=0 is_masked_op=0

the reason is because Matcher::supports_vector_ variable_shifts returns false. the port of RISC-V Vector API now supports the vector shifts, so this should return with UseRVV. By the Way, the Matcher::supports_vector_variable_shifts function was introduced by Vector API, and I think forgot to modify the Matcher::supports_vector_variable_shifts function when implementing vector shift.
After the fix, the test passes normally and generates the Opto JIT Code such as:

1c2     loadV V1, [R7]  # vector (rvv)
1ca     lwu  R28, [R28, #12]    # loadN, compressed ptr, #@loadN ! Field: jdk/internal/vm/vector/VectorSupport$VectorPayload.payload (constant)
1ce     decode_heap_oop  R7, R28    #@decodeHeapOop
1d2     addi  R7, R7, #16   # ptr, #@addP_reg_imm
1d4     loadV V2, [R7]  # vector (rvv)
1dc     vand_immI V1, V1, #7
1e4     spill [sp, #48] -> R7    # spill size = 32
1e6     # castII of R7, #@castII
1e6     vasrB V3, V2, V1
1fa     spill [sp, #96] -> R29   # spill size = 32
1fc     bgeu  R7, R29, B101 #@cmpU_branch  P=0.000001 C=-1.000000

Testing:

qemu 8.1.50 with UseRVV:

• Run tier1-3 tests (release)
• Run test/jdk/jdk/incubator/vector (fastdebug)

---

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Issue

• JDK-8332533: RISC-V: Enable vector variable shift instructions for machines with RVV (Enhancement - P4)

Reviewers

• Fei Yang (@RealFYang - Reviewer) ⚠️ Review applies to 546c255a
• Hamlin Li (@Hamlin-Li - Reviewer)

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[openjdk]

@zifeihan This change now passes all automated pre-integration checks.

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8332533: RISC-V: Enable vector variable shift instructions for machines with RVV

Reviewed-by: fyang, mli

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[mlbridge]

Webrevs

• 02: Full - Incremental (e8042c6d)
• 01: Full - Incremental (0c64eee1)
• 00: Full (546c255a)

[RealFYang]

Looks good. Thanks.

[Hamlin-Li]

Looks good, thanks.

[Hamlin-Li]

Is UseRVV a const? Seems you need to remove constexpr.
Or you can just return true (so, keep constexpr), as supports_vector_variable_shifts is not a independent check, and it's protected by Matcher::match_rule_supported_vector in both vector api and auto-vectorization.

[zifeihan]

Is UseRVV a const? Seems you need to remove constexpr. Or you can just return true (so, keep constexpr), as supports_vector_variable_shifts is not a independent check, and it's protected by Matcher::match_rule_supported_vector in both vector api and auto-vectorization.

Thanks for your review. I've removed constexpr.

[Hamlin-Li]

Thanks, still good.

[zifeihan]

@RealFYang @Hamlin-Li : Thanks for the review.
/integrate

[openjdk]

@zifeihan
Your change (at version e8042c6) is now ready to be sponsored by a Committer.

[RealFYang]

/sponsor

[openjdk]

Going to push as commit 67f03f2.

[openjdk]

@RealFYang @zifeihan Pushed as commit 67f03f2.

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