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8334999: RISC-V: implement AES single block encryption/decryption intrinsics #19960
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👋 Welcome back ArsenyBochkarev! A progress list of the required criteria for merging this PR into |
@ArsenyBochkarev This change now passes all automated pre-integration checks. ℹ️ This project also has non-automated pre-integration requirements. Please see the file CONTRIBUTING.md for details. After integration, the commit message for the final commit will be:
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Thank you, looks good!
As for comparison with the openssl version: first of all, thanks for the sources, @RealFYang! The main difference that I see is that they introduced three different different versions of encryption depending on the key sizes, which allows them to skip a couple of instructions, like when I did |
Does [1] https://github.com/openssl/openssl/blob/master/crypto/aes/asm/aes-riscv64-zvkned.pl#L451 |
@ArsenyBochkarev This pull request has been inactive for more than 4 weeks and will be automatically closed if another 4 weeks passes without any activity. To avoid this, simply add a new comment to the pull request. Feel free to ask for assistance if you need help with progressing this pull request towards integration! |
Hello @RealFYang! Sorry for such a late reply.
As far as I know, the
I missed this case in initial multiversioning commit, so I multiversioned the decrypt intrisic also, thanks for pointing it out! |
@RealFYang following up on your questions. I would love to see this one go through as it promises some pretty significant gains on compatible hardware! Thanks again |
Yeah, will take another look. Have you tried this on real hardware? Interesting to see the numbers. |
There is no real hardware that I know of that have vector crypto just yet. I expect it's one of these that we'll want to test as soon as hardware is available, and even possibly enable by default then |
Hi all! I'm sorry for such a late replies. I was able to optimize decryption sequence by using keys from encryption stage with reversed rounds order |
Thanks for the update. Do you mind several more minor cleanups? Looks good to me otherwise. Thanks. |
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@yhzhu20 Done! |
@ArsenyBochkarev Please do not rebase or force-push to an active PR as it invalidates existing review comments. Note for future reference, the bots always squash all changes into a single commit automatically as part of the integration. See OpenJDK Developers’ Guide for more information. |
Thank you. Approved. |
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Thanks for the update. Two comments remain. seems fine otherwise.
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Looks good. Thanks.
Thanks everyone for all the comments and reviews! |
/integrate |
@ArsenyBochkarev |
/sponsor |
Going to push as commit e5bbad0.
Your commit was automatically rebased without conflicts. |
@VladimirKempik @ArsenyBochkarev Pushed as commit e5bbad0. 💡 You may see a message that your pull request was closed with unmerged commits. This can be safely ignored. |
Hello everyone! Please review this port of vector AES single block encryption/decryption intrinsics. On my QEMU with
Zvkned
extension enabled thetest/hotspot/jtreg/compiler/codegen/aes/TestAESMain.java
test is OK. I know that currently hardware implementing this extension is not available on the market but I suppose this PR can be a good starting point on supporting AES intrinsics for RISC-V in OpenJDK.Progress
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git
Checkout this PR locally:
$ git fetch https://git.openjdk.org/jdk.git pull/19960/head:pull/19960
$ git checkout pull/19960
Update a local copy of the PR:
$ git checkout pull/19960
$ git pull https://git.openjdk.org/jdk.git pull/19960/head
Using Skara CLI tools
Checkout this PR locally:
$ git pr checkout 19960
View PR using the GUI difftool:
$ git pr show -t 19960
Using diff file
Download this PR as a diff file:
https://git.openjdk.org/jdk/pull/19960.diff
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