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4 changes: 2 additions & 2 deletions src/hotspot/cpu/aarch64/c1_MacroAssembler_aarch64.cpp
Original file line number Diff line number Diff line change
Expand Up @@ -75,8 +75,8 @@ int C1_MacroAssembler::lock_object(Register hdr, Register obj, Register disp_hdr

if (DiagnoseSyncOnValueBasedClasses != 0) {
load_klass(hdr, obj);
ldrw(hdr, Address(hdr, Klass::access_flags_offset()));
tstw(hdr, JVM_ACC_IS_VALUE_BASED_CLASS);
ldrb(hdr, Address(hdr, Klass::misc_flags_offset()));
tst(hdr, KlassFlags::_misc_is_value_based_class);
br(Assembler::NE, slow_case);
}

Expand Down
4 changes: 2 additions & 2 deletions src/hotspot/cpu/aarch64/c1_Runtime1_aarch64.cpp
Original file line number Diff line number Diff line change
Expand Up @@ -783,8 +783,8 @@ OopMapSet* Runtime1::generate_code_for(StubID id, StubAssembler* sasm) {
Label register_finalizer;
Register t = r5;
__ load_klass(t, r0);
__ ldrw(t, Address(t, Klass::access_flags_offset()));
__ tbnz(t, exact_log2(JVM_ACC_HAS_FINALIZER), register_finalizer);
__ ldrb(t, Address(t, Klass::misc_flags_offset()));
__ tbnz(t, exact_log2(KlassFlags::_misc_has_finalizer), register_finalizer);
__ ret(lr);

__ bind(register_finalizer);
Expand Down
8 changes: 4 additions & 4 deletions src/hotspot/cpu/aarch64/c2_MacroAssembler_aarch64.cpp
Original file line number Diff line number Diff line change
Expand Up @@ -64,8 +64,8 @@ void C2_MacroAssembler::fast_lock(Register objectReg, Register boxReg, Register

if (DiagnoseSyncOnValueBasedClasses != 0) {
load_klass(tmp, oop);
ldrw(tmp, Address(tmp, Klass::access_flags_offset()));
tstw(tmp, JVM_ACC_IS_VALUE_BASED_CLASS);
ldrb(tmp, Address(tmp, Klass::misc_flags_offset()));
tst(tmp, KlassFlags::_misc_is_value_based_class);
br(Assembler::NE, cont);
}

Expand Down Expand Up @@ -243,8 +243,8 @@ void C2_MacroAssembler::fast_lock_lightweight(Register obj, Register box, Regist

if (DiagnoseSyncOnValueBasedClasses != 0) {
load_klass(t1, obj);
ldrw(t1, Address(t1, Klass::access_flags_offset()));
tstw(t1, JVM_ACC_IS_VALUE_BASED_CLASS);
ldrb(t1, Address(t1, Klass::misc_flags_offset()));
tst(t1, KlassFlags::_misc_is_value_based_class);
br(Assembler::NE, slow_path);
}

Expand Down
4 changes: 2 additions & 2 deletions src/hotspot/cpu/aarch64/interp_masm_aarch64.cpp
Original file line number Diff line number Diff line change
Expand Up @@ -690,8 +690,8 @@ void InterpreterMacroAssembler::lock_object(Register lock_reg)

if (DiagnoseSyncOnValueBasedClasses != 0) {
load_klass(tmp, obj_reg);
ldrw(tmp, Address(tmp, Klass::access_flags_offset()));
tstw(tmp, JVM_ACC_IS_VALUE_BASED_CLASS);
ldrb(tmp, Address(tmp, Klass::misc_flags_offset()));
tst(tmp, KlassFlags::_misc_is_value_based_class);
br(Assembler::NE, slow_case);
}

Expand Down
6 changes: 3 additions & 3 deletions src/hotspot/cpu/aarch64/templateTable_aarch64.cpp
Original file line number Diff line number Diff line change
@@ -1,5 +1,5 @@
/*
* Copyright (c) 2003, 2023, Oracle and/or its affiliates. All rights reserved.
* Copyright (c) 2003, 2024, Oracle and/or its affiliates. All rights reserved.
* Copyright (c) 2014, Red Hat Inc. All rights reserved.
* DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
*
Expand Down Expand Up @@ -2191,9 +2191,9 @@ void TemplateTable::_return(TosState state)

__ ldr(c_rarg1, aaddress(0));
__ load_klass(r3, c_rarg1);
__ ldrw(r3, Address(r3, Klass::access_flags_offset()));
__ ldrb(r3, Address(r3, Klass::misc_flags_offset()));
Label skip_register_finalizer;
__ tbz(r3, exact_log2(JVM_ACC_HAS_FINALIZER), skip_register_finalizer);
__ tbz(r3, exact_log2(KlassFlags::_misc_has_finalizer), skip_register_finalizer);

__ call_VM(noreg, CAST_FROM_FN_PTR(address, InterpreterRuntime::register_finalizer), c_rarg1);

Expand Down
4 changes: 2 additions & 2 deletions src/hotspot/cpu/arm/c1_MacroAssembler_arm.cpp
Original file line number Diff line number Diff line change
Expand Up @@ -195,8 +195,8 @@ int C1_MacroAssembler::lock_object(Register hdr, Register obj, Register disp_hdr

if (DiagnoseSyncOnValueBasedClasses != 0) {
load_klass(tmp2, obj);
ldr_u32(tmp2, Address(tmp2, Klass::access_flags_offset()));
tst(tmp2, JVM_ACC_IS_VALUE_BASED_CLASS);
ldrb(tmp2, Address(tmp2, Klass::misc_flags_offset()));
tst(tmp2, KlassFlags::_misc_is_value_based_class);
b(slow_case, ne);
}

Expand Down
8 changes: 4 additions & 4 deletions src/hotspot/cpu/arm/c1_Runtime1_arm.cpp
Original file line number Diff line number Diff line change
@@ -1,5 +1,5 @@
/*
* Copyright (c) 2008, 2023, Oracle and/or its affiliates. All rights reserved.
* Copyright (c) 2008, 2024, Oracle and/or its affiliates. All rights reserved.
* DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
*
* This code is free software; you can redistribute it and/or modify it
Expand Down Expand Up @@ -504,11 +504,11 @@ OopMapSet* Runtime1::generate_code_for(StubID id, StubAssembler* sasm) {
{
__ set_info("register_finalizer", dont_gc_arguments);

// Do not call runtime if JVM_ACC_HAS_FINALIZER flag is not set
// Do not call runtime if has_finalizer flag is not set
__ load_klass(Rtemp, R0);
__ ldr_u32(Rtemp, Address(Rtemp, Klass::access_flags_offset()));
__ ldrb(Rtemp, Address(Rtemp, Klass::misc_flags_offset()));

__ tst(Rtemp, JVM_ACC_HAS_FINALIZER);
__ tst(Rtemp, KlassFlags::_misc_has_finalizer);
__ bx(LR, eq);

// Call VM
Expand Down
6 changes: 3 additions & 3 deletions src/hotspot/cpu/arm/c2_MacroAssembler_arm.cpp
Original file line number Diff line number Diff line change
@@ -1,5 +1,5 @@
/*
* Copyright (c) 2021, 2023, Oracle and/or its affiliates. All rights reserved.
* Copyright (c) 2021, 2024, Oracle and/or its affiliates. All rights reserved.
* DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
*
* This code is free software; you can redistribute it and/or modify it
Expand Down Expand Up @@ -86,8 +86,8 @@ void C2_MacroAssembler::fast_lock(Register Roop, Register Rbox, Register Rscratc

if (DiagnoseSyncOnValueBasedClasses != 0) {
load_klass(Rscratch, Roop);
ldr_u32(Rscratch, Address(Rscratch, Klass::access_flags_offset()));
tst(Rscratch, JVM_ACC_IS_VALUE_BASED_CLASS);
ldrb(Rscratch, Address(Rscratch, Klass::misc_flags_offset()));
tst(Rscratch, KlassFlags::_misc_is_value_based_class);
b(done, ne);
}

Expand Down
6 changes: 3 additions & 3 deletions src/hotspot/cpu/arm/interp_masm_arm.cpp
Original file line number Diff line number Diff line change
@@ -1,5 +1,5 @@
/*
* Copyright (c) 2008, 2023, Oracle and/or its affiliates. All rights reserved.
* Copyright (c) 2008, 2024, Oracle and/or its affiliates. All rights reserved.
* DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
*
* This code is free software; you can redistribute it and/or modify it
Expand Down Expand Up @@ -909,8 +909,8 @@ void InterpreterMacroAssembler::lock_object(Register Rlock) {

if (DiagnoseSyncOnValueBasedClasses != 0) {
load_klass(R0, Robj);
ldr_u32(R0, Address(R0, Klass::access_flags_offset()));
tst(R0, JVM_ACC_IS_VALUE_BASED_CLASS);
ldrb(R0, Address(R0, Klass::misc_flags_offset()));
tst(R0, KlassFlags::_misc_is_value_based_class);
b(slow_case, ne);
}

Expand Down
6 changes: 3 additions & 3 deletions src/hotspot/cpu/arm/templateTable_arm.cpp
Original file line number Diff line number Diff line change
@@ -1,5 +1,5 @@
/*
* Copyright (c) 2008, 2023, Oracle and/or its affiliates. All rights reserved.
* Copyright (c) 2008, 2024, Oracle and/or its affiliates. All rights reserved.
* DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
*
* This code is free software; you can redistribute it and/or modify it
Expand Down Expand Up @@ -2494,8 +2494,8 @@ void TemplateTable::_return(TosState state) {
assert(state == vtos, "only valid state");
__ ldr(R1, aaddress(0));
__ load_klass(Rtemp, R1);
__ ldr_u32(Rtemp, Address(Rtemp, Klass::access_flags_offset()));
__ tbz(Rtemp, exact_log2(JVM_ACC_HAS_FINALIZER), skip_register_finalizer);
__ ldrb(Rtemp, Address(Rtemp, Klass::misc_flags_offset()));
__ tbz(Rtemp, exact_log2(KlassFlags::_misc_has_finalizer), skip_register_finalizer);

__ call_VM(noreg, CAST_FROM_FN_PTR(address, InterpreterRuntime::register_finalizer), R1);

Expand Down
4 changes: 2 additions & 2 deletions src/hotspot/cpu/ppc/c1_MacroAssembler_ppc.cpp
Original file line number Diff line number Diff line change
Expand Up @@ -86,8 +86,8 @@ void C1_MacroAssembler::lock_object(Register Rmark, Register Roop, Register Rbox

if (DiagnoseSyncOnValueBasedClasses != 0) {
load_klass(Rscratch, Roop);
lwz(Rscratch, in_bytes(Klass::access_flags_offset()), Rscratch);
testbitdi(CCR0, R0, Rscratch, exact_log2(JVM_ACC_IS_VALUE_BASED_CLASS));
lbz(Rscratch, in_bytes(Klass::misc_flags_offset()), Rscratch);
testbitdi(CCR0, R0, Rscratch, exact_log2(KlassFlags::_misc_is_value_based_class));
bne(CCR0, slow_int);
}

Expand Down
6 changes: 3 additions & 3 deletions src/hotspot/cpu/ppc/c1_Runtime1_ppc.cpp
Original file line number Diff line number Diff line change
@@ -1,5 +1,5 @@
/*
* Copyright (c) 1999, 2023, Oracle and/or its affiliates. All rights reserved.
* Copyright (c) 1999, 2024, Oracle and/or its affiliates. All rights reserved.
* Copyright (c) 2012, 2023 SAP SE. All rights reserved.
* DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
*
Expand Down Expand Up @@ -479,8 +479,8 @@ OopMapSet* Runtime1::generate_code_for(StubID id, StubAssembler* sasm) {

// Load the klass and check the has finalizer flag.
__ load_klass(t, R3_ARG1);
__ lwz(t, in_bytes(Klass::access_flags_offset()), t);
__ testbitdi(CCR0, R0, t, exact_log2(JVM_ACC_HAS_FINALIZER));
__ lbz(t, in_bytes(Klass::misc_flags_offset()), t);
__ testbitdi(CCR0, R0, t, exact_log2(KlassFlags::_misc_has_finalizer));
// Return if has_finalizer bit == 0 (CR0.eq).
__ bclr(Assembler::bcondCRbiIs1, Assembler::bi0(CCR0, Assembler::equal), Assembler::bhintbhBCLRisReturn);

Expand Down
6 changes: 3 additions & 3 deletions src/hotspot/cpu/ppc/interp_masm_ppc_64.cpp
Original file line number Diff line number Diff line change
@@ -1,5 +1,5 @@
/*
* Copyright (c) 2003, 2023, Oracle and/or its affiliates. All rights reserved.
* Copyright (c) 2003, 2024, Oracle and/or its affiliates. All rights reserved.
* Copyright (c) 2012, 2023 SAP SE. All rights reserved.
* DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
*
Expand Down Expand Up @@ -970,8 +970,8 @@ void InterpreterMacroAssembler::lock_object(Register monitor, Register object) {

if (DiagnoseSyncOnValueBasedClasses != 0) {
load_klass(tmp, object);
lwz(tmp, in_bytes(Klass::access_flags_offset()), tmp);
testbitdi(CCR0, R0, tmp, exact_log2(JVM_ACC_IS_VALUE_BASED_CLASS));
lbz(tmp, in_bytes(Klass::misc_flags_offset()), tmp);
testbitdi(CCR0, R0, tmp, exact_log2(KlassFlags::_misc_is_value_based_class));
bne(CCR0, slow_case);
}

Expand Down
8 changes: 4 additions & 4 deletions src/hotspot/cpu/ppc/macroAssembler_ppc.cpp
Original file line number Diff line number Diff line change
Expand Up @@ -2558,8 +2558,8 @@ void MacroAssembler::compiler_fast_lock_object(ConditionRegister flag, Register

if (DiagnoseSyncOnValueBasedClasses != 0) {
load_klass(temp, oop);
lwz(temp, in_bytes(Klass::access_flags_offset()), temp);
testbitdi(flag, R0, temp, exact_log2(JVM_ACC_IS_VALUE_BASED_CLASS));
lbz(temp, in_bytes(Klass::misc_flags_offset()), temp);
testbitdi(flag, R0, temp, exact_log2(KlassFlags::_misc_is_value_based_class));
bne(flag, failure);
}

Expand Down Expand Up @@ -2749,8 +2749,8 @@ void MacroAssembler::compiler_fast_lock_lightweight_object(ConditionRegister fla

if (DiagnoseSyncOnValueBasedClasses != 0) {
load_klass(tmp1, obj);
lwz(tmp1, in_bytes(Klass::access_flags_offset()), tmp1);
testbitdi(flag, R0, tmp1, exact_log2(JVM_ACC_IS_VALUE_BASED_CLASS));
lbz(tmp1, in_bytes(Klass::misc_flags_offset()), tmp1);
testbitdi(flag, R0, tmp1, exact_log2(KlassFlags::_misc_is_value_based_class));
bne(flag, slow_path);
}

Expand Down
4 changes: 2 additions & 2 deletions src/hotspot/cpu/ppc/templateTable_ppc_64.cpp
Original file line number Diff line number Diff line change
Expand Up @@ -2130,8 +2130,8 @@ void TemplateTable::_return(TosState state) {

// Load klass of this obj.
__ load_klass(Rklass, R17_tos);
__ lwz(Rklass_flags, in_bytes(Klass::access_flags_offset()), Rklass);
__ testbitdi(CCR0, R0, Rklass_flags, exact_log2(JVM_ACC_HAS_FINALIZER));
__ lbz(Rklass_flags, in_bytes(Klass::misc_flags_offset()), Rklass);
__ testbitdi(CCR0, R0, Rklass_flags, exact_log2(KlassFlags::_misc_has_finalizer));
__ bfalse(CCR0, Lskip_register_finalizer);

__ call_VM(noreg, CAST_FROM_FN_PTR(address, InterpreterRuntime::register_finalizer), R17_tos /* obj */);
Expand Down
4 changes: 2 additions & 2 deletions src/hotspot/cpu/riscv/c1_MacroAssembler_riscv.cpp
Original file line number Diff line number Diff line change
Expand Up @@ -64,8 +64,8 @@ int C1_MacroAssembler::lock_object(Register hdr, Register obj, Register disp_hdr

if (DiagnoseSyncOnValueBasedClasses != 0) {
load_klass(hdr, obj);
lwu(hdr, Address(hdr, Klass::access_flags_offset()));
test_bit(temp, hdr, exact_log2(JVM_ACC_IS_VALUE_BASED_CLASS));
lbu(hdr, Address(hdr, Klass::misc_flags_offset()));
test_bit(temp, hdr, exact_log2(KlassFlags::_misc_is_value_based_class));
bnez(temp, slow_case, true /* is_far */);
}

Expand Down
6 changes: 3 additions & 3 deletions src/hotspot/cpu/riscv/c1_Runtime1_riscv.cpp
Original file line number Diff line number Diff line change
@@ -1,5 +1,5 @@
/*
* Copyright (c) 1999, 2023, Oracle and/or its affiliates. All rights reserved.
* Copyright (c) 1999, 2024, Oracle and/or its affiliates. All rights reserved.
* Copyright (c) 2014, Red Hat Inc. All rights reserved.
* Copyright (c) 2020, 2023, Huawei Technologies Co., Ltd. All rights reserved.
* DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
Expand Down Expand Up @@ -799,8 +799,8 @@ OopMapSet* Runtime1::generate_code_for(StubID id, StubAssembler* sasm) {
Label register_finalizer;
Register t = x15;
__ load_klass(t, x10);
__ lwu(t, Address(t, Klass::access_flags_offset()));
__ test_bit(t0, t, exact_log2(JVM_ACC_HAS_FINALIZER));
__ lbu(t, Address(t, Klass::misc_flags_offset()));
__ test_bit(t0, t, exact_log2(KlassFlags::_misc_has_finalizer));
__ bnez(t0, register_finalizer);
__ ret();

Expand Down
8 changes: 4 additions & 4 deletions src/hotspot/cpu/riscv/c2_MacroAssembler_riscv.cpp
Original file line number Diff line number Diff line change
Expand Up @@ -68,8 +68,8 @@ void C2_MacroAssembler::fast_lock(Register objectReg, Register boxReg,

if (DiagnoseSyncOnValueBasedClasses != 0) {
load_klass(tmp, oop);
lwu(tmp, Address(tmp, Klass::access_flags_offset()));
test_bit(tmp, tmp, exact_log2(JVM_ACC_IS_VALUE_BASED_CLASS));
lbu(tmp, Address(tmp, Klass::misc_flags_offset()));
test_bit(tmp, tmp, exact_log2(KlassFlags::_misc_is_value_based_class));
bnez(tmp, slow_path);
}

Expand Down Expand Up @@ -277,8 +277,8 @@ void C2_MacroAssembler::fast_lock_lightweight(Register obj, Register box,

if (DiagnoseSyncOnValueBasedClasses != 0) {
load_klass(tmp1, obj);
lwu(tmp1, Address(tmp1, Klass::access_flags_offset()));
test_bit(tmp1, tmp1, exact_log2(JVM_ACC_IS_VALUE_BASED_CLASS));
lbu(tmp1, Address(tmp1, Klass::misc_flags_offset()));
test_bit(tmp1, tmp1, exact_log2(KlassFlags::_misc_is_value_based_class));
bnez(tmp1, slow_path);
}

Expand Down
6 changes: 3 additions & 3 deletions src/hotspot/cpu/riscv/interp_masm_riscv.cpp
Original file line number Diff line number Diff line change
@@ -1,5 +1,5 @@
/*
* Copyright (c) 2003, 2023, Oracle and/or its affiliates. All rights reserved.
* Copyright (c) 2003, 2024, Oracle and/or its affiliates. All rights reserved.
* Copyright (c) 2014, 2020, Red Hat Inc. All rights reserved.
* Copyright (c) 2020, 2023, Huawei Technologies Co., Ltd. All rights reserved.
* DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
Expand Down Expand Up @@ -750,8 +750,8 @@ void InterpreterMacroAssembler::lock_object(Register lock_reg)

if (DiagnoseSyncOnValueBasedClasses != 0) {
load_klass(tmp, obj_reg);
lwu(tmp, Address(tmp, Klass::access_flags_offset()));
test_bit(tmp, tmp, exact_log2(JVM_ACC_IS_VALUE_BASED_CLASS));
lbu(tmp, Address(tmp, Klass::misc_flags_offset()));
test_bit(tmp, tmp, exact_log2(KlassFlags::_misc_is_value_based_class));
bnez(tmp, slow_case);
}

Expand Down
6 changes: 3 additions & 3 deletions src/hotspot/cpu/riscv/templateTable_riscv.cpp
Original file line number Diff line number Diff line change
@@ -1,5 +1,5 @@
/*
* Copyright (c) 2003, 2023, Oracle and/or its affiliates. All rights reserved.
* Copyright (c) 2003, 2024, Oracle and/or its affiliates. All rights reserved.
* Copyright (c) 2014, Red Hat Inc. All rights reserved.
* Copyright (c) 2020, 2023, Huawei Technologies Co., Ltd. All rights reserved.
* DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
Expand Down Expand Up @@ -2098,9 +2098,9 @@ void TemplateTable::_return(TosState state) {

__ ld(c_rarg1, aaddress(0));
__ load_klass(x13, c_rarg1);
__ lwu(x13, Address(x13, Klass::access_flags_offset()));
__ lbu(x13, Address(x13, Klass::misc_flags_offset()));
Label skip_register_finalizer;
__ test_bit(t0, x13, exact_log2(JVM_ACC_HAS_FINALIZER));
__ test_bit(t0, x13, exact_log2(KlassFlags::_misc_has_finalizer));
__ beqz(t0, skip_register_finalizer);

__ call_VM(noreg, CAST_FROM_FN_PTR(address, InterpreterRuntime::register_finalizer), c_rarg1);
Expand Down
2 changes: 1 addition & 1 deletion src/hotspot/cpu/s390/c1_MacroAssembler_s390.cpp
Original file line number Diff line number Diff line change
Expand Up @@ -72,7 +72,7 @@ void C1_MacroAssembler::lock_object(Register Rmark, Register Roop, Register Rbox

if (DiagnoseSyncOnValueBasedClasses != 0) {
load_klass(tmp, Roop);
testbit(Address(tmp, Klass::access_flags_offset()), exact_log2(JVM_ACC_IS_VALUE_BASED_CLASS));
z_tm(Address(tmp, Klass::misc_flags_offset()), KlassFlags::_misc_is_value_based_class);
branch_optimized(Assembler::bcondAllOne, slow_case);
}

Expand Down
4 changes: 2 additions & 2 deletions src/hotspot/cpu/s390/c1_Runtime1_s390.cpp
Original file line number Diff line number Diff line change
@@ -1,5 +1,5 @@
/*
* Copyright (c) 2016, 2023, Oracle and/or its affiliates. All rights reserved.
* Copyright (c) 2016, 2024, Oracle and/or its affiliates. All rights reserved.
* Copyright (c) 2016, 2023 SAP SE. All rights reserved.
* DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
*
Expand Down Expand Up @@ -443,7 +443,7 @@ OopMapSet* Runtime1::generate_code_for(StubID id, StubAssembler* sasm) {
// Load the klass and check the has finalizer flag.
Register klass = Z_ARG2;
__ load_klass(klass, Z_ARG1);
__ testbit(Address(klass, Klass::access_flags_offset()), exact_log2(JVM_ACC_HAS_FINALIZER));
__ z_tm(Address(klass, Klass::misc_flags_offset()), KlassFlags::_misc_has_finalizer);
__ z_bcr(Assembler::bcondAllZero, Z_R14); // Return if bit is not set.

OopMap* oop_map = save_live_registers(sasm);
Expand Down
2 changes: 1 addition & 1 deletion src/hotspot/cpu/s390/interp_masm_s390.cpp
Original file line number Diff line number Diff line change
Expand Up @@ -1007,7 +1007,7 @@ void InterpreterMacroAssembler::lock_object(Register monitor, Register object) {

if (DiagnoseSyncOnValueBasedClasses != 0) {
load_klass(tmp, object);
testbit(Address(tmp, Klass::access_flags_offset()), exact_log2(JVM_ACC_IS_VALUE_BASED_CLASS));
z_tm(Address(tmp, Klass::misc_flags_offset()), KlassFlags::_misc_is_value_based_class);
z_btrue(slow_case);
}

Expand Down
8 changes: 2 additions & 6 deletions src/hotspot/cpu/s390/macroAssembler_s390.cpp
Original file line number Diff line number Diff line change
Expand Up @@ -3507,9 +3507,7 @@ void MacroAssembler::compiler_fast_lock_object(Register oop, Register box, Regis

if (DiagnoseSyncOnValueBasedClasses != 0) {
load_klass(temp, oop);
z_l(temp, Address(temp, Klass::access_flags_offset()));
assert((JVM_ACC_IS_VALUE_BASED_CLASS & 0xFFFF) == 0, "or change following instruction");
z_nilh(temp, JVM_ACC_IS_VALUE_BASED_CLASS >> 16);
z_tm(Address(temp, Klass::misc_flags_offset()), KlassFlags::_misc_is_value_based_class);
z_brne(done);
}

Expand Down Expand Up @@ -6154,9 +6152,7 @@ void MacroAssembler::compiler_fast_lock_lightweight_object(Register obj, Registe

if (DiagnoseSyncOnValueBasedClasses != 0) {
load_klass(tmp1, obj);
z_l(tmp1, Address(tmp1, Klass::access_flags_offset()));
assert((JVM_ACC_IS_VALUE_BASED_CLASS & 0xFFFF) == 0, "or change following instruction");
z_nilh(tmp1, JVM_ACC_IS_VALUE_BASED_CLASS >> 16);
z_tm(Address(tmp1, Klass::misc_flags_offset()), KlassFlags::_misc_is_value_based_class);
z_brne(slow_path);
}

Expand Down
2 changes: 1 addition & 1 deletion src/hotspot/cpu/s390/templateTable_s390.cpp
Original file line number Diff line number Diff line change
Expand Up @@ -2321,7 +2321,7 @@ void TemplateTable::_return(TosState state) {
assert(state == vtos, "only valid state");
__ z_lg(Rthis, aaddress(0));
__ load_klass(Rklass, Rthis);
__ testbit(Address(Rklass, Klass::access_flags_offset()), exact_log2(JVM_ACC_HAS_FINALIZER));
__ z_tm(Address(Rklass, Klass::misc_flags_offset()), KlassFlags::_misc_has_finalizer);
__ z_bfalse(skip_register_finalizer);
__ call_VM(noreg, CAST_FROM_FN_PTR(address, InterpreterRuntime::register_finalizer), Rthis);
__ bind(skip_register_finalizer);
Expand Down
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