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8259822: [PPC64] Support the prefixed instruction format added in POWER10 #2095

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wants to merge 11 commits into from
@@ -60,7 +60,7 @@ bool Assembler::in_scratch_emit_size() {
#ifdef COMPILER2
Thread* thread = Thread::current();

if(!thread->is_Compiler_thread()) return false;
if (!thread->is_Compiler_thread()) return false;

AbstractCompiler* comp = ((CompilerThread *)thread)->compiler();

@@ -811,7 +811,7 @@ class Assembler : public AbstractAssembler {
PREFIX_OPCODE_TYPEx0_MASK = PREFIX_OPCODE_TYPE_MASK | ( 1u << PRE_ST1_SHIFT),
PREFIX_OPCODE_TYPEx1_MASK = PREFIX_OPCODE_TYPE_MASK | (15u << PRE_ST4_SHIFT),

//Masks for each instructions
// Masks for each instructions
PADDI_PREFIX_OPCODE_MASK = PREFIX_OPCODE_TYPEx0_MASK,
PADDI_SUFFIX_OPCODE_MASK = ADDI_OPCODE_MASK,
};
@@ -1109,7 +1109,7 @@ class Assembler : public AbstractAssembler {
static int inv_bo_field(int x) { return inv_opp_u_field(x, 10, 6); }
static int inv_bi_field(int x) { return inv_opp_u_field(x, 15, 11); }

// support to extended opcodes (prefixed instructions) introduced by POWER10
// For extended opcodes (prefixed instructions) introduced with Power 10
static long inv_r_eo( int x) { return inv_opp_u_field(x, 11, 11); }
static long inv_type( int x) { return inv_opp_u_field(x, 7, 6); }
static long inv_st_x0( int x) { return inv_opp_u_field(x, 8, 8); }
@@ -1244,7 +1244,7 @@ class Assembler : public AbstractAssembler {
static int vcmp_rc( int x) { return opp_u_field(x, 21, 21); } // for vcmp* instructions
static int xxsplt_uim(int x) { return opp_u_field(x, 15, 14); } // for xxsplt* instructions

// support to extended opcodes (prefixed instructions) introduced by POWER10
// For extended opcodes (prefixed instructions) introduced with Power 10
static long r_eo( int x) { return opp_u_field(x, 11, 11); }
static long type( int x) { return opp_u_field(x, 7, 6); }
static long st_x0( int x) { return opp_u_field(x, 8, 8); }
@@ -1306,15 +1306,15 @@ class Assembler : public AbstractAssembler {
static inline int lo16_unsigned(int x) { return x & 0xffff; }

static void set_imm18(int* instr, int s) {
assert(PowerArchitecturePPC64 >= 10, "Prefixed instruction is supported in POWER10 and up");
assert(PowerArchitecturePPC64 >= 10, "Prefixed instructions are supported only in Power 10 and up");
// imm18 is in the lower 18 bits of the prefix instruction,
// so this is endian-neutral. Same for the get_imm18 below.
uint32_t w = *(uint32_t *)instr;
*instr = (int)((w & ~0x0003FFFF) | (s & 0x0003FFFF));
}

static int get_imm18(address a, int instruction_number) {
assert(PowerArchitecturePPC64 >= 10, "Prefixed instruction is supported in POWER10 and up");
assert(PowerArchitecturePPC64 >= 10, "Prefixed instructions are supported only in Power 10 and up");
return (((int *)a)[instruction_number] << 14) >> 14;
}

@@ -1346,7 +1346,7 @@ class Assembler : public AbstractAssembler {
}

inline void emit_int32(int); // shadows AbstractAssembler::emit_int32
inline void emit_prefix(int); // emit prefix word only (and a nop to skip 64byte boundary)
inline void emit_prefix(int); // emit prefix word only (and a nop to skip 64-byte boundary)

This comment has been minimized.

@TheRealMDoerr

TheRealMDoerr Mar 24, 2021
Contributor

Unused.

inline void emit_data(int);
inline void emit_data(int, RelocationHolder const&);
inline void emit_data(int, relocInfo::relocType rtype);
@@ -38,7 +38,7 @@ inline void Assembler::emit_prefix(int x) {
assert((x & PREFIX_OPCODE_MASK) == PREFIX_PRIMARY_OPCODE || (x & PREFIX_OPCODE_MASK) == 0,
"Unexpected primary opcode for prefix word");

// Add nop if a prefixed (two-word) instruction is going to cross 64-byte boundaries.
// Add nop if a prefixed (two-word) instruction is going to cross a 64-byte boundary.
// (See Section 1.6 of Power ISA Version 3.1)
if(is_aligned(reinterpret_cast<uintptr_t>(pc()) + sizeof(int32_t), 64) ||

This comment has been minimized.

@CoreyAshford

CoreyAshford Feb 1, 2021

add space after 'if'

Assembler::in_scratch_emit_size()) {
@@ -5838,11 +5838,10 @@ instruct loadConI32(iRegIdst dst, immI32 src) %{
match(Set dst src);
ins_cost(DEFAULT_COST+1);

format %{ "(nop if crossing 64byte boundary)\n\t"
format %{ "(nop if crossing a 64-byte boundary)\n\t"
"PLI $dst, $src" %}
size(12);
ins_encode %{
// TODO: PPC port $archOpcode(ppc64Opcode_paddi);
__ pli($dst$$Register, $src$$constant);
%}
ins_pipe(pipe_class_default);
@@ -5928,7 +5927,6 @@ instruct loadConL34(iRegLdst dst, immL34 src) %{
"PLI $dst, $src \t// long" %}
size(12);
ins_encode %{
// TODO: PPC port $archOpcode(ppc64Opcode_paddi);
__ pli($dst$$Register, $src$$constant);
%}
ins_pipe(pipe_class_default);
@@ -8577,7 +8575,6 @@ instruct addI_reg_imm32(iRegIdst dst, iRegIsrc src1, immI32 src2) %{
"PADDI $dst, $src1, $src2" %}
size(12);
ins_encode %{
// TODO: PPC port $archOpcode(ppc64Opcode_paddi);
__ paddi($dst$$Register, $src1$$Register, $src2$$constant);
%}
ins_pipe(pipe_class_default);
@@ -8668,7 +8665,6 @@ instruct addL_reg_imm34(iRegLdst dst, iRegLsrc src1, immL34 src2) %{
"PADDI $dst, $src1, $src2" %}
size(12);
ins_encode %{
// TODO: PPC port $archOpcode(ppc64Opcode_paddi);
__ paddi($dst$$Register, $src1$$Register, $src2$$constant);
%}
ins_pipe(pipe_class_default);
@@ -8722,7 +8718,6 @@ instruct addP_reg_imm34(iRegPdst dst, iRegP_N2P src1, immL34 src2) %{
"PADDI $dst, $src1, $src2" %}
size(12);
ins_encode %{
// TODO: PPC port $archOpcode(ppc64Opcode_addi);
__ paddi($dst$$Register, $src1$$Register, $src2$$constant);
%}
ins_pipe(pipe_class_default);
@@ -12050,14 +12045,14 @@ instruct cmprb_Whitespace_reg_reg(iRegIdst dst, iRegIsrc src1, iRegIsrc src2, fl
ins_pipe(pipe_class_default);
%}

// POWER10 version, using prefixed addi to load 32bit constant
// Power 10 version, using prefixed addi to load 32-bit constant
instruct cmprb_Whitespace_reg_reg_prefixed(iRegIdst dst, iRegIsrc src1, iRegIsrc src2, flagsReg crx) %{
match(Set dst (Whitespace src1));
predicate(PowerArchitecturePPC64 >= 10);
effect(TEMP src2, TEMP crx);
ins_cost(3 * DEFAULT_COST);

format %{ "(nop if crossing 64byte boundary)\n\t"
format %{ "(nop if crossing a 64-byte boundary)\n\t"
"PLI $src2, 0x201C0D09\n\t"
"CMPRB $crx, 1, $src1, $src2\n\t"
"SETB $dst, $crx" %}
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