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8259822: [PPC64] Support the prefixed instruction format added in POWER10 #2095

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wants to merge 11 commits into from
@@ -60,7 +60,9 @@ bool Assembler::in_scratch_emit_size() {
#ifdef COMPILER2
Thread* thread = Thread::current();

if (!thread->is_Compiler_thread()) return false;
if (!thread->is_Compiler_thread()) {
return false;
}

AbstractCompiler* comp = ((CompilerThread *)thread)->compiler();

@@ -1110,18 +1110,18 @@ class Assembler : public AbstractAssembler {
static int inv_bi_field(int x) { return inv_opp_u_field(x, 15, 11); }

// For extended opcodes (prefixed instructions) introduced with Power 10
static long inv_r_eo( int x) { return inv_opp_u_field(x, 11, 11); }
static long inv_type( int x) { return inv_opp_u_field(x, 7, 6); }
static long inv_st_x0( int x) { return inv_opp_u_field(x, 8, 8); }
static long inv_st_x1( int x) { return inv_opp_u_field(x, 11, 8); }
static long inv_r_eo( int x) { return inv_opp_u_field(x, 11, 11); }
static long inv_type( int x) { return inv_opp_u_field(x, 7, 6); }
static long inv_st_x0( int x) { return inv_opp_u_field(x, 8, 8); }
static long inv_st_x1( int x) { return inv_opp_u_field(x, 11, 8); }

// - 8LS:D/MLS:D Formats
static long inv_d0_eo( long x) { return inv_opp_u_field(x, 31, 14); }
static long inv_d0_eo( long x) { return inv_opp_u_field(x, 31, 14); }

// - 8RR:XX4/8RR:D Formats
static long inv_imm0_eo( int x) { return inv_opp_u_field(x, 31, 16); }
static long inv_uimm_eo( int x) { return inv_opp_u_field(x, 31, 29); }
static long inv_imm_eo( int x) { return inv_opp_u_field(x, 31, 24); }
static long inv_imm0_eo(int x) { return inv_opp_u_field(x, 31, 16); }
static long inv_uimm_eo(int x) { return inv_opp_u_field(x, 31, 29); }
static long inv_imm_eo( int x) { return inv_opp_u_field(x, 31, 24); }

#define opp_u_field(x, hi_bit, lo_bit) u_field(x, 31-(lo_bit), 31-(hi_bit))
#define opp_s_field(x, hi_bit, lo_bit) s_field(x, 31-(lo_bit), 31-(hi_bit))
@@ -1318,8 +1318,8 @@ class Assembler : public AbstractAssembler {
return (((int *)a)[instruction_number] << 14) >> 14;
}

static inline int hi18_signed( int x) { return hi16_signed(x); }
static inline int hi18_signed( long x) { return (int)((x << 30) >> 46); }
static inline int hi18_signed( int x) { return hi16_signed(x); }
static inline int hi18_signed(long x) { return (int)((x << 30) >> 46); }

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@TheRealMDoerr

TheRealMDoerr Mar 24, 2021
Contributor

Sees like they are unused and should get removed.


protected:

@@ -1384,9 +1384,6 @@ class Assembler : public AbstractAssembler {
// Prefixed add immediate, introduced by POWER10
inline void paddi(Register d, Register a, long si34, bool r);
inline void pli( Register d, long si34);
inline void pla( Register d, long si34);
inline void pla( Register d, Register a, long si34);
inline void psubi(Register d, Register a, long si34);

private:
inline void addi_r0ok( Register d, Register a, int si16);
@@ -40,7 +40,7 @@ inline void Assembler::emit_prefix(int x) {

// Add nop if a prefixed (two-word) instruction is going to cross a 64-byte boundary.
// (See Section 1.6 of Power ISA Version 3.1)
if(is_aligned(reinterpret_cast<uintptr_t>(pc()) + sizeof(int32_t), 64) ||
if (is_aligned(reinterpret_cast<uintptr_t>(pc()) + sizeof(int32_t), 64) ||
Assembler::in_scratch_emit_size()) {
Assembler::nop();
}
@@ -144,12 +144,12 @@ inline void Assembler::divwu( Register d, Register a, Register b) { emit_int32(
inline void Assembler::divwu_( Register d, Register a, Register b) { emit_int32(DIVWU_OPCODE | rt(d) | ra(a) | rb(b) | oe(0) | rc(1)); }

// Prefixed instructions, introduced by POWER10
inline void Assembler::paddi( Register d, Register a, long si34, bool r = false) {
inline void Assembler::paddi(Register d, Register a, long si34, bool r = false) {
assert(a != R0 || r, "r0 not allowed, unless R is set (CIA relative)");
paddi_r0ok( d, a, si34, r);

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@CoreyAshford

CoreyAshford Feb 1, 2021

The space after the ( isn't needed here, since it's not aligning with a similar call above or below.

This comment has been minimized.

@TheRealMDoerr

TheRealMDoerr Mar 23, 2021
Contributor

Right, please remove extra spaces.

}

inline void Assembler::paddi_r0ok( Register d, Register a, long si34, bool r = false) {
inline void Assembler::paddi_r0ok(Register d, Register a, long si34, bool r = false) {
emit_prefix(PADDI_PREFIX_OPCODE | r_eo(r) | d0_eo(si34));
emit_int32( PADDI_SUFFIX_OPCODE | rt(d) | ra(a) | d1_eo(si34));
}
@@ -193,10 +193,7 @@ inline void Assembler::addir(Register d, int si16, Register a) { Assembler::addi
inline void Assembler::subi( Register d, Register a, int si16) { Assembler::addi(d, a, -si16); }

// Prefixed instructions, introduced by POWER10
inline void Assembler::pli( Register d, long si34) { Assembler::paddi_r0ok( d, R0, si34, false); }
inline void Assembler::pla( Register d, long si34) { Assembler::paddi_r0ok( d, R0, si34, true); }
inline void Assembler::pla( Register d, Register a, long si34) { Assembler::paddi( d, a, si34, false); }
inline void Assembler::psubi(Register d, Register a, long si34) { Assembler::paddi( d, a, -si34, false); }
inline void Assembler::pli(Register d, long si34) { Assembler::paddi_r0ok( d, R0, si34, false); }

// PPC 1, section 3.3.9, Fixed-Point Compare Instructions
inline void Assembler::cmpi( ConditionRegister f, int l, Register a, int si16) { emit_int32( CMPI_OPCODE | bf(f) | l10(l) | ra(a) | simm(si16,16)); }
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