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8335367: [s390] Add support for load immediate on condition instructions. #22058

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mmatti-sw wants to merge 4 commits into from
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8335367: [s390] Add support for load immediate on condition instructions. #22058

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eb33409
Add support for load immediate on condition instructions
mmatti-sw Nov 13, 2024
c1e1365
Update
mmatti-sw Nov 13, 2024
31709a7
Update src/hotspot/cpu/s390/assembler_s390.hpp
mmatti-sw Nov 28, 2024
9f5f396
Updated based on review comments from Lutz.
mmatti-sw Dec 2, 2024
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14 changes: 12 additions & 2 deletions src/hotspot/cpu/s390/assembler_s390.hpp
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Original file line number Diff line number Diff line change
Expand Up @@ -637,6 +637,11 @@ class Assembler : public AbstractAssembler {
#define LCDBR_ZOPC (unsigned int)(179 << 24 | 19 << 16)
#define LCXBR_ZOPC (unsigned int)(179 << 24 | 67 << 16)

// Load Halfword Immediate on Condition
#define LOCHI_ZOPC (unsigned long)(0xECL << 40 | 0x42L)
#define LOCHHI_ZOPC (unsigned long)(0xECL << 40 | 0x4EL)
#define LOCGHI_ZOPC (unsigned long)(0xECL << 40 | 0x46L)

// Add
// RR, signed
#define AR_ZOPC (unsigned int)(26 << 8)
Expand Down Expand Up @@ -987,8 +992,8 @@ class Assembler : public AbstractAssembler {
#define BASR_ZOPC (unsigned int)(13 << 8)
#define BCT_ZOPC (unsigned int)(70 << 24)
#define BCTR_ZOPC (unsigned int)(6 << 8)
#define BCTG_ZOPC (unsigned int)(227L << 40 | 70)
#define BCTGR_ZOPC (unsigned long)(0xb946 << 16)
#define BCTG_ZOPC (unsigned long)(227L << 40 | 70)
#define BCTGR_ZOPC (unsigned int)(0xb946 << 16)
// Absolute
#define BC_ZOPC (unsigned int)(71 << 24)
#define BAL_ZOPC (unsigned int)(69 << 24)
Expand Down Expand Up @@ -2065,6 +2070,11 @@ class Assembler : public AbstractAssembler {
inline void z_llilh(Register r1, int64_t i2); // r1 = i2_imm16 ; uint64 <- (uint16<<16)
inline void z_llill(Register r1, int64_t i2); // r1 = i2_imm16 ; uint64 <- uint16

// load halfword immediate on condition
inline void z_lochi( Register r1, int64_t i2, branch_condition m3); // load immediate r1[32-63] = i2_simm16 ; int32 <- int16
inline void z_lochhi(Register r1, int64_t i2, branch_condition m3); // load immediate r1[ 0-31] = i2_simm16 ; int32 <- int16
inline void z_locghi(Register r1, int64_t i2, branch_condition m3); // load immediate r1[ 0-63] = i2_simm16 ; int64 <- int16

// insert immediate
inline void z_ic( Register r1, int64_t d2, Register x2, Register b2); // insert character
inline void z_icy( Register r1, int64_t d2, Register x2, Register b2); // insert character
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5 changes: 5 additions & 0 deletions src/hotspot/cpu/s390/assembler_s390.inline.hpp
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Expand Up @@ -245,6 +245,11 @@ inline void Assembler::z_stcm (Register r1, int64_t m3, int64_t d2, Register b2)
inline void Assembler::z_stcmy(Register r1, int64_t m3, int64_t d2, Register b2) { emit_48( STCMY_ZOPC | regt(r1, 8, 48) | uimm4(m3, 12, 48) | rsymask_48(d2, b2)); }
inline void Assembler::z_stcmh(Register r1, int64_t m3, int64_t d2, Register b2) { emit_48( STCMH_ZOPC | regt(r1, 8, 48) | uimm4(m3, 12, 48) | rsymask_48(d2, b2)); }

// load halfword immediate on condition
inline void Assembler::z_lochi(Register r1, int64_t i2, branch_condition m3) { emit_48( LOCHI_ZOPC | reg(r1, 8, 48) | simm16(i2, 16, 48) | uimm4(m3, 12, 48)); }
inline void Assembler::z_lochhi(Register r1, int64_t i2, branch_condition m3) { emit_48( LOCHHI_ZOPC | reg(r1, 8, 48) | simm16(i2, 16, 48) | uimm4(m3, 12, 48)); }
inline void Assembler::z_locghi(Register r1, int64_t i2, branch_condition m3) { emit_48( LOCGHI_ZOPC | reg(r1, 8, 48) | simm16(i2, 16, 48) | uimm4(m3, 12, 48)); }

// memory-immediate instructions (8-bit immediate)
inline void Assembler::z_cli( int64_t d1, Register b1, int64_t i2) { emit_32( CLI_ZOPC | rsmask_32( d1, b1) | uimm8(i2, 8, 32)); }
inline void Assembler::z_mvi( int64_t d1, Register b1, int64_t i2) { emit_32( MVI_ZOPC | rsmask_32( d1, b1) | imm8(i2, 8, 32)); }
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2 changes: 1 addition & 1 deletion src/hotspot/cpu/s390/macroAssembler_s390.cpp
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Expand Up @@ -3287,7 +3287,7 @@ void MacroAssembler::lookup_secondary_supers_table(Register r_sub_klass,
z_bru(L_done); // pass whatever result we got from a slow path

bind(L_failure);
// TODO: use load immediate on condition and z_bru above will not be required

z_lghi(r_result, 1);
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@RealLucy RealLucy Nov 29, 2024

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This lghi deserves a conversion to locghi. Furthermore, without checking for feature availability, the code will require z13 or newer. Is that intended?

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@offamitkumar offamitkumar Nov 29, 2024

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yeah, actually that was my intention but then I find out that codepath which jumps to L_failure not comes with setting cc to 2.

  testbit(r_array_index, 63);
  z_bfalse(L_failure);

  testbit(r_bitmap, (bit + 1) & Klass::SECONDARY_SUPERS_TABLE_MASK);
  z_bfalse(L_failure);

So other solution which I could think of is, to assume that search will fail and load 1 at the start

  // Initialize r_result with 0 (indicating success). If searching fails, r_result will be loaded
  // with 1 (failure) at the end of this method.
  clear_reg(r_result, true /* whole_reg */, false /* set_cc */); // r_result = 0

But then I remembered this: https://github.com/openjdk/jdk/pull/19544/files#r1660693537

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@offamitkumar offamitkumar Nov 29, 2024

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So other solution which I could think of is, to assume that search will fail and load 1 at the start

with this we can now look for CC = EQ. And use z_locghi(result, 0, Assembler::bcondEqual);

Also now logic for secondary supers table for c1 & interpreter assumes that search will fail and loads 1 at the start. So to be in sync, better we keep it this way :)


bind(L_done);
Expand Down