From 02e156227eb395d7bb7dddf8a70b7cbf4d5bfc28 Mon Sep 17 00:00:00 2001
From: wenanjian <wenanjian@bytedance.com>
Date: Thu, 6 Feb 2025 19:36:58 +0800
Subject: [PATCH 1/7] 8349632:RISC-V: Add Zfa fminm/fmaxm

---
 src/hotspot/cpu/riscv/assembler_riscv.hpp     | 20 ++++++++
 .../cpu/riscv/c2_MacroAssembler_riscv.cpp     | 13 +++++
 .../cpu/riscv/c2_MacroAssembler_riscv.hpp     |  4 ++
 src/hotspot/cpu/riscv/riscv.ad                | 48 ++++++++++++++-----
 4 files changed, 73 insertions(+), 12 deletions(-)

diff --git a/src/hotspot/cpu/riscv/assembler_riscv.hpp b/src/hotspot/cpu/riscv/assembler_riscv.hpp
index 3a638357f0b37..43deb297e4a7e 100644
--- a/src/hotspot/cpu/riscv/assembler_riscv.hpp
+++ b/src/hotspot/cpu/riscv/assembler_riscv.hpp
@@ -1409,6 +1409,26 @@ enum operand_size { int8, int16, int32, uint32, int64 };
     fp_base<D_64_dp, 0b11110>(Rd, Rs1, 0b00001, 0b000);
   }
 
+  void fminm_s(FloatRegister Rd, FloatRegister Rs1, FloatRegister Rs2) {
+    assert_cond(UseZfa);
+    fp_base<S_32_sp, 0b00101>(Rd, Rs1, Rs2, 0b010);
+  }
+
+  void fmaxm_s(FloatRegister Rd, FloatRegister Rs1, FloatRegister Rs2) {
+    assert_cond(UseZfa);
+    fp_base<S_32_sp, 0b00101>(Rd, Rs1, Rs2, 0b011);
+  }
+
+  void fminm_d(FloatRegister Rd, FloatRegister Rs1, FloatRegister Rs2) {
+    assert_cond(UseZfa);
+    fp_base<D_64_dp, 0b00101>(Rd, Rs1, Rs2, 0b010);
+  }
+
+  void fmaxm_d(FloatRegister Rd, FloatRegister Rs1, FloatRegister Rs2) {
+    assert_cond(UseZfa);
+    fp_base<D_64_dp, 0b00101>(Rd, Rs1, Rs2, 0b011);
+  }
+
 // ==========================
 // RISC-V Vector Extension
 // ==========================
diff --git a/src/hotspot/cpu/riscv/c2_MacroAssembler_riscv.cpp b/src/hotspot/cpu/riscv/c2_MacroAssembler_riscv.cpp
index c3296aeb76b33..0334c2210e45f 100644
--- a/src/hotspot/cpu/riscv/c2_MacroAssembler_riscv.cpp
+++ b/src/hotspot/cpu/riscv/c2_MacroAssembler_riscv.cpp
@@ -2156,6 +2156,19 @@ void C2_MacroAssembler::minmax_fp(FloatRegister dst, FloatRegister src1, FloatRe
   bind(Done);
 }
 
+void C2_MacroAssembler::minmmaxm_fp(FloatRegister dst, FloatRegister src1, FloatRegister src2,
+                                  bool is_double, bool is_min) {
+  assert_different_registers(dst, src1, src2);
+
+  if (is_double) {
+    is_min ? fminm_d(dst, src1, src2)
+           : fmaxm_d(dst, src1, src2);
+  } else {
+    is_min ? fminm_s(dst, src1, src2)
+           : fmaxm_s(dst, src1, src2);
+  }
+}
+
 // According to Java SE specification, for floating-point round operations, if
 // the input is NaN, +/-infinity, or +/-0, the same input is returned as the
 // rounded result; this differs from behavior of RISC-V fcvt instructions (which
diff --git a/src/hotspot/cpu/riscv/c2_MacroAssembler_riscv.hpp b/src/hotspot/cpu/riscv/c2_MacroAssembler_riscv.hpp
index 114ad0a101c23..a453c2c3507e4 100644
--- a/src/hotspot/cpu/riscv/c2_MacroAssembler_riscv.hpp
+++ b/src/hotspot/cpu/riscv/c2_MacroAssembler_riscv.hpp
@@ -167,6 +167,10 @@
                  FloatRegister src1, FloatRegister src2,
                  bool is_double, bool is_min);
 
+  void minmmaxm_fp(FloatRegister dst,
+                   FloatRegister src1, FloatRegister src2,
+                   bool is_double, bool is_min);
+
   void round_double_mode(FloatRegister dst, FloatRegister src, int round_mode,
                          Register tmp1, Register tmp2, Register tmp3);
 
diff --git a/src/hotspot/cpu/riscv/riscv.ad b/src/hotspot/cpu/riscv/riscv.ad
index b8660afb5fd4f..42c278b84ff95 100644
--- a/src/hotspot/cpu/riscv/riscv.ad
+++ b/src/hotspot/cpu/riscv/riscv.ad
@@ -7292,9 +7292,15 @@ instruct maxF_reg_reg(fRegF dst, fRegF src1, fRegF src2, rFlagsReg cr) %{
   format %{ "maxF $dst, $src1, $src2" %}
 
   ins_encode %{
-    __ minmax_fp(as_FloatRegister($dst$$reg),
-                 as_FloatRegister($src1$$reg), as_FloatRegister($src2$$reg),
-                 false /* is_double */, false /* is_min */);
+    if (UseZfa) {
+      __ minmmaxm_fp(as_FloatRegister($dst$$reg),
+                     as_FloatRegister($src1$$reg), as_FloatRegister($src2$$reg),
+                     false /* is_double */, false /* is_min */);
+    } else {
+      __ minmax_fp(as_FloatRegister($dst$$reg),
+                   as_FloatRegister($src1$$reg), as_FloatRegister($src2$$reg),
+                   false /* is_double */, false /* is_min */);
+    }
   %}
 
   ins_pipe(pipe_class_default);
@@ -7308,9 +7314,15 @@ instruct minF_reg_reg(fRegF dst, fRegF src1, fRegF src2, rFlagsReg cr) %{
   format %{ "minF $dst, $src1, $src2" %}
 
   ins_encode %{
-    __ minmax_fp(as_FloatRegister($dst$$reg),
-                 as_FloatRegister($src1$$reg), as_FloatRegister($src2$$reg),
-                 false /* is_double */, true /* is_min */);
+    if (UseZfa) {
+      __ minmmaxm_fp(as_FloatRegister($dst$$reg),
+                     as_FloatRegister($src1$$reg), as_FloatRegister($src2$$reg),
+                     false /* is_double */, true /* is_min */);
+    } else {
+      __ minmax_fp(as_FloatRegister($dst$$reg),
+                   as_FloatRegister($src1$$reg), as_FloatRegister($src2$$reg),
+                   false /* is_double */, true /* is_min */);
+    }
   %}
 
   ins_pipe(pipe_class_default);
@@ -7324,9 +7336,15 @@ instruct maxD_reg_reg(fRegD dst, fRegD src1, fRegD src2, rFlagsReg cr) %{
   format %{ "maxD $dst, $src1, $src2" %}
 
   ins_encode %{
-    __ minmax_fp(as_FloatRegister($dst$$reg),
-                 as_FloatRegister($src1$$reg), as_FloatRegister($src2$$reg),
-                 true /* is_double */, false /* is_min */);
+    if (UseZfa) {
+      __ minmmaxm_fp(as_FloatRegister($dst$$reg),
+                     as_FloatRegister($src1$$reg), as_FloatRegister($src2$$reg),
+                     true /* is_double */, false /* is_min */);
+    } else {
+      __ minmax_fp(as_FloatRegister($dst$$reg),
+                   as_FloatRegister($src1$$reg), as_FloatRegister($src2$$reg),
+                   true /* is_double */, false /* is_min */);
+    }
   %}
 
   ins_pipe(pipe_class_default);
@@ -7340,9 +7358,15 @@ instruct minD_reg_reg(fRegD dst, fRegD src1, fRegD src2, rFlagsReg cr) %{
   format %{ "minD $dst, $src1, $src2" %}
 
   ins_encode %{
-    __ minmax_fp(as_FloatRegister($dst$$reg),
-                 as_FloatRegister($src1$$reg), as_FloatRegister($src2$$reg),
-                 true /* is_double */, true /* is_min */);
+    if (UseZfa) {
+      __ minmmaxm_fp(as_FloatRegister($dst$$reg),
+                     as_FloatRegister($src1$$reg), as_FloatRegister($src2$$reg),
+                     true /* is_double */, true /* is_min */);
+    } else {
+      __ minmax_fp(as_FloatRegister($dst$$reg),
+                   as_FloatRegister($src1$$reg), as_FloatRegister($src2$$reg),
+                   true /* is_double */, true /* is_min */);
+    }
   %}
 
   ins_pipe(pipe_class_default);

From 1d22e6fd477fe046f66f38dd8353414d60712671 Mon Sep 17 00:00:00 2001
From: Anjian-Wen <wenanjian@bytedance.com>
Date: Fri, 21 Feb 2025 16:27:57 +0800
Subject: [PATCH 2/7] JDK-8349632: RISCV: Add Zfa fminm/fmaxm

delete assert and change fminm/fmaxm to new match rule
---
 .../cpu/riscv/c2_MacroAssembler_riscv.cpp     |  2 -
 src/hotspot/cpu/riscv/riscv.ad                | 92 +++++++++++++------
 2 files changed, 64 insertions(+), 30 deletions(-)

diff --git a/src/hotspot/cpu/riscv/c2_MacroAssembler_riscv.cpp b/src/hotspot/cpu/riscv/c2_MacroAssembler_riscv.cpp
index 0334c2210e45f..52956c4612b4b 100644
--- a/src/hotspot/cpu/riscv/c2_MacroAssembler_riscv.cpp
+++ b/src/hotspot/cpu/riscv/c2_MacroAssembler_riscv.cpp
@@ -2129,8 +2129,6 @@ void C2_MacroAssembler::enc_cmove(int cmpFlag, Register op1, Register op2, Regis
 // Set dst to NaN if any NaN input.
 void C2_MacroAssembler::minmax_fp(FloatRegister dst, FloatRegister src1, FloatRegister src2,
                                   bool is_double, bool is_min) {
-  assert_different_registers(dst, src1, src2);
-
   Label Done, Compare;
 
   is_double ? fclass_d(t0, src1)
diff --git a/src/hotspot/cpu/riscv/riscv.ad b/src/hotspot/cpu/riscv/riscv.ad
index 42c278b84ff95..712583c758ff8 100644
--- a/src/hotspot/cpu/riscv/riscv.ad
+++ b/src/hotspot/cpu/riscv/riscv.ad
@@ -7286,21 +7286,30 @@ instruct nmaddD_reg_reg(fRegD dst, fRegD src1, fRegD src2, fRegD src3) %{
 
 // Math.max(FF)F
 instruct maxF_reg_reg(fRegF dst, fRegF src1, fRegF src2, rFlagsReg cr) %{
+  predicate(!UseZfa);
   match(Set dst (MaxF src1 src2));
   effect(TEMP_DEF dst, KILL cr);
 
   format %{ "maxF $dst, $src1, $src2" %}
 
   ins_encode %{
-    if (UseZfa) {
-      __ minmmaxm_fp(as_FloatRegister($dst$$reg),
-                     as_FloatRegister($src1$$reg), as_FloatRegister($src2$$reg),
-                     false /* is_double */, false /* is_min */);
-    } else {
-      __ minmax_fp(as_FloatRegister($dst$$reg),
+    __ minmax_fp(as_FloatRegister($dst$$reg),
+                 as_FloatRegister($src1$$reg), as_FloatRegister($src2$$reg),
+                 false /* is_double */, false /* is_min */);
+  %}
+
+  ins_pipe(pipe_class_default);
+%}
+
+instruct maxF_reg_reg_zfa(fRegF dst, fRegF src1, fRegF src2) %{
+  match(Set dst (MaxF src1 src2));
+
+  format %{ "maxF $dst, $src1, $src2" %}
+
+  ins_encode %{
+    __ minmmaxm_fp(as_FloatRegister($dst$$reg),
                    as_FloatRegister($src1$$reg), as_FloatRegister($src2$$reg),
                    false /* is_double */, false /* is_min */);
-    }
   %}
 
   ins_pipe(pipe_class_default);
@@ -7308,21 +7317,30 @@ instruct maxF_reg_reg(fRegF dst, fRegF src1, fRegF src2, rFlagsReg cr) %{
 
 // Math.min(FF)F
 instruct minF_reg_reg(fRegF dst, fRegF src1, fRegF src2, rFlagsReg cr) %{
+  predicate(!UseZfa);
   match(Set dst (MinF src1 src2));
   effect(TEMP_DEF dst, KILL cr);
 
   format %{ "minF $dst, $src1, $src2" %}
 
   ins_encode %{
-    if (UseZfa) {
-      __ minmmaxm_fp(as_FloatRegister($dst$$reg),
-                     as_FloatRegister($src1$$reg), as_FloatRegister($src2$$reg),
-                     false /* is_double */, true /* is_min */);
-    } else {
-      __ minmax_fp(as_FloatRegister($dst$$reg),
+    __ minmax_fp(as_FloatRegister($dst$$reg),
+                 as_FloatRegister($src1$$reg), as_FloatRegister($src2$$reg),
+                 false /* is_double */, true /* is_min */);
+  %}
+
+  ins_pipe(pipe_class_default);
+%}
+
+instruct minF_reg_reg_zfa(fRegF dst, fRegF src1, fRegF src2) %{
+  match(Set dst (MinF src1 src2));
+
+  format %{ "minF $dst, $src1, $src2" %}
+
+  ins_encode %{
+    __ minmmaxm_fp(as_FloatRegister($dst$$reg),
                    as_FloatRegister($src1$$reg), as_FloatRegister($src2$$reg),
                    false /* is_double */, true /* is_min */);
-    }
   %}
 
   ins_pipe(pipe_class_default);
@@ -7330,21 +7348,30 @@ instruct minF_reg_reg(fRegF dst, fRegF src1, fRegF src2, rFlagsReg cr) %{
 
 // Math.max(DD)D
 instruct maxD_reg_reg(fRegD dst, fRegD src1, fRegD src2, rFlagsReg cr) %{
+  predicate(!UseZfa);
   match(Set dst (MaxD src1 src2));
   effect(TEMP_DEF dst, KILL cr);
 
   format %{ "maxD $dst, $src1, $src2" %}
 
   ins_encode %{
-    if (UseZfa) {
-      __ minmmaxm_fp(as_FloatRegister($dst$$reg),
-                     as_FloatRegister($src1$$reg), as_FloatRegister($src2$$reg),
-                     true /* is_double */, false /* is_min */);
-    } else {
-      __ minmax_fp(as_FloatRegister($dst$$reg),
+    __ minmax_fp(as_FloatRegister($dst$$reg),
+                 as_FloatRegister($src1$$reg), as_FloatRegister($src2$$reg),
+                 true /* is_double */, false /* is_min */);
+  %}
+
+  ins_pipe(pipe_class_default);
+%}
+
+instruct maxD_reg_reg_zfa(fRegD dst, fRegD src1, fRegD src2) %{
+  match(Set dst (MaxD src1 src2));
+
+  format %{ "maxD $dst, $src1, $src2" %}
+
+  ins_encode %{
+    __ minmmaxm_fp(as_FloatRegister($dst$$reg),
                    as_FloatRegister($src1$$reg), as_FloatRegister($src2$$reg),
                    true /* is_double */, false /* is_min */);
-    }
   %}
 
   ins_pipe(pipe_class_default);
@@ -7352,21 +7379,30 @@ instruct maxD_reg_reg(fRegD dst, fRegD src1, fRegD src2, rFlagsReg cr) %{
 
 // Math.min(DD)D
 instruct minD_reg_reg(fRegD dst, fRegD src1, fRegD src2, rFlagsReg cr) %{
+  predicate(!UseZfa);
   match(Set dst (MinD src1 src2));
   effect(TEMP_DEF dst, KILL cr);
 
   format %{ "minD $dst, $src1, $src2" %}
 
   ins_encode %{
-    if (UseZfa) {
-      __ minmmaxm_fp(as_FloatRegister($dst$$reg),
-                     as_FloatRegister($src1$$reg), as_FloatRegister($src2$$reg),
-                     true /* is_double */, true /* is_min */);
-    } else {
-      __ minmax_fp(as_FloatRegister($dst$$reg),
+    __ minmax_fp(as_FloatRegister($dst$$reg),
+                 as_FloatRegister($src1$$reg), as_FloatRegister($src2$$reg),
+                 true /* is_double */, true /* is_min */);
+  %}
+
+  ins_pipe(pipe_class_default);
+%}
+
+instruct minD_reg_reg_zfa(fRegD dst, fRegD src1, fRegD src2) %{
+  match(Set dst (MinD src1 src2));
+
+  format %{ "minD $dst, $src1, $src2" %}
+
+  ins_encode %{
+    __ minmmaxm_fp(as_FloatRegister($dst$$reg),
                    as_FloatRegister($src1$$reg), as_FloatRegister($src2$$reg),
                    true /* is_double */, true /* is_min */);
-    }
   %}
 
   ins_pipe(pipe_class_default);

From defa74d4101a6a267799b482924fa6da631995ed Mon Sep 17 00:00:00 2001
From: Anjian-Wen <wenanjian@bytedance.com>
Date: Fri, 21 Feb 2025 16:51:27 +0800
Subject: [PATCH 3/7] 8349632: RISC-V: Add Zfa fminm/fmaxm

delete assert in new add macroAssembly but not the old
---
 src/hotspot/cpu/riscv/c2_MacroAssembler_riscv.cpp | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/src/hotspot/cpu/riscv/c2_MacroAssembler_riscv.cpp b/src/hotspot/cpu/riscv/c2_MacroAssembler_riscv.cpp
index 52956c4612b4b..966267deaba91 100644
--- a/src/hotspot/cpu/riscv/c2_MacroAssembler_riscv.cpp
+++ b/src/hotspot/cpu/riscv/c2_MacroAssembler_riscv.cpp
@@ -2129,6 +2129,8 @@ void C2_MacroAssembler::enc_cmove(int cmpFlag, Register op1, Register op2, Regis
 // Set dst to NaN if any NaN input.
 void C2_MacroAssembler::minmax_fp(FloatRegister dst, FloatRegister src1, FloatRegister src2,
                                   bool is_double, bool is_min) {
+  assert_different_registers(dst, src1, src2);
+
   Label Done, Compare;
 
   is_double ? fclass_d(t0, src1)
@@ -2156,8 +2158,6 @@ void C2_MacroAssembler::minmax_fp(FloatRegister dst, FloatRegister src1, FloatRe
 
 void C2_MacroAssembler::minmmaxm_fp(FloatRegister dst, FloatRegister src1, FloatRegister src2,
                                   bool is_double, bool is_min) {
-  assert_different_registers(dst, src1, src2);
-
   if (is_double) {
     is_min ? fminm_d(dst, src1, src2)
            : fmaxm_d(dst, src1, src2);

From 037a3640b6fc72c3122a87ea8a2ad170f6824fbb Mon Sep 17 00:00:00 2001
From: Anjian-Wen <wenanjian@bytedance.com>
Date: Fri, 21 Feb 2025 19:18:51 +0800
Subject: [PATCH 4/7] JDK-8349632: RISC-V: Add Zfa fminm/fmaxm

add zfa predicate
---
 src/hotspot/cpu/riscv/riscv.ad | 4 ++++
 1 file changed, 4 insertions(+)

diff --git a/src/hotspot/cpu/riscv/riscv.ad b/src/hotspot/cpu/riscv/riscv.ad
index 712583c758ff8..12539097fd7d1 100644
--- a/src/hotspot/cpu/riscv/riscv.ad
+++ b/src/hotspot/cpu/riscv/riscv.ad
@@ -7302,6 +7302,7 @@ instruct maxF_reg_reg(fRegF dst, fRegF src1, fRegF src2, rFlagsReg cr) %{
 %}
 
 instruct maxF_reg_reg_zfa(fRegF dst, fRegF src1, fRegF src2) %{
+  predicate(UseZfa);
   match(Set dst (MaxF src1 src2));
 
   format %{ "maxF $dst, $src1, $src2" %}
@@ -7333,6 +7334,7 @@ instruct minF_reg_reg(fRegF dst, fRegF src1, fRegF src2, rFlagsReg cr) %{
 %}
 
 instruct minF_reg_reg_zfa(fRegF dst, fRegF src1, fRegF src2) %{
+  predicate(UseZfa);
   match(Set dst (MinF src1 src2));
 
   format %{ "minF $dst, $src1, $src2" %}
@@ -7364,6 +7366,7 @@ instruct maxD_reg_reg(fRegD dst, fRegD src1, fRegD src2, rFlagsReg cr) %{
 %}
 
 instruct maxD_reg_reg_zfa(fRegD dst, fRegD src1, fRegD src2) %{
+  predicate(UseZfa);
   match(Set dst (MaxD src1 src2));
 
   format %{ "maxD $dst, $src1, $src2" %}
@@ -7395,6 +7398,7 @@ instruct minD_reg_reg(fRegD dst, fRegD src1, fRegD src2, rFlagsReg cr) %{
 %}
 
 instruct minD_reg_reg_zfa(fRegD dst, fRegD src1, fRegD src2) %{
+  predicate(UseZfa);
   match(Set dst (MinD src1 src2));
 
   format %{ "minD $dst, $src1, $src2" %}

From b763ee4d5144a5fbb73839e647f873a607ef101b Mon Sep 17 00:00:00 2001
From: Anjian-Wen <wenanjian@bytedance.com>
Date: Mon, 24 Feb 2025 10:49:47 +0800
Subject: [PATCH 5/7] 8349632: RISC-V: Add Zfa fminm/fmaxm

Change macro-assembler routine to directly call in riscv.ad
---
 .../cpu/riscv/c2_MacroAssembler_riscv.cpp     | 11 ----------
 .../cpu/riscv/c2_MacroAssembler_riscv.hpp     |  4 ----
 src/hotspot/cpu/riscv/riscv.ad                | 20 ++++++++-----------
 3 files changed, 8 insertions(+), 27 deletions(-)

diff --git a/src/hotspot/cpu/riscv/c2_MacroAssembler_riscv.cpp b/src/hotspot/cpu/riscv/c2_MacroAssembler_riscv.cpp
index 966267deaba91..c3296aeb76b33 100644
--- a/src/hotspot/cpu/riscv/c2_MacroAssembler_riscv.cpp
+++ b/src/hotspot/cpu/riscv/c2_MacroAssembler_riscv.cpp
@@ -2156,17 +2156,6 @@ void C2_MacroAssembler::minmax_fp(FloatRegister dst, FloatRegister src1, FloatRe
   bind(Done);
 }
 
-void C2_MacroAssembler::minmmaxm_fp(FloatRegister dst, FloatRegister src1, FloatRegister src2,
-                                  bool is_double, bool is_min) {
-  if (is_double) {
-    is_min ? fminm_d(dst, src1, src2)
-           : fmaxm_d(dst, src1, src2);
-  } else {
-    is_min ? fminm_s(dst, src1, src2)
-           : fmaxm_s(dst, src1, src2);
-  }
-}
-
 // According to Java SE specification, for floating-point round operations, if
 // the input is NaN, +/-infinity, or +/-0, the same input is returned as the
 // rounded result; this differs from behavior of RISC-V fcvt instructions (which
diff --git a/src/hotspot/cpu/riscv/c2_MacroAssembler_riscv.hpp b/src/hotspot/cpu/riscv/c2_MacroAssembler_riscv.hpp
index a453c2c3507e4..114ad0a101c23 100644
--- a/src/hotspot/cpu/riscv/c2_MacroAssembler_riscv.hpp
+++ b/src/hotspot/cpu/riscv/c2_MacroAssembler_riscv.hpp
@@ -167,10 +167,6 @@
                  FloatRegister src1, FloatRegister src2,
                  bool is_double, bool is_min);
 
-  void minmmaxm_fp(FloatRegister dst,
-                   FloatRegister src1, FloatRegister src2,
-                   bool is_double, bool is_min);
-
   void round_double_mode(FloatRegister dst, FloatRegister src, int round_mode,
                          Register tmp1, Register tmp2, Register tmp3);
 
diff --git a/src/hotspot/cpu/riscv/riscv.ad b/src/hotspot/cpu/riscv/riscv.ad
index 12539097fd7d1..e630db5a90dad 100644
--- a/src/hotspot/cpu/riscv/riscv.ad
+++ b/src/hotspot/cpu/riscv/riscv.ad
@@ -7308,9 +7308,8 @@ instruct maxF_reg_reg_zfa(fRegF dst, fRegF src1, fRegF src2) %{
   format %{ "maxF $dst, $src1, $src2" %}
 
   ins_encode %{
-    __ minmmaxm_fp(as_FloatRegister($dst$$reg),
-                   as_FloatRegister($src1$$reg), as_FloatRegister($src2$$reg),
-                   false /* is_double */, false /* is_min */);
+    __ fmaxm_s(as_FloatRegister($dst$$reg),
+               as_FloatRegister($src1$$reg), as_FloatRegister($src2$$reg));
   %}
 
   ins_pipe(pipe_class_default);
@@ -7340,9 +7339,8 @@ instruct minF_reg_reg_zfa(fRegF dst, fRegF src1, fRegF src2) %{
   format %{ "minF $dst, $src1, $src2" %}
 
   ins_encode %{
-    __ minmmaxm_fp(as_FloatRegister($dst$$reg),
-                   as_FloatRegister($src1$$reg), as_FloatRegister($src2$$reg),
-                   false /* is_double */, true /* is_min */);
+    __ fminm_s(as_FloatRegister($dst$$reg),
+               as_FloatRegister($src1$$reg), as_FloatRegister($src2$$reg));
   %}
 
   ins_pipe(pipe_class_default);
@@ -7372,9 +7370,8 @@ instruct maxD_reg_reg_zfa(fRegD dst, fRegD src1, fRegD src2) %{
   format %{ "maxD $dst, $src1, $src2" %}
 
   ins_encode %{
-    __ minmmaxm_fp(as_FloatRegister($dst$$reg),
-                   as_FloatRegister($src1$$reg), as_FloatRegister($src2$$reg),
-                   true /* is_double */, false /* is_min */);
+    __ fmaxm_d(as_FloatRegister($dst$$reg),
+               as_FloatRegister($src1$$reg), as_FloatRegister($src2$$reg));
   %}
 
   ins_pipe(pipe_class_default);
@@ -7404,9 +7401,8 @@ instruct minD_reg_reg_zfa(fRegD dst, fRegD src1, fRegD src2) %{
   format %{ "minD $dst, $src1, $src2" %}
 
   ins_encode %{
-    __ minmmaxm_fp(as_FloatRegister($dst$$reg),
-                   as_FloatRegister($src1$$reg), as_FloatRegister($src2$$reg),
-                   true /* is_double */, true /* is_min */);
+    __ fminm_d(as_FloatRegister($dst$$reg),
+               as_FloatRegister($src1$$reg), as_FloatRegister($src2$$reg));
   %}
 
   ins_pipe(pipe_class_default);

From faa90708d16cb67cf6a7245575713b07b033d8e3 Mon Sep 17 00:00:00 2001
From: Anjian-Wen <wenanjian@bytedance.com>
Date: Wed, 12 Mar 2025 11:34:56 +0800
Subject: [PATCH 6/7] add temp commit for test

---
 src/hotspot/cpu/riscv/riscv.ad | 1 +
 1 file changed, 1 insertion(+)

diff --git a/src/hotspot/cpu/riscv/riscv.ad b/src/hotspot/cpu/riscv/riscv.ad
index 75bd50d8c0d5d..25a32ab580b6e 100644
--- a/src/hotspot/cpu/riscv/riscv.ad
+++ b/src/hotspot/cpu/riscv/riscv.ad
@@ -7306,6 +7306,7 @@ instruct maxF_reg_reg_zfa(fRegF dst, fRegF src1, fRegF src2) %{
 
   format %{ "maxF $dst, $src1, $src2" %}
 
+  // try add some temp commit for temp test 
   ins_encode %{
     __ fmaxm_s(as_FloatRegister($dst$$reg),
                as_FloatRegister($src1$$reg), as_FloatRegister($src2$$reg));

From 249bcd4dab797adb3fcb627d04bfd1ae2eb9534c Mon Sep 17 00:00:00 2001
From: Anjian-Wen <wenanjian@bytedance.com>
Date: Wed, 12 Mar 2025 11:41:13 +0800
Subject: [PATCH 7/7] delete useless comment

---
 src/hotspot/cpu/riscv/riscv.ad | 1 -
 1 file changed, 1 deletion(-)

diff --git a/src/hotspot/cpu/riscv/riscv.ad b/src/hotspot/cpu/riscv/riscv.ad
index 25a32ab580b6e..75bd50d8c0d5d 100644
--- a/src/hotspot/cpu/riscv/riscv.ad
+++ b/src/hotspot/cpu/riscv/riscv.ad
@@ -7306,7 +7306,6 @@ instruct maxF_reg_reg_zfa(fRegF dst, fRegF src1, fRegF src2) %{
 
   format %{ "maxF $dst, $src1, $src2" %}
 
-  // try add some temp commit for temp test 
   ins_encode %{
     __ fmaxm_s(as_FloatRegister($dst$$reg),
                as_FloatRegister($src1$$reg), as_FloatRegister($src2$$reg));