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0372026
Card table as DCQ
tschatzl Feb 11, 2025
7782295
* remove some commented out debug code
tschatzl Feb 24, 2025
9e26abb
* remove mention of "enqueue" or "enqueuing" for actions related to p…
tschatzl Feb 24, 2025
3004a96
* fix crash when writing dirty cards for memory regions during card t…
tschatzl Feb 24, 2025
b8100b9
* mdoerr review: fix comments in ppc code
tschatzl Feb 24, 2025
0100d8e
* only provide byte map base for JavaThreads
tschatzl Feb 25, 2025
9ef9c5f
* remove unnecessarily added logging
tschatzl Feb 25, 2025
e51eec8
* ayang review 1
tschatzl Feb 28, 2025
7d361fc
* ayang review 1 (ctd)
tschatzl Feb 28, 2025
d87935a
* fix assert
tschatzl Feb 28, 2025
810bf2d
* fix comment (trailing whitespace)
tschatzl Mar 3, 2025
b3dd008
ayang review 2
tschatzl Mar 3, 2025
8f46dc9
* iwalulya initial comments
tschatzl Mar 4, 2025
9e2ee54
* do not change card table base for gc threads during swapping
tschatzl Mar 4, 2025
442d9ea
* iwalulya review 2
tschatzl Mar 4, 2025
fc674f0
* ayang review - fix comment
tschatzl Mar 4, 2025
b4d19d9
iwalulya review
tschatzl Mar 4, 2025
4a97811
ayang review
tschatzl Mar 4, 2025
a457e6e
* fix whitespace
tschatzl Mar 5, 2025
350a4fa
* iwalulya review
tschatzl Mar 6, 2025
c994000
* ayang review 3
tschatzl Mar 7, 2025
93b884f
* fix card table verification crashes: in the first refinement phase,…
tschatzl Mar 8, 2025
758fac0
* optimized RISCV gen_write_ref_array_post_barrier() implementation c…
tschatzl Mar 11, 2025
aec9505
Merge branch 'master' into 8342382-card-table-instead-of-dcq
tschatzl Mar 12, 2025
3766b76
* ayang review
tschatzl Mar 12, 2025
7861117
* when aborting refinement during full collection, the global card ta…
tschatzl Mar 13, 2025
51a9eed
* ayang review
tschatzl Mar 14, 2025
b073017
Merge branch 'master' into 8342381-card-table-instead-of-dcq
tschatzl Mar 14, 2025
447fe39
* more documentation on why we need to rendezvous the gc threads
tschatzl Mar 15, 2025
4d0afd5
* obsolete G1UpdateBufferSize
tschatzl Mar 17, 2025
ff9eb26
Merge branch 'master' into 8342382-card-table-instead-of-dcq3
tschatzl Mar 18, 2025
c833bc8
* factor out card table and refinement table merging into a single
tschatzl Mar 18, 2025
f419556
* fix IR code generation tests that change due to barrier cost changes
tschatzl Mar 19, 2025
5e76a51
* make young gen length revising independent of refinement thread
tschatzl Mar 20, 2025
d931104
Merge branch 'master' into submit/8342382-card-table-instead-of-dcq
tschatzl Mar 21, 2025
6d574da
Merge branch 'master' into 8342382-card-table-instead-of-dcq
tschatzl Mar 26, 2025
51fb6e6
Merge branch 'master' into 8342382-card-table-instead-of-dcq
tschatzl Apr 1, 2025
27b3dd6
Merge branch 'master' into 8342382-card-table-instead-of-dcq
tschatzl Apr 4, 2025
1c5a669
* missing file from merge
tschatzl Apr 4, 2025
c5d5f3a
Reorder includes
robcasloz Apr 9, 2025
9481821
Refine needs_liveness_data
robcasloz Apr 9, 2025
855ec8d
Do not unnecessarily pass around tmp2 in x86
robcasloz Apr 9, 2025
d4649ed
* ayang review: revising young gen length
tschatzl Apr 9, 2025
63b1de8
Merge branch 'master' into 8342382-card-table-instead-of-dcq
tschatzl Apr 10, 2025
39aa903
* fixes after merge related to 32 bit x86 removal
tschatzl Apr 10, 2025
fcf96a2
Merge branch 'master' into 8342382-card-table-instead-of-dcq
tschatzl Apr 10, 2025
fd77531
* remove support for 32 bit x86 in the barrier generation code, follo…
tschatzl Apr 10, 2025
068d2a3
* indentation fix
tschatzl Apr 10, 2025
e683152
* ayang review (part 1)
tschatzl Apr 11, 2025
a3b2386
* ayang review (part 2 - yield duration changes)
tschatzl Apr 11, 2025
e4bf1ac
Merge branch 'master' into 8342382-card-table-instead-of-dcq
tschatzl Apr 23, 2025
51dfbe5
Merge branch 'master' into card-table-as-dcq-merge
tschatzl Apr 29, 2025
8b56880
* ayang review: remove sweep_epoch
tschatzl Apr 29, 2025
1def83a
Merge branch 'master' into 8342382-card-table-instead-of-dcq
tschatzl May 15, 2025
c07a73d
Merge branch 'master' into 8342382-card-table-instead-of-dcq
tschatzl Jun 10, 2025
750ed2d
Merge branch 'master' into 8342382-card-table-instead-of-dcq
tschatzl Jun 27, 2025
441c234
Merge branch 'master' into 8342382-card-table-instead-of-dcq
tschatzl Jul 7, 2025
5ab928e
Merge branch 'master' into pull/23739
tschatzl Jul 14, 2025
4b21868
Merge branch 'master' into 8342382-card-table-instead-of-dcq
tschatzl Jul 17, 2025
cea0e1b
Merge branch 'master' into 8342382-card-table-instead-of-dcq
tschatzl Jul 23, 2025
dd83638
* remove unused G1DetachedRefinementStats_lock
tschatzl Jul 23, 2025
23aa2c8
Merge branch 'master' into 8342382-card-table-instead-of-dcq
tschatzl Jul 28, 2025
188fc81
Merge branch 'master' into 8342382-card-table-instead-of-dcq
tschatzl Aug 5, 2025
7fe518e
Merge branch 'master' into 8342382-card-table-instead-of-dcq
tschatzl Aug 12, 2025
6c88f1d
Merge branch 'master' into 8342382-card-table-instead-of-dcq
tschatzl Aug 22, 2025
e8a8282
* forgot to actually save the files
tschatzl Aug 22, 2025
cc4b7a0
* fix merge error
tschatzl Aug 22, 2025
4a41b40
Merge branch 'master' into 8342382-card-table-instead-of-dcq
tschatzl Sep 1, 2025
b3873d6
* commit merge changes
tschatzl Sep 1, 2025
104d506
* improve logging for refinement, making it similar to marking logging
tschatzl Sep 3, 2025
2a614a2
Merge branch 'master' into 8342382-card-table-instead-of-dcq
tschatzl Sep 4, 2025
4601bf8
* sort includes
tschatzl Sep 8, 2025
87b4136
* iwalulya: remove confusing comment
tschatzl Sep 10, 2025
e7c3a06
Merge branch 'master' into 8342382-card-table-instead-of-dcq
tschatzl Sep 10, 2025
de1469d
Merge branch 'master' into 8342382-card-table-instead-of-dcq
tschatzl Sep 10, 2025
d0ca906
* aph review, fix some comment
tschatzl Sep 10, 2025
b47c7b0
* walulyai review
tschatzl Sep 10, 2025
c469c13
* walulyai review
tschatzl Sep 10, 2025
74e9240
* therealaph suggestion for avoiding the register aliasin in gen_writ…
tschatzl Sep 12, 2025
1ced9f9
Merge branch 'master' into 8342382-card-table-instead-of-dcq
tschatzl Sep 12, 2025
bf8cab3
* iwalulya review
tschatzl Sep 12, 2025
b5d22d5
Merge branch 'master' into 8342382-card-table-instead-of-dcq
tschatzl Sep 22, 2025
53ef008
* improved gen_write_ref_array_post_barrier() for riscv, contributed …
tschatzl Sep 22, 2025
6e37f8d
* iwalulya: "Amount of" -> "Number of" in new flag description
tschatzl Sep 22, 2025
311bb3e
* walulyai: remove cost_per_pending_card_ms_default array since we on…
tschatzl Sep 22, 2025
d80d690
* walulyai: remove unnecessarily introduced newline
tschatzl Sep 22, 2025
3c889e9
* walulyai: bufferNodeList can be removed
tschatzl Sep 22, 2025
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239 changes: 73 additions & 166 deletions src/hotspot/cpu/aarch64/gc/g1/g1BarrierSetAssembler_aarch64.cpp
Original file line number Diff line number Diff line change
Expand Up @@ -86,15 +86,48 @@ void G1BarrierSetAssembler::gen_write_ref_array_pre_barrier(MacroAssembler* masm
}
}

void G1BarrierSetAssembler::gen_write_ref_array_post_barrier(MacroAssembler* masm, DecoratorSet decorators,
Register start, Register count, Register scratch, RegSet saved_regs) {
__ push(saved_regs, sp);
assert_different_registers(start, count, scratch);
assert_different_registers(c_rarg0, count);
__ mov(c_rarg0, start);
__ mov(c_rarg1, count);
__ call_VM_leaf(CAST_FROM_FN_PTR(address, G1BarrierSetRuntime::write_ref_array_post_entry), 2);
__ pop(saved_regs, sp);
void G1BarrierSetAssembler::gen_write_ref_array_post_barrier(MacroAssembler* masm,
DecoratorSet decorators,
Register start,
Register count,
Register scratch,
RegSet saved_regs) {

Label done;
Label loop;
Label next;

__ cbz(count, done);

// Calculate the number of card marks to set. Since the object might start and
// end within a card, we need to calculate this via the card table indexes of
// the actual start and last addresses covered by the object.
// Temporarily use the count register for the last element address.
__ lea(count, Address(start, count, Address::lsl(LogBytesPerHeapOop))); // end = start + count << LogBytesPerHeapOop
__ sub(count, count, BytesPerHeapOop); // Use last element address for end.

__ lsr(start, start, CardTable::card_shift());
__ lsr(count, count, CardTable::card_shift());
__ sub(count, count, start); // Number of bytes to mark - 1.

// Add card table base offset to start.
__ ldr(scratch, Address(rthread, in_bytes(G1ThreadLocalData::card_table_base_offset())));
__ add(start, start, scratch);

__ bind(loop);
if (UseCondCardMark) {
__ ldrb(scratch, Address(start, count));
// Instead of loading clean_card_val and comparing, we exploit the fact that
// the LSB of non-clean cards is always 0, and the LSB of clean cards 1.
__ tbz(scratch, 0, next);
}
static_assert(G1CardTable::dirty_card_val() == 0, "must be to use zr");
__ strb(zr, Address(start, count));
__ bind(next);
__ subs(count, count, 1);
__ br(Assembler::GE, loop);

__ bind(done);
}

static void generate_queue_test_and_insertion(MacroAssembler* masm, ByteSize index_offset, ByteSize buffer_offset, Label& runtime,
Expand Down Expand Up @@ -202,10 +235,14 @@ void G1BarrierSetAssembler::g1_write_barrier_pre(MacroAssembler* masm,
static void generate_post_barrier_fast_path(MacroAssembler* masm,
const Register store_addr,
const Register new_val,
const Register thread,
const Register tmp1,
const Register tmp2,
Label& done,
bool new_val_may_be_null) {
assert(thread == rthread, "must be");
assert_different_registers(store_addr, new_val, thread, tmp1, tmp2, noreg, rscratch1);

// Does store cross heap regions?
__ eor(tmp1, store_addr, new_val); // tmp1 := store address ^ new value
__ lsr(tmp1, tmp1, G1HeapRegion::LogOfHRGrainBytes); // tmp1 := ((store address ^ new value) >> LogOfHRGrainBytes)
Expand All @@ -214,33 +251,19 @@ static void generate_post_barrier_fast_path(MacroAssembler* masm,
if (new_val_may_be_null) {
__ cbz(new_val, done);
}
// Storing region crossing non-null, is card young?
// Storing region crossing non-null.
__ lsr(tmp1, store_addr, CardTable::card_shift()); // tmp1 := card address relative to card table base
__ load_byte_map_base(tmp2); // tmp2 := card table base address
__ add(tmp1, tmp1, tmp2); // tmp1 := card address
__ ldrb(tmp2, Address(tmp1)); // tmp2 := card
__ cmpw(tmp2, (int)G1CardTable::g1_young_card_val()); // tmp2 := card == young_card_val?
}

static void generate_post_barrier_slow_path(MacroAssembler* masm,
const Register thread,
const Register tmp1,
const Register tmp2,
Label& done,
Label& runtime) {
__ membar(Assembler::StoreLoad); // StoreLoad membar
__ ldrb(tmp2, Address(tmp1)); // tmp2 := card
__ cbzw(tmp2, done);
// Storing a region crossing, non-null oop, card is clean.
// Dirty card and log.
STATIC_ASSERT(CardTable::dirty_card_val() == 0);
__ strb(zr, Address(tmp1)); // *(card address) := dirty_card_val
generate_queue_test_and_insertion(masm,
G1ThreadLocalData::dirty_card_queue_index_offset(),
G1ThreadLocalData::dirty_card_queue_buffer_offset(),
runtime,
thread, tmp1, tmp2, rscratch1);
__ b(done);
Address card_table_addr(thread, in_bytes(G1ThreadLocalData::card_table_base_offset()));
__ ldr(tmp2, card_table_addr); // tmp2 := card table base address
if (UseCondCardMark) {
__ ldrb(rscratch1, Address(tmp1, tmp2)); // rscratch1 := card
// Instead of loading clean_card_val and comparing, we exploit the fact that
// the LSB of non-clean cards is always 0, and the LSB of clean cards 1.
__ tbz(rscratch1, 0, done);
}
static_assert(G1CardTable::dirty_card_val() == 0, "must be to use zr");
__ strb(zr, Address(tmp1, tmp2)); // *(card address) := dirty_card_val
}

void G1BarrierSetAssembler::g1_write_barrier_post(MacroAssembler* masm,
Expand All @@ -249,27 +272,8 @@ void G1BarrierSetAssembler::g1_write_barrier_post(MacroAssembler* masm,
Register thread,
Register tmp1,
Register tmp2) {
assert(thread == rthread, "must be");
assert_different_registers(store_addr, new_val, thread, tmp1, tmp2,
rscratch1);
assert(store_addr != noreg && new_val != noreg && tmp1 != noreg
&& tmp2 != noreg, "expecting a register");

Label done;
Label runtime;

generate_post_barrier_fast_path(masm, store_addr, new_val, tmp1, tmp2, done, true /* new_val_may_be_null */);
// If card is young, jump to done
__ br(Assembler::EQ, done);
generate_post_barrier_slow_path(masm, thread, tmp1, tmp2, done, runtime);

__ bind(runtime);
// save the live input values
RegSet saved = RegSet::of(store_addr);
__ push(saved, sp);
__ call_VM_leaf(CAST_FROM_FN_PTR(address, G1BarrierSetRuntime::write_ref_field_post_entry), tmp1, thread);
__ pop(saved, sp);

generate_post_barrier_fast_path(masm, store_addr, new_val, thread, tmp1, tmp2, done, false /* new_val_may_be_null */);
__ bind(done);
}

Expand Down Expand Up @@ -329,38 +333,10 @@ void G1BarrierSetAssembler::g1_write_barrier_post_c2(MacroAssembler* masm,
Register thread,
Register tmp1,
Register tmp2,
G1PostBarrierStubC2* stub) {
assert(thread == rthread, "must be");
assert_different_registers(store_addr, new_val, thread, tmp1, tmp2,
rscratch1);
assert(store_addr != noreg && new_val != noreg && tmp1 != noreg
&& tmp2 != noreg, "expecting a register");

stub->initialize_registers(thread, tmp1, tmp2);

bool new_val_may_be_null = (stub->barrier_data() & G1C2BarrierPostNotNull) == 0;
generate_post_barrier_fast_path(masm, store_addr, new_val, tmp1, tmp2, *stub->continuation(), new_val_may_be_null);
// If card is not young, jump to stub (slow path)
__ br(Assembler::NE, *stub->entry());

__ bind(*stub->continuation());
}

void G1BarrierSetAssembler::generate_c2_post_barrier_stub(MacroAssembler* masm,
G1PostBarrierStubC2* stub) const {
Assembler::InlineSkippedInstructionsCounter skip_counter(masm);
Label runtime;
Register thread = stub->thread();
Register tmp1 = stub->tmp1(); // tmp1 holds the card address.
Register tmp2 = stub->tmp2();
assert(stub->tmp3() == noreg, "not needed in this platform");

__ bind(*stub->entry());
generate_post_barrier_slow_path(masm, thread, tmp1, tmp2, *stub->continuation(), runtime);

__ bind(runtime);
generate_c2_barrier_runtime_call(masm, stub, tmp1, CAST_FROM_FN_PTR(address, G1BarrierSetRuntime::write_ref_field_post_entry));
__ b(*stub->continuation());
bool new_val_may_be_null) {
Label done;
generate_post_barrier_fast_path(masm, store_addr, new_val, thread, tmp1, tmp2, done, new_val_may_be_null);
__ bind(done);
}

#endif // COMPILER2
Expand Down Expand Up @@ -456,20 +432,19 @@ void G1BarrierSetAssembler::gen_pre_barrier_stub(LIR_Assembler* ce, G1PreBarrier
__ b(*stub->continuation());
}

void G1BarrierSetAssembler::gen_post_barrier_stub(LIR_Assembler* ce, G1PostBarrierStub* stub) {
G1BarrierSetC1* bs = (G1BarrierSetC1*)BarrierSet::barrier_set()->barrier_set_c1();
__ bind(*stub->entry());
assert(stub->addr()->is_register(), "Precondition.");
assert(stub->new_val()->is_register(), "Precondition.");
Register new_val_reg = stub->new_val()->as_register();
__ cbz(new_val_reg, *stub->continuation());
ce->store_parameter(stub->addr()->as_pointer_register(), 0);
__ far_call(RuntimeAddress(bs->post_barrier_c1_runtime_code_blob()->code_begin()));
__ b(*stub->continuation());
}

#undef __

void G1BarrierSetAssembler::g1_write_barrier_post_c1(MacroAssembler* masm,
Register store_addr,
Register new_val,
Register thread,
Register tmp1,
Register tmp2) {
Label done;
generate_post_barrier_fast_path(masm, store_addr, new_val, thread, tmp1, tmp2, done, true /* new_val_may_be_null */);
masm->bind(done);
}

#define __ sasm->

void G1BarrierSetAssembler::generate_c1_pre_barrier_runtime_stub(StubAssembler* sasm) {
Expand Down Expand Up @@ -521,74 +496,6 @@ void G1BarrierSetAssembler::generate_c1_pre_barrier_runtime_stub(StubAssembler*
__ epilogue();
}

void G1BarrierSetAssembler::generate_c1_post_barrier_runtime_stub(StubAssembler* sasm) {
__ prologue("g1_post_barrier", false);

// arg0: store_address
Address store_addr(rfp, 2*BytesPerWord);

BarrierSet* bs = BarrierSet::barrier_set();
CardTableBarrierSet* ctbs = barrier_set_cast<CardTableBarrierSet>(bs);
CardTable* ct = ctbs->card_table();

Label done;
Label runtime;

// At this point we know new_value is non-null and the new_value crosses regions.
// Must check to see if card is already dirty

const Register thread = rthread;

Address queue_index(thread, in_bytes(G1ThreadLocalData::dirty_card_queue_index_offset()));
Address buffer(thread, in_bytes(G1ThreadLocalData::dirty_card_queue_buffer_offset()));

const Register card_offset = rscratch2;
// LR is free here, so we can use it to hold the byte_map_base.
const Register byte_map_base = lr;

assert_different_registers(card_offset, byte_map_base, rscratch1);

__ load_parameter(0, card_offset);
__ lsr(card_offset, card_offset, CardTable::card_shift());
__ load_byte_map_base(byte_map_base);
__ ldrb(rscratch1, Address(byte_map_base, card_offset));
__ cmpw(rscratch1, (int)G1CardTable::g1_young_card_val());
__ br(Assembler::EQ, done);

assert((int)CardTable::dirty_card_val() == 0, "must be 0");

__ membar(Assembler::StoreLoad);
__ ldrb(rscratch1, Address(byte_map_base, card_offset));
__ cbzw(rscratch1, done);

// storing region crossing non-null, card is clean.
// dirty card and log.
__ strb(zr, Address(byte_map_base, card_offset));

// Convert card offset into an address in card_addr
Register card_addr = card_offset;
__ add(card_addr, byte_map_base, card_addr);

__ ldr(rscratch1, queue_index);
__ cbz(rscratch1, runtime);
__ sub(rscratch1, rscratch1, wordSize);
__ str(rscratch1, queue_index);

// Reuse LR to hold buffer_addr
const Register buffer_addr = lr;

__ ldr(buffer_addr, buffer);
__ str(card_addr, Address(buffer_addr, rscratch1));
__ b(done);

__ bind(runtime);
__ push_call_clobbered_registers();
__ call_VM_leaf(CAST_FROM_FN_PTR(address, G1BarrierSetRuntime::write_ref_field_post_entry), card_addr, thread);
__ pop_call_clobbered_registers();
__ bind(done);
__ epilogue();
}

#undef __

#endif // COMPILER1
17 changes: 9 additions & 8 deletions src/hotspot/cpu/aarch64/gc/g1/g1BarrierSetAssembler_aarch64.hpp
Original file line number Diff line number Diff line change
@@ -1,5 +1,5 @@
/*
* Copyright (c) 2018, 2024, Oracle and/or its affiliates. All rights reserved.
* Copyright (c) 2018, 2025, Oracle and/or its affiliates. All rights reserved.
* DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
*
* This code is free software; you can redistribute it and/or modify it
Expand Down Expand Up @@ -32,9 +32,7 @@
class LIR_Assembler;
class StubAssembler;
class G1PreBarrierStub;
class G1PostBarrierStub;
class G1PreBarrierStubC2;
class G1PostBarrierStubC2;

class G1BarrierSetAssembler: public ModRefBarrierSetAssembler {
protected:
Expand Down Expand Up @@ -65,10 +63,15 @@ class G1BarrierSetAssembler: public ModRefBarrierSetAssembler {
public:
#ifdef COMPILER1
void gen_pre_barrier_stub(LIR_Assembler* ce, G1PreBarrierStub* stub);
void gen_post_barrier_stub(LIR_Assembler* ce, G1PostBarrierStub* stub);

void generate_c1_pre_barrier_runtime_stub(StubAssembler* sasm);
void generate_c1_post_barrier_runtime_stub(StubAssembler* sasm);

void g1_write_barrier_post_c1(MacroAssembler* masm,
Register store_addr,
Register new_val,
Register thread,
Register tmp1,
Register tmp2);
#endif

#ifdef COMPILER2
Expand All @@ -87,9 +90,7 @@ class G1BarrierSetAssembler: public ModRefBarrierSetAssembler {
Register thread,
Register tmp1,
Register tmp2,
G1PostBarrierStubC2* c2_stub);
void generate_c2_post_barrier_stub(MacroAssembler* masm,
G1PostBarrierStubC2* stub) const;
bool new_val_may_be_null);
#endif

void load_at(MacroAssembler* masm, DecoratorSet decorators, BasicType type,
Expand Down
8 changes: 4 additions & 4 deletions src/hotspot/cpu/aarch64/gc/g1/g1_aarch64.ad
Original file line number Diff line number Diff line change
@@ -1,5 +1,5 @@
//
// Copyright (c) 2024, Oracle and/or its affiliates. All rights reserved.
// Copyright (c) 2024, 2025, Oracle and/or its affiliates. All rights reserved.
// DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
//
// This code is free software; you can redistribute it and/or modify it
Expand Down Expand Up @@ -62,13 +62,13 @@ static void write_barrier_post(MacroAssembler* masm,
Register new_val,
Register tmp1,
Register tmp2) {
if (!G1PostBarrierStubC2::needs_barrier(node)) {
if (!G1BarrierStubC2::needs_post_barrier(node)) {
return;
}
Assembler::InlineSkippedInstructionsCounter skip_counter(masm);
G1BarrierSetAssembler* g1_asm = static_cast<G1BarrierSetAssembler*>(BarrierSet::barrier_set()->barrier_set_assembler());
G1PostBarrierStubC2* const stub = G1PostBarrierStubC2::create(node);
g1_asm->g1_write_barrier_post_c2(masm, store_addr, new_val, rthread, tmp1, tmp2, stub);
bool new_val_may_be_null = G1BarrierStubC2::post_new_val_may_be_null(node);
g1_asm->g1_write_barrier_post_c2(masm, store_addr, new_val, rthread, tmp1, tmp2, new_val_may_be_null);
}

%}
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