From 1aa9d89224dcb868bf4e7ddc4ef9f9f0270f4bcf Mon Sep 17 00:00:00 2001
From: hamlin <hamlin@hamlin.eu.rivosinc.com>
Date: Fri, 28 Feb 2025 11:37:19 +0000
Subject: [PATCH 1/3] initial commit

---
 src/hotspot/cpu/riscv/c2_MacroAssembler_riscv.cpp | 2 --
 1 file changed, 2 deletions(-)

diff --git a/src/hotspot/cpu/riscv/c2_MacroAssembler_riscv.cpp b/src/hotspot/cpu/riscv/c2_MacroAssembler_riscv.cpp
index 34a61177774ea..cd007afdc9848 100644
--- a/src/hotspot/cpu/riscv/c2_MacroAssembler_riscv.cpp
+++ b/src/hotspot/cpu/riscv/c2_MacroAssembler_riscv.cpp
@@ -2135,8 +2135,6 @@ void C2_MacroAssembler::enc_cmove(int cmpFlag, Register op1, Register op2, Regis
 // Set dst to NaN if any NaN input.
 void C2_MacroAssembler::minmax_fp(FloatRegister dst, FloatRegister src1, FloatRegister src2,
                                   bool is_double, bool is_min) {
-  assert_different_registers(dst, src1, src2);
-
   Label Done, Compare;
 
   is_double ? fclass_d(t0, src1)

From f6fba6bf0a5cb403a421e2ea7f425841a43198ea Mon Sep 17 00:00:00 2001
From: hamlin <hamlin@hamlin.eu.rivosinc.com>
Date: Fri, 28 Feb 2025 12:38:26 +0000
Subject: [PATCH 2/3] remove unnecessary effect

---
 src/hotspot/cpu/riscv/riscv.ad | 4 ----
 1 file changed, 4 deletions(-)

diff --git a/src/hotspot/cpu/riscv/riscv.ad b/src/hotspot/cpu/riscv/riscv.ad
index b8660afb5fd4f..499ae183d09ee 100644
--- a/src/hotspot/cpu/riscv/riscv.ad
+++ b/src/hotspot/cpu/riscv/riscv.ad
@@ -7287,7 +7287,6 @@ instruct nmaddD_reg_reg(fRegD dst, fRegD src1, fRegD src2, fRegD src3) %{
 // Math.max(FF)F
 instruct maxF_reg_reg(fRegF dst, fRegF src1, fRegF src2, rFlagsReg cr) %{
   match(Set dst (MaxF src1 src2));
-  effect(TEMP_DEF dst, KILL cr);
 
   format %{ "maxF $dst, $src1, $src2" %}
 
@@ -7303,7 +7302,6 @@ instruct maxF_reg_reg(fRegF dst, fRegF src1, fRegF src2, rFlagsReg cr) %{
 // Math.min(FF)F
 instruct minF_reg_reg(fRegF dst, fRegF src1, fRegF src2, rFlagsReg cr) %{
   match(Set dst (MinF src1 src2));
-  effect(TEMP_DEF dst, KILL cr);
 
   format %{ "minF $dst, $src1, $src2" %}
 
@@ -7319,7 +7317,6 @@ instruct minF_reg_reg(fRegF dst, fRegF src1, fRegF src2, rFlagsReg cr) %{
 // Math.max(DD)D
 instruct maxD_reg_reg(fRegD dst, fRegD src1, fRegD src2, rFlagsReg cr) %{
   match(Set dst (MaxD src1 src2));
-  effect(TEMP_DEF dst, KILL cr);
 
   format %{ "maxD $dst, $src1, $src2" %}
 
@@ -7335,7 +7332,6 @@ instruct maxD_reg_reg(fRegD dst, fRegD src1, fRegD src2, rFlagsReg cr) %{
 // Math.min(DD)D
 instruct minD_reg_reg(fRegD dst, fRegD src1, fRegD src2, rFlagsReg cr) %{
   match(Set dst (MinD src1 src2));
-  effect(TEMP_DEF dst, KILL cr);
 
   format %{ "minD $dst, $src1, $src2" %}
 

From a5d9782ca9c12f39fb56e9e7fdb86e58215ef873 Mon Sep 17 00:00:00 2001
From: hamlin <hamlin@hamlin.eu.rivosinc.com>
Date: Fri, 28 Feb 2025 12:52:28 +0000
Subject: [PATCH 3/3] keep cr/t1 in effect

---
 src/hotspot/cpu/riscv/riscv.ad | 4 ++++
 1 file changed, 4 insertions(+)

diff --git a/src/hotspot/cpu/riscv/riscv.ad b/src/hotspot/cpu/riscv/riscv.ad
index 499ae183d09ee..a4da786f02e9b 100644
--- a/src/hotspot/cpu/riscv/riscv.ad
+++ b/src/hotspot/cpu/riscv/riscv.ad
@@ -7287,6 +7287,7 @@ instruct nmaddD_reg_reg(fRegD dst, fRegD src1, fRegD src2, fRegD src3) %{
 // Math.max(FF)F
 instruct maxF_reg_reg(fRegF dst, fRegF src1, fRegF src2, rFlagsReg cr) %{
   match(Set dst (MaxF src1 src2));
+  effect(KILL cr);
 
   format %{ "maxF $dst, $src1, $src2" %}
 
@@ -7302,6 +7303,7 @@ instruct maxF_reg_reg(fRegF dst, fRegF src1, fRegF src2, rFlagsReg cr) %{
 // Math.min(FF)F
 instruct minF_reg_reg(fRegF dst, fRegF src1, fRegF src2, rFlagsReg cr) %{
   match(Set dst (MinF src1 src2));
+  effect(KILL cr);
 
   format %{ "minF $dst, $src1, $src2" %}
 
@@ -7317,6 +7319,7 @@ instruct minF_reg_reg(fRegF dst, fRegF src1, fRegF src2, rFlagsReg cr) %{
 // Math.max(DD)D
 instruct maxD_reg_reg(fRegD dst, fRegD src1, fRegD src2, rFlagsReg cr) %{
   match(Set dst (MaxD src1 src2));
+  effect(KILL cr);
 
   format %{ "maxD $dst, $src1, $src2" %}
 
@@ -7332,6 +7335,7 @@ instruct maxD_reg_reg(fRegD dst, fRegD src1, fRegD src2, rFlagsReg cr) %{
 // Math.min(DD)D
 instruct minD_reg_reg(fRegD dst, fRegD src1, fRegD src2, rFlagsReg cr) %{
   match(Set dst (MinD src1 src2));
+  effect(KILL cr);
 
   format %{ "minD $dst, $src1, $src2" %}