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8261027: AArch64: Support for LSE atomics C++ HotSpot code #2434

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@@ -24,6 +24,7 @@
.text

.globl aarch64_atomic_fetch_add_8_default_impl
.align 5
aarch64_atomic_fetch_add_8_default_impl:
0: ldaxr x2, [x0]
add x8, x2, x1
@@ -33,6 +34,7 @@ aarch64_atomic_fetch_add_8_default_impl:
ret

.globl aarch64_atomic_fetch_add_4_default_impl
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@nick-arm

nick-arm Feb 8, 2021
Member

The N1 optimisation guide suggests aligning branch targets on 32 byte boundaries.

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@theRealAph

theRealAph Feb 8, 2021
Author Contributor

OK.

.align 5
aarch64_atomic_fetch_add_4_default_impl:
0: ldaxr w2, [x0]
add w8, w2, w1
@@ -42,6 +44,7 @@ aarch64_atomic_fetch_add_4_default_impl:
ret

.globl aarch64_atomic_xchg_4_default_impl
.align 5
aarch64_atomic_xchg_4_default_impl:
0: ldaxr w2, [x0]
stlxr w8, w1, [x0]
@@ -50,6 +53,7 @@ aarch64_atomic_xchg_4_default_impl:
ret

.globl aarch64_atomic_xchg_8_default_impl
.align 5
aarch64_atomic_xchg_8_default_impl:
0: ldaxr x2, [x0]
stlxr w8, x1, [x0]
@@ -58,6 +62,7 @@ aarch64_atomic_xchg_8_default_impl:
ret

.globl aarch64_atomic_cmpxchg_1_default_impl
.align 5
aarch64_atomic_cmpxchg_1_default_impl:
0: ldxrb w3, [x0]
eor w8, w3, w1
@@ -69,6 +74,7 @@ aarch64_atomic_cmpxchg_1_default_impl:
ret

.globl aarch64_atomic_cmpxchg_4_default_impl
.align 5
aarch64_atomic_cmpxchg_4_default_impl:
0: ldxr w3, [x0]
cmp w3, w1
@@ -79,6 +85,7 @@ aarch64_atomic_cmpxchg_4_default_impl:
ret

.globl aarch64_atomic_cmpxchg_8_default_impl
.align 5
aarch64_atomic_cmpxchg_8_default_impl:
0: ldxr x3, [x0]
cmp x3, x1
@@ -5586,34 +5586,39 @@ class StubGenerator: public StubCodeGenerator {
__ align(CodeEntryAlignment);
StubCodeMark mark(this, "StubRoutines", "atomic entry points");

__align(32);
aarch64_atomic_fetch_add_8_impl = (aarch64_atomic_stub_t)__ pc();
{
Register prev = r2, addr = c_rarg0, incr = c_rarg1;
__ atomic_addal(prev, incr, addr);
__ mov(r0, prev);
__ ret(lr);
}
__align(32);
aarch64_atomic_fetch_add_4_impl = (aarch64_atomic_stub_t)__ pc();
{
Register prev = r2, addr = c_rarg0, incr = c_rarg1;
__ atomic_addalw(prev, incr, addr);
__ movw(r0, prev);
__ ret(lr);
}
__align(32);
aarch64_atomic_xchg_4_impl = (aarch64_atomic_stub_t)__ pc();
{
Register prev = r2, addr = c_rarg0, newv = c_rarg1;
__ atomic_xchglw(prev, newv, addr);
__ movw(r0, prev);
__ ret(lr);
}
__align(32);
aarch64_atomic_xchg_8_impl = (aarch64_atomic_stub_t)__ pc();
{
Register prev = r2, addr = c_rarg0, newv = c_rarg1;
__ atomic_xchgl(prev, newv, addr);
__ mov(r0, prev);
__ ret(lr);
}
__align(32);
aarch64_atomic_cmpxchg_1_impl = (aarch64_atomic_stub_t)__ pc();
{
Register prev = r3, ptr = c_rarg0, compare_val = c_rarg1,
@@ -5625,6 +5630,7 @@ class StubGenerator: public StubCodeGenerator {
__ movw(r0, prev);
__ ret(lr);
}
__align(32);
aarch64_atomic_cmpxchg_4_impl = (aarch64_atomic_stub_t)__ pc();
{
Register prev = r3, ptr = c_rarg0, compare_val = c_rarg1,
@@ -5636,6 +5642,7 @@ class StubGenerator: public StubCodeGenerator {
__ movw(r0, prev);
__ ret(lr);
}
__align(32);
aarch64_atomic_cmpxchg_8_impl = (aarch64_atomic_stub_t)__ pc();
{
Register prev = r3, ptr = c_rarg0, compare_val = c_rarg1,
@@ -85,8 +85,8 @@ struct Atomic::PlatformAdd {

template<typename D, typename I>
D add_and_fetch(D volatile* dest, I add_value, atomic_memory_order order) const {
D old_value = fetch_and_add(dest, add_value, order) + add_value;
return old_value;
D value = fetch_and_add(dest, add_value, order) + add_value;
return value;
}
};

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