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8353686: Optimize Math.cbrt for x86 64 bit platforms #24470

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8353686: Optimize Math.cbrt for x86 64 bit platforms #24470

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30c48cb
x86_64 intrinsic for cbrt using libm
missa-prime Apr 6, 2025
db27673
Merge branch 'master' into user/missa-prime/cbrt
missa-prime Apr 16, 2025
9cab7b2
Change coeff_table alignment from 4 bytes to 16 bytes to conform with…
missa-prime Apr 25, 2025
3212c66
Merge branch 'openjdk:master' into user/missa-prime/cbrt
missa-prime May 2, 2025
57412f0
Add new set of cbrt micro-benchmarks
missa-prime May 6, 2025
75516f1
Remove unnecessary movapd definitions in macro-assembler header file
missa-prime May 28, 2025
14b416c
Remove unnecessary unpckhpd and unpcklpd definitions in macro-assembl…
missa-prime May 28, 2025
42424aa
Use rcx as base and r8 as index for address calculations in certain c…
missa-prime May 28, 2025
ff4d4f2
Remove comment mentioning invalid exception when NaN input is provided
missa-prime May 28, 2025
c00b625
Add special case values to cbrt micro-benchmark set
missa-prime May 29, 2025
233e018
Add newline back to templateInterpreterGenerator_x86_64.cpp source file
missa-prime May 29, 2025
c931222
Set address attributes in movapd assembly instruction function defini…
missa-prime May 30, 2025
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6 changes: 1 addition & 5 deletions src/hotspot/cpu/x86/macroAssembler_x86.hpp
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Original file line number Diff line number Diff line change
Expand Up @@ -1245,8 +1245,7 @@ class MacroAssembler: public Assembler {
void evmovdquq(XMMRegister dst, KRegister mask, AddressLiteral src, bool merge, int vector_len, Register rscratch = noreg);
void evmovdqaq(XMMRegister dst, KRegister mask, AddressLiteral src, bool merge, int vector_len, Register rscratch = noreg);

void movapd(XMMRegister dst, XMMRegister src) { Assembler::movapd(dst, src); }
void movapd(XMMRegister dst, Address src) { Assembler::movapd(dst, src); }
using Assembler::movapd;
void movapd(XMMRegister dst, AddressLiteral src, Register rscratch = noreg);

// Move Aligned Double Quadword
Expand Down Expand Up @@ -1318,9 +1317,6 @@ class MacroAssembler: public Assembler {
void ucomisd(XMMRegister dst, Address src) { Assembler::ucomisd(dst, src); }
void ucomisd(XMMRegister dst, AddressLiteral src, Register rscratch = noreg);

void unpckhpd(XMMRegister dst, XMMRegister src) { Assembler::unpckhpd(dst, src); }
void unpcklpd(XMMRegister dst, XMMRegister src) { Assembler::unpcklpd(dst, src); }

// Bitwise Logical XOR of Packed Double-Precision Floating-Point Values
void xorpd(XMMRegister dst, XMMRegister src);
void xorpd(XMMRegister dst, Address src) { Assembler::xorpd(dst, src); }
Expand Down
10 changes: 5 additions & 5 deletions src/hotspot/cpu/x86/stubGenerator_x86_64_cbrt.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -40,7 +40,7 @@
// where P=p1+p2*r+..+p8*r^7
//
// Special cases:
// cbrt(NaN) = quiet NaN, and raise invalid exception
// cbrt(NaN) = quiet NaN
// cbrt(+/-INF) = +/-INF
// cbrt(+/-0) = +/-0
//
Expand Down Expand Up @@ -223,7 +223,7 @@ address StubGenerator::generate_libmCbrt() {
__ movsd(xmm2, ExternalAddress(SIG_MASK), r11 /*rscratch*/);
__ andl(rcx, 248);
__ lea(r8, ExternalAddress(rcp_table));
__ movsd(xmm4, Address(r8, rcx, Address::times_1));
__ movsd(xmm4, Address(rcx, r8, Address::times_1));
__ movq(r9, rax);
__ andl(rdx, rax);
__ cmpl(rdx, 0);
Expand Down Expand Up @@ -260,10 +260,10 @@ address StubGenerator::generate_libmCbrt() {
__ subsd(xmm1, xmm3);
__ movq(xmm3, xmm7);
__ lea(r8, ExternalAddress(cbrt_table));
__ mulsd(xmm7, Address(r8, rcx, Address::times_1));
__ mulsd(xmm7, Address(rcx, r8, Address::times_1));
__ mulsd(xmm1, xmm4);
__ lea(r8, ExternalAddress(D_table));
__ mulsd(xmm3, Address(r8, rcx, Address::times_1));
__ mulsd(xmm3, Address(rcx, r8, Address::times_1));
__ movapd(xmm4, xmm1);
__ unpcklpd(xmm1, xmm1);
__ mulpd(xmm5, xmm1);
Expand Down Expand Up @@ -292,7 +292,7 @@ address StubGenerator::generate_libmCbrt() {
__ movdl(rax, xmm7);
__ andl(rcx, 248);
__ lea(r8, ExternalAddress(rcp_table));
__ movsd(xmm4, Address(r8, rcx, Address::times_1));
__ movsd(xmm4, Address(rcx, r8, Address::times_1));
__ movq(r9, rax);
__ andl(rdx, rax);
__ shrl(rdx, 8);
Expand Down