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8351016: RA support for EVEX to REX/REX2 demotion to optimize NDD instructions#26283

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8351016: RA support for EVEX to REX/REX2 demotion to optimize NDD instructions#26283
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jatin-bhateja:JDK-8351016

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@jatin-bhateja jatin-bhateja commented Jul 14, 2025

Currently, while choosing the colour (register) for a definition live range during the select phase of register allocation, we pick the first available colour that does not match with already allocated neighboring live ranges.

With Intel APX NDD ISA extension, several existing two-address arithmetic instructions can now have an explicit non-destructive destination operand; this, in general, saves additional spills for two-address instructions where the destination is also the first source operand, and where the source live range surpasses the current instruction.

All NDD instructions mandate extended EVEX encoding with a bulky 4-byte prefix, JDK-8351994 added logic for NDD to REX/REX2 demotion in the assembler layer, but due to the existing first color selection register allocation policy, the demotions are rare. This patch biases the allocation of NDD definition to the first source operand or the second source operand for the commutative class of operations.

Biasing is a compile-time hint to the allocator and is different from live range coalescing (aggressive/conservative), which merges the two live ranges using the union find algorithm. Given that REX encoding needs a 1-byte prefix and REX2 encoding needs a 2-byte prefix, domotion saves considerable JIT code size.

The patch shows around 5-20% improvement in code size by facilitating NDD demotion.

For the following micro, the method JIT code size reduced from 136 to 120 bytes, which is around a 13% reduction in code size footprint.

Micro:-
image

Baseline :-
image

With opt:-
image

Thorough validations are underway using the latest Intel Software Development Emulator version 9.58.

Kindly review and share your feedback.

Best Regards,
Jatin


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  • JDK-8351016: RA support for EVEX to REX/REX2 demotion to optimize NDD instructions (Sub-task - P4)

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👋 Welcome back jbhateja! A progress list of the required criteria for merging this PR into master will be added to the body of your pull request. There are additional pull request commands available for use with this pull request.

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jatin-bhateja commented Jul 14, 2025

/keepalive

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@jatin-bhateja This change now passes all automated pre-integration checks.

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8351016: RA support for EVEX to REX/REX2 demotion to optimize NDD instructions

Reviewed-by: sviswanathan, dlunden, vlivanov, qamai

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jatin-bhateja commented Jul 14, 2025

/label add hotspot-compiler-dev

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@jatin-bhateja The pull request is being re-evaluated and the inactivity timeout has been reset.

@openjdk openjdk bot added the hotspot-compiler hotspot-compiler-dev@openjdk.org label Jul 14, 2025
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This may also be applicable to non-APX instructions. For example, in the case of casting long to int, if the destination and the source are the same, then we do not need to emit any code. As a result, do you think it is better to mark operands in the ad file to preferably have the same register as the result?

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jatin-bhateja commented Jul 14, 2025

This may also be applicable to non-APX instructions. For example, in the case of casting long to int, if the destination and the source are the same, then we do not need to emit any code. As a result, do you think it is better to mark operands in the ad file to preferably have the same register as the result?

Yes, for now, I limited this to APX, but biasing the allocation of destination to non-interfering use(src) will enable instruction elision during assembling. Currently, while assigning a color(reg) to a live range, the allocator picks the first free aligned register.

do you think it is better to mark operands in the ad file to preferably have the same register as the result?

There are existing DF attributions like USE_DEF which can be used to add such a constraint, but for APX NDD, we do not wish to up-front constrain the source to be the same as the destination, as it defeats the purpose, and the allocator may end up emitting a copy before the NDD instruction to honour this constraint. The idea here is to only bias color selection for non-interfering live ranges to facilitate EEVEX to REX/REX2 demotions.

@bridgekeeper bridgekeeper bot added oca Needs verification of OCA signatory status and removed oca Needs verification of OCA signatory status labels Jul 15, 2025
@jatin-bhateja jatin-bhateja marked this pull request as ready for review August 4, 2025 15:17
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@jatin-bhateja jatin-bhateja marked this pull request as draft August 4, 2025 15:20
@openjdk openjdk bot removed the rfr Pull request is ready for review label Aug 4, 2025
@jatin-bhateja jatin-bhateja marked this pull request as ready for review August 4, 2025 15:45
@openjdk openjdk bot added the rfr Pull request is ready for review label Aug 4, 2025
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@jatin-bhateja Thanks for looking into this.

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@jatin-bhateja To determine the appropriate audience for reviewing this pull request, one or more labels corresponding to different subsystems will normally be applied automatically. However, no automatic labelling rule matches the changes in this pull request. In order to have an "RFR" email sent to the correct mailing list, you will need to add one or more applicable labels manually using the /label pull request command.

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Looks good to me.

@openjdk openjdk bot added the ready Pull request is ready to be integrated label Sep 19, 2025
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I can't approve this approach. I think blindly biasing the color of an operation to that of its input is too optimistic and will lead to numerous false-positive cases. It is better to have a more fine-grained selection using the script in the ad file. For example:

instruct addI_rReg_ndd(rRegI dst, rRegI src1, rRegI src2, rFlagsReg cr)
%{
  predicate(UseAPX);
  match(Set dst (AddI src1 src2));
  effect(KILL cr);
  bias(src1);
  flag(PD::Flag_sets_overflow_flag, PD::Flag_sets_sign_flag, PD::Flag_sets_zero_flag, PD::Flag_sets_carry_flag, PD::Flag_sets_parity_flag);

  format %{ "eaddl    $dst, $src1, $src2\t# int ndd" %}
  ins_encode %{
    __ eaddl($dst$$Register, $src1$$Register, $src2$$Register, false);
  %}
  ins_pipe(ialu_reg_reg);
%}

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@jatin-bhateja Please do not rebase or force-push to an active PR as it invalidates existing review comments. Note for future reference, the bots always squash all changes into a single commit automatically as part of the integration. See OpenJDK Developers’ Guide for more information.

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Hi @iwanowww , Please let me know if this is good to land now.

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Thanks, Jatin. Overall, looks good.

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openjdk bot commented Nov 25, 2025

@jatin-bhateja Please do not rebase or force-push to an active PR as it invalidates existing review comments. Note for future reference, the bots always squash all changes into a single commit automatically as part of the integration. See OpenJDK Developers’ Guide for more information.

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Thanks for clarifications, Jatin. Looks good.

@openjdk openjdk bot added the ready Pull request is ready to be integrated label Nov 25, 2025
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jatin-bhateja commented Nov 26, 2025

Thanks @iwanowww , for your comments and review approval.

Hi @sviswa7 , @dlunde can you check and re-approve this version.

Best Regards

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dlunde commented Nov 26, 2025

Rerunning tests and will re-approve when finished. Latest changes look good, here are a few nits (only comment and style changes): e33416a

Also, thanks for your patience!

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Hi @dlunde , waiting for your test clearance. thanks!

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Tests look good!

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Hi @sviswa7. @iwanowww , can you kindly re-approve this.

@openjdk openjdk bot added the ready Pull request is ready to be integrated label Nov 29, 2025
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Thanks @iwanowww , @dean-long, @dlunde , @merykitty and @sviswa7 for your reviews and approval

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/integrate

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openjdk bot commented Dec 1, 2025

Going to push as commit e0311ec.
Since your change was applied there have been 36 commits pushed to the master branch:

Your commit was automatically rebased without conflicts.

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@jatin-bhateja Pushed as commit e0311ec.

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