8367014: Rename class Atomic to AtomicAccess

src/hotspot/cpu/aarch64/gc/shared/barrierSetAssembler_aarch64.cpp

@@ -275,7 +275,7 @@ address BarrierSetAssembler::patching_epoch_addr() {
 }
 
 void BarrierSetAssembler::increment_patching_epoch() {
-  Atomic::inc(&_patching_epoch);
+  AtomicAccess::inc(&_patching_epoch);
 }
 
 void BarrierSetAssembler::clear_patching_epoch() {

src/hotspot/cpu/aarch64/gc/shared/barrierSetNMethod_aarch64.cpp

@@ -112,22 +112,22 @@ class NativeNMethodBarrier {
   }
 
   int get_value() {
-    return Atomic::load_acquire(guard_addr());
+    return AtomicAccess::load_acquire(guard_addr());
   }
 
   void set_value(int value, int bit_mask) {
     if (bit_mask == ~0) {
-      Atomic::release_store(guard_addr(), value);
+      AtomicAccess::release_store(guard_addr(), value);
       return;
     }
     assert((value & ~bit_mask) == 0, "trying to set bits outside the mask");
     value &= bit_mask;
-    int old_value = Atomic::load(guard_addr());
+    int old_value = AtomicAccess::load(guard_addr());
     while (true) {
       // Only bits in the mask are changed
       int new_value = value | (old_value & ~bit_mask);
       if (new_value == old_value) break;
-      int v = Atomic::cmpxchg(guard_addr(), old_value, new_value, memory_order_release);
+      int v = AtomicAccess::cmpxchg(guard_addr(), old_value, new_value, memory_order_release);
       if (v == old_value) break;
       old_value = v;
     }

src/hotspot/cpu/aarch64/stubGenerator_aarch64.cpp

@@ -42,7 +42,7 @@
 #include "prims/methodHandles.hpp"
 #include "prims/upcallLinker.hpp"
 #include "runtime/arguments.hpp"
-#include "runtime/atomic.hpp"
+#include "runtime/atomicAccess.hpp"
 #include "runtime/continuation.hpp"
 #include "runtime/continuationEntry.inline.hpp"
 #include "runtime/frame.inline.hpp"
@@ -10265,7 +10265,7 @@ class StubGenerator: public StubCodeGenerator {
 
 #if defined (LINUX) && !defined (__ARM_FEATURE_ATOMICS)
 
-  // ARMv8.1 LSE versions of the atomic stubs used by Atomic::PlatformXX.
+  // ARMv8.1 LSE versions of the atomic stubs used by AtomicAccess::PlatformXX.
   //
   // If LSE is in use, generate LSE versions of all the stubs. The
   // non-LSE versions are in atomic_aarch64.S.

src/hotspot/cpu/arm/gc/shared/barrierSetNMethod_arm.cpp

@@ -48,22 +48,22 @@ class NativeNMethodBarrier: public NativeInstruction {
 
 public:
   int get_value() {
-    return Atomic::load_acquire(guard_addr());
+    return AtomicAccess::load_acquire(guard_addr());
   }
 
   void set_value(int value, int bit_mask) {
     if (bit_mask == ~0) {
-      Atomic::release_store(guard_addr(), value);
+      AtomicAccess::release_store(guard_addr(), value);
       return;
     }
     assert((value & ~bit_mask) == 0, "trying to set bits outside the mask");
     value &= bit_mask;
-    int old_value = Atomic::load(guard_addr());
+    int old_value = AtomicAccess::load(guard_addr());
     while (true) {
       // Only bits in the mask are changed
       int new_value = value | (old_value & ~bit_mask);
       if (new_value == old_value) break;
-      int v = Atomic::cmpxchg(guard_addr(), old_value, new_value, memory_order_release);
+      int v = AtomicAccess::cmpxchg(guard_addr(), old_value, new_value, memory_order_release);
       if (v == old_value) break;
       old_value = v;
     }

src/hotspot/cpu/arm/stubGenerator_arm.cpp

@@ -421,7 +421,8 @@ class StubGenerator: public StubCodeGenerator {
   }
 
 
- // As per atomic.hpp the Atomic read-modify-write operations must be logically implemented as:
+ // As per atomicAccess.hpp the atomic read-modify-write operations must be
+ // logically implemented as:
  //  <fence>; <op>; <membar StoreLoad|StoreStore>
  // But for load-linked/store-conditional based systems a fence here simply means
  // no load/store can be reordered with respect to the initial load-linked, so we have:
@@ -440,7 +441,7 @@ class StubGenerator: public StubCodeGenerator {
   // be removed in the future.
 
   // Implementation of atomic_add(jint add_value, volatile jint* dest)
-  // used by Atomic::add(volatile jint* dest, jint add_value)
+  // used by AtomicAccess::add(volatile jint* dest, jint add_value)
   //
   // Arguments :
   //
@@ -492,7 +493,7 @@ class StubGenerator: public StubCodeGenerator {
   }
 
   // Implementation of jint atomic_xchg(jint exchange_value, volatile jint* dest)
-  // used by Atomic::add(volatile jint* dest, jint exchange_value)
+  // used by AtomicAccess::add(volatile jint* dest, jint exchange_value)
   //
   // Arguments :
   //
@@ -542,7 +543,7 @@ class StubGenerator: public StubCodeGenerator {
   }
 
   // Implementation of jint atomic_cmpxchg(jint exchange_value, volatile jint *dest, jint compare_value)
-  // used by Atomic::cmpxchg(volatile jint *dest, jint compare_value, jint exchange_value)
+  // used by AtomicAccess::cmpxchg(volatile jint *dest, jint compare_value, jint exchange_value)
   //
   // Arguments :
   //
@@ -582,7 +583,7 @@ class StubGenerator: public StubCodeGenerator {
     return start;
   }
 
-  // Support for jlong Atomic::cmpxchg(jlong exchange_value, volatile jlong *dest, jlong compare_value)
+  // Support for jlong AtomicAccess::cmpxchg(jlong exchange_value, volatile jlong *dest, jlong compare_value)
   // reordered before by a wrapper to (jlong compare_value, jlong exchange_value, volatile jlong *dest)
   //
   // Arguments :

src/hotspot/cpu/ppc/gc/shared/barrierSetNMethod_ppc.cpp

@@ -73,15 +73,15 @@ class NativeNMethodBarrier: public NativeInstruction {
       u_char buf[NativeMovRegMem::instruction_size];
       uint64_t u64;
     } new_mov_instr, old_mov_instr;
-    new_mov_instr.u64 = old_mov_instr.u64 = Atomic::load(instr);
+    new_mov_instr.u64 = old_mov_instr.u64 = AtomicAccess::load(instr);
     while (true) {
       // Only bits in the mask are changed
       int old_value = nativeMovRegMem_at(old_mov_instr.buf)->offset();
       int new_value = value | (old_value & ~bit_mask);
       if (new_value == old_value) return; // skip icache flush if nothing changed
       nativeMovRegMem_at(new_mov_instr.buf)->set_offset(new_value, false /* no icache flush */);
       // Swap in the new value
-      uint64_t v = Atomic::cmpxchg(instr, old_mov_instr.u64, new_mov_instr.u64, memory_order_relaxed);
+      uint64_t v = AtomicAccess::cmpxchg(instr, old_mov_instr.u64, new_mov_instr.u64, memory_order_relaxed);
       if (v == old_mov_instr.u64) break;
       old_mov_instr.u64 = v;
     }

src/hotspot/cpu/ppc/nativeInst_ppc.cpp

@@ -347,7 +347,7 @@ void NativeGeneralJump::replace_mt_safe(address instr_addr, address code_buffer)
   // Finally patch out the jump.
   volatile juint *jump_addr = (volatile juint*)instr_addr;
   // Release not needed because caller uses invalidate_range after copying the remaining bytes.
-  //Atomic::release_store(jump_addr, *((juint*)code_buffer));
+  //AtomicAccess::release_store(jump_addr, *((juint*)code_buffer));
   *jump_addr = *((juint*)code_buffer); // atomically store code over branch instruction
   ICache::ppc64_flush_icache_bytes(instr_addr, NativeGeneralJump::instruction_size);
 }

src/hotspot/cpu/riscv/gc/shared/barrierSetAssembler_riscv.cpp

@@ -217,7 +217,7 @@ address BarrierSetAssembler::patching_epoch_addr() {
 }
 
 void BarrierSetAssembler::increment_patching_epoch() {
-  Atomic::inc(&_patching_epoch);
+  AtomicAccess::inc(&_patching_epoch);
 }
 
 void BarrierSetAssembler::clear_patching_epoch() {

src/hotspot/cpu/riscv/gc/shared/barrierSetNMethod_riscv.cpp

@@ -106,22 +106,22 @@ class NativeNMethodBarrier {
   }
 
   int get_value() {
-    return Atomic::load_acquire(guard_addr());
+    return AtomicAccess::load_acquire(guard_addr());
   }
 
   void set_value(int value, int bit_mask) {
     if (bit_mask == ~0) {
-      Atomic::release_store(guard_addr(), value);
+      AtomicAccess::release_store(guard_addr(), value);
       return;
     }
     assert((value & ~bit_mask) == 0, "trying to set bits outside the mask");
     value &= bit_mask;
-    int old_value = Atomic::load(guard_addr());
+    int old_value = AtomicAccess::load(guard_addr());
     while (true) {
       // Only bits in the mask are changed
       int new_value = value | (old_value & ~bit_mask);
       if (new_value == old_value) break;
-      int v = Atomic::cmpxchg(guard_addr(), old_value, new_value, memory_order_release);
+      int v = AtomicAccess::cmpxchg(guard_addr(), old_value, new_value, memory_order_release);
       if (v == old_value) break;
       old_value = v;
     }

src/hotspot/cpu/s390/gc/shared/barrierSetNMethod_s390.cpp

@@ -64,12 +64,12 @@ class NativeMethodBarrier: public NativeInstruction {
       assert((value & ~bit_mask) == 0, "trying to set bits outside the mask");
       value &= bit_mask;
       int32_t* data_addr = (int32_t*)get_patchable_data_address();
-      int old_value = Atomic::load(data_addr);
+      int old_value = AtomicAccess::load(data_addr);
       while (true) {
         // Only bits in the mask are changed
         int new_value = value | (old_value & ~bit_mask);
         if (new_value == old_value) break;
-        int v = Atomic::cmpxchg(data_addr, old_value, new_value, memory_order_release);
+        int v = AtomicAccess::cmpxchg(data_addr, old_value, new_value, memory_order_release);
         if (v == old_value) break;
         old_value = v;
       }

src/hotspot/cpu/x86/gc/shared/barrierSetNMethod_x86.cpp

@@ -65,12 +65,12 @@ class NativeNMethodCmpBarrier: public NativeInstruction {
     assert(align_up(immediate_address(), sizeof(jint)) ==
            align_down(immediate_address(), sizeof(jint)), "immediate not aligned");
     jint* data_addr = (jint*)immediate_address();
-    jint old_value = Atomic::load(data_addr);
+    jint old_value = AtomicAccess::load(data_addr);
     while (true) {
       // Only bits in the mask are changed
       jint new_value = imm | (old_value & ~bit_mask);
       if (new_value == old_value) break;
-      jint v = Atomic::cmpxchg(data_addr, old_value, new_value, memory_order_release);
+      jint v = AtomicAccess::cmpxchg(data_addr, old_value, new_value, memory_order_release);
       if (v == old_value) break;
       old_value = v;
     }

src/hotspot/os/aix/os_aix.cpp

@@ -43,7 +43,7 @@
 #include "prims/jniFastGetField.hpp"
 #include "prims/jvm_misc.hpp"
 #include "runtime/arguments.hpp"
-#include "runtime/atomic.hpp"
+#include "runtime/atomicAccess.hpp"
 #include "runtime/globals.hpp"
 #include "runtime/globals_extension.hpp"
 #include "runtime/interfaceSupport.inline.hpp"

src/hotspot/os/bsd/os_bsd.cpp

@@ -39,7 +39,7 @@
 #include "prims/jniFastGetField.hpp"
 #include "prims/jvm_misc.hpp"
 #include "runtime/arguments.hpp"
-#include "runtime/atomic.hpp"
+#include "runtime/atomicAccess.hpp"
 #include "runtime/globals.hpp"
 #include "runtime/globals_extension.hpp"
 #include "runtime/interfaceSupport.inline.hpp"
@@ -809,7 +809,7 @@ jlong os::javaTimeNanos() {
   if (now <= prev) {
     return prev;   // same or retrograde time;
   }
-  const uint64_t obsv = Atomic::cmpxchg(&Bsd::_max_abstime, prev, now);
+  const uint64_t obsv = AtomicAccess::cmpxchg(&Bsd::_max_abstime, prev, now);
   assert(obsv >= prev, "invariant");   // Monotonicity
   // If the CAS succeeded then we're done and return "now".
   // If the CAS failed and the observed value "obsv" is >= now then
@@ -2135,14 +2135,14 @@ uint os::processor_id() {
   __asm__ ("cpuid\n\t" : "+a" (eax), "+b" (ebx), "+c" (ecx), "+d" (edx) : );
 
   uint apic_id = (ebx >> 24) & (processor_id_map_size - 1);
-  int processor_id = Atomic::load(&processor_id_map[apic_id]);
+  int processor_id = AtomicAccess::load(&processor_id_map[apic_id]);
 
   while (processor_id < 0) {
     // Assign processor id to APIC id
-    processor_id = Atomic::cmpxchg(&processor_id_map[apic_id], processor_id_unassigned, processor_id_assigning);
+    processor_id = AtomicAccess::cmpxchg(&processor_id_map[apic_id], processor_id_unassigned, processor_id_assigning);
     if (processor_id == processor_id_unassigned) {
-      processor_id = Atomic::fetch_then_add(&processor_id_next, 1) % os::processor_count();
-      Atomic::store(&processor_id_map[apic_id], processor_id);
+      processor_id = AtomicAccess::fetch_then_add(&processor_id_next, 1) % os::processor_count();
+      AtomicAccess::store(&processor_id_map[apic_id], processor_id);
     }
   }
 

src/hotspot/os/linux/os_linux.cpp

@@ -42,7 +42,7 @@
 #include "prims/jniFastGetField.hpp"
 #include "prims/jvm_misc.hpp"
 #include "runtime/arguments.hpp"
-#include "runtime/atomic.hpp"
+#include "runtime/atomicAccess.hpp"
 #include "runtime/globals.hpp"
 #include "runtime/globals_extension.hpp"
 #include "runtime/init.hpp"
@@ -4783,8 +4783,8 @@ static bool should_warn_invalid_processor_id() {
 
   static volatile int warn_once = 1;
 
-  if (Atomic::load(&warn_once) == 0 ||
-      Atomic::xchg(&warn_once, 0) == 0) {
+  if (AtomicAccess::load(&warn_once) == 0 ||
+      AtomicAccess::xchg(&warn_once, 0) == 0) {
     // Don't warn more than once
     return false;
   }

src/hotspot/os/posix/os_posix.cpp

@@ -31,7 +31,7 @@
 #include "nmt/memTracker.hpp"
 #include "os_posix.inline.hpp"
 #include "runtime/arguments.hpp"
-#include "runtime/atomic.hpp"
+#include "runtime/atomicAccess.hpp"
 #include "runtime/frame.inline.hpp"
 #include "runtime/globals_extension.hpp"
 #include "runtime/interfaceSupport.inline.hpp"
@@ -1691,7 +1691,7 @@ void PlatformEvent::park() {       // AKA "down()"
   // atomically decrement _event
   for (;;) {
     v = _event;
-    if (Atomic::cmpxchg(&_event, v, v - 1) == v) break;
+    if (AtomicAccess::cmpxchg(&_event, v, v - 1) == v) break;
   }
   guarantee(v >= 0, "invariant");
 
@@ -1738,7 +1738,7 @@ int PlatformEvent::park_nanos(jlong nanos) {
   // atomically decrement _event
   for (;;) {
     v = _event;
-    if (Atomic::cmpxchg(&_event, v, v - 1) == v) break;
+    if (AtomicAccess::cmpxchg(&_event, v, v - 1) == v) break;
   }
   guarantee(v >= 0, "invariant");
 
@@ -1794,7 +1794,7 @@ void PlatformEvent::unpark() {
   // but only in the correctly written condition checking loops of ObjectMonitor,
   // Mutex/Monitor, and JavaThread::sleep
 
-  if (Atomic::xchg(&_event, 1) >= 0) return;
+  if (AtomicAccess::xchg(&_event, 1) >= 0) return;
 
   int status = pthread_mutex_lock(_mutex);
   assert_status(status == 0, status, "mutex_lock");
@@ -1847,9 +1847,9 @@ void Parker::park(bool isAbsolute, jlong time) {
 
   // Optional fast-path check:
   // Return immediately if a permit is available.
-  // We depend on Atomic::xchg() having full barrier semantics
+  // We depend on AtomicAccess::xchg() having full barrier semantics
   // since we are doing a lock-free update to _counter.
-  if (Atomic::xchg(&_counter, 0) > 0) return;
+  if (AtomicAccess::xchg(&_counter, 0) > 0) return;
 
   JavaThread *jt = JavaThread::current();
 

src/hotspot/os/posix/signals_posix.cpp

@@ -28,7 +28,7 @@
 #include "jvm.h"
 #include "logging/log.hpp"
 #include "os_posix.hpp"
-#include "runtime/atomic.hpp"
+#include "runtime/atomicAccess.hpp"
 #include "runtime/globals.hpp"
 #include "runtime/interfaceSupport.inline.hpp"
 #include "runtime/java.hpp"
@@ -356,7 +356,7 @@ static void jdk_misc_signal_init() {
 
 void os::signal_notify(int sig) {
   if (sig_semaphore != nullptr) {
-    Atomic::inc(&pending_signals[sig]);
+    AtomicAccess::inc(&pending_signals[sig]);
     sig_semaphore->signal();
   } else {
     // Signal thread is not created with ReduceSignalUsage and jdk_misc_signal_init
@@ -369,7 +369,7 @@ static int check_pending_signals() {
   for (;;) {
     for (int i = 0; i < NSIG + 1; i++) {
       jint n = pending_signals[i];
-      if (n > 0 && n == Atomic::cmpxchg(&pending_signals[i], n, n - 1)) {
+      if (n > 0 && n == AtomicAccess::cmpxchg(&pending_signals[i], n, n - 1)) {
         return i;
       }
     }

src/hotspot/os/posix/suspendResume_posix.cpp

@@ -22,7 +22,7 @@
  *
  */
 
-#include "runtime/atomic.hpp"
+#include "runtime/atomicAccess.hpp"
 #include "suspendResume_posix.hpp"
 
 /* try to switch state from state "from" to state "to"
@@ -31,7 +31,7 @@
 SuspendResume::State SuspendResume::switch_state(SuspendResume::State from,
                                                  SuspendResume::State to)
 {
-  SuspendResume::State result = Atomic::cmpxchg(&_state, from, to);
+  SuspendResume::State result = AtomicAccess::cmpxchg(&_state, from, to);
   if (result == from) {
     // success
     return to;