8366333: AArch64: Enhance SVE subword type implementation of vector compress #27188

erifan · 2025-09-10T08:41:51Z

The AArch64 SVE and SVE2 architectures lack an instruction suitable for subword-type compress operations. Therefore, the current implementation uses the 32-bit SVE compact instruction to compress subword types by first widening the high and low parts to 32 bits, compressing them, and then narrowing them back to their original type. Finally, the high and low parts are merged using the index + tbl instructions.

This approach is significantly slower compared to architectures with native support. After evaluating all available AArch64 SVE instructions and experimenting with various implementations—such as looping over the active elements, extraction, and insertion—I confirmed that the existing algorithm is optimal given the instruction set. However, there is still room for optimization in the following two aspects:

Merging with index + tbl is suboptimal due to the high latency of the index instruction.
For partial subword types, operations to the highest half are unnecessary because those bits are invalid.

This pull request introduces the following changes:

Replaces index + tbl with the whilelt + splice instructions, which offer lower latency and higher throughput.
Eliminates unnecessary compress operations for partial subword type cases.
For sve_compress_byte, one less temporary register is used to alleviate potential register pressure.

Benchmark results demonstrate that these changes significantly improve performance.

Benchmarks on Nvidia Grace machine with 128-bit SVE:

Benchmark	            Unit	Before	 Error	After	 Error	Uplift
Byte128Vector.compress	ops/ms	4846.97	 26.23	6638.56	 31.60	1.36
Byte64Vector.compress	ops/ms	2447.69	 12.95	7167.68	 34.49	2.92
Short128Vector.compress	ops/ms	7174.88	 40.94	8398.45	 9.48	1.17
Short64Vector.compress	ops/ms	3618.72	 3.04	8618.22	 10.91	2.38

This PR was tested on 128-bit, 256-bit, and 512-bit SVE environments, and all tests passed.

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Issue

JDK-8366333: AArch64: Enhance SVE subword type implementation of vector compress (Enhancement - P4)

Reviewers

Galder Zamarreño (@galderz - Author) Review applies to 0836d1b8
Vladimir Ivanov (@iwanowww - Reviewer) Review applies to f3344e5f
Jatin Bhateja (@jatin-bhateja - Reviewer)
Xiaohong Gong (@XiaohongGong - Committer)

Contributors

Jatin Bhateja <jbhateja@openjdk.org>

Reviewing

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Update a local copy of the PR:
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Using Webrev

Link to Webrev Comment

…ompress The AArch64 SVE and SVE2 architectures lack an instruction suitable for subword-type `compress` operations. Therefore, the current implementation uses the 32-bit SVE `compact` instruction to compress subword types by first widening the high and low parts to 32 bits, compressing them, and then narrowing them back to their original type. Finally, the high and low parts are merged using the `index + tbl` instructions. This approach is significantly slower compared to architectures with native support. After evaluating all available AArch64 SVE instructions and experimenting with various implementations—such as looping over the active elements, extraction, and insertion—I confirmed that the existing algorithm is optimal given the instruction set. However, there is still room for optimization in the following two aspects: 1. Merging with `index + tbl` is suboptimal due to the high latency of the `index` instruction. 2. For partial subword types, operations to the highest half are unnecessary because those bits are invalid. This pull request introduces the following changes: 1. Replaces `index + tbl` with the `whilelt + splice` instructions, which offer lower latency and higher throughput. 2. Eliminates unnecessary compress operations for partial subword type cases. 3. For `sve_compress_byte`, one less temporary register is used to alleviate potential register pressure. Benchmark results demonstrate that these changes significantly improve performance. Benchmarks on Nvidia Grace machine with 128-bit SVE: ``` Benchmark Unit Before Error After Error Uplift Byte128Vector.compress ops/ms 4846.97 26.23 6638.56 31.60 1.36 Byte64Vector.compress ops/ms 2447.69 12.95 7167.68 34.49 2.92 Short128Vector.compress ops/ms 7174.88 40.94 8398.45 9.48 1.17 Short64Vector.compress ops/ms 3618.72 3.04 8618.22 10.91 2.38 ``` This PR was tested on 128-bit, 256-bit, and 512-bit SVE environments, and all tests passed.

bridgekeeper · 2025-09-10T08:42:55Z

👋 Welcome back erifan! A progress list of the required criteria for merging this PR into master will be added to the body of your pull request. There are additional pull request commands available for use with this pull request.

openjdk · 2025-09-10T08:43:50Z

@erifan This change now passes all automated pre-integration checks.

ℹ️ This project also has non-automated pre-integration requirements. Please see the file CONTRIBUTING.md for details.

After integration, the commit message for the final commit will be:

8366333: AArch64: Enhance SVE subword type implementation of vector compress

Co-authored-by: Jatin Bhateja <jbhateja@openjdk.org>
Reviewed-by: jbhateja, xgong, galder, vlivanov

You can use pull request commands such as /summary, /contributor and /issue to adjust it as needed.

At the time when this comment was updated there had been 203 new commits pushed to the master branch:

680414d: 8369631: Assess and remedy any unsafe usage of the sr_semaphore Semaphore in the Posix signal code
c2fde51: 8357390: java/awt/Toolkit/ScreenInsetsTest/ScreenInsetsTest.java Test failing on Ubuntu 24.04 Vm Hosts used by Oracle's internal CI system
eff6439: 8370120: Make jpackage tests output more stable
... and 200 more: https://git.openjdk.org/jdk/compare/eb34a117934951af075a425ce2cf8d3b1ced9700...master

As there are no conflicts, your changes will automatically be rebased on top of these commits when integrating. If you prefer to avoid this automatic rebasing, please check the documentation for the /integrate command for further details.

As you do not have Committer status in this project an existing Committer must agree to sponsor your change. Possible candidates are the reviewers of this PR (@eme64, @iwanowww, @jatin-bhateja, @XiaohongGong) but any other Committer may sponsor as well.

➡️ To flag this PR as ready for integration with the above commit message, type /integrate in a new comment. (Afterwards, your sponsor types /sponsor in a new comment to perform the integration).

openjdk · 2025-09-10T08:44:22Z

@erifan this pull request can not be integrated into master due to one or more merge conflicts. To resolve these merge conflicts and update this pull request you can run the following commands in the local repository for your personal fork:

git checkout JDK-8366333-compress
git fetch https://git.openjdk.org/jdk.git master
git merge FETCH_HEAD
# resolve conflicts and follow the instructions given by git merge
git commit -m "Merge master"
git push

openjdk · 2025-09-10T08:44:46Z

@erifan The following label will be automatically applied to this pull request:

hotspot-compiler

When this pull request is ready to be reviewed, an "RFR" email will be sent to the corresponding mailing list. If you would like to change these labels, use the /label pull request command.

mlbridge · 2025-09-10T08:48:58Z

Webrevs

galderz · 2025-09-11T06:07:42Z

Would it make sense to additionally run the relevant benchmarks on other popular aarch64 platforms such as Graviton, to make sure the improvements are seen there as well?

src/hotspot/cpu/aarch64/c2_MacroAssembler_aarch64.cpp

erifan · 2025-09-15T09:58:19Z

@galderz Yeah, absolutely. This is the test results on an AWS graviton3 V1 machine, we can see similar performance gain.

Benchmark	Units	Before	Error	After	Error	Uplift
Byte128Vector.compress	ops/ms	2405.511	0.763	6116.85	17.699	2.54284848
Byte64Vector.compress	ops/ms	1151.662	11.262	5278.924	6.74	4.58374419
Double128Vector.compress	ops/ms	4919.017	4.909	4940.232	20.143	1.00431285
Double64Vector.compress	ops/ms	37.071	0.778	37.109	0.945	1.00102506
Float128Vector.compress	ops/ms	9580.312	48.341	9586.499	74.934	1.0006458
Float64Vector.compress	ops/ms	4943.728	7.361	4941.917	5.871	0.99963368
Int128Vector.compress	ops/ms	9496.991	34.972	9515.122	29.204	1.00190913
Int64Vector.compress	ops/ms	4940.23	7.141	4941.815	5.077	1.00032084
Long128Vector.compress	ops/ms	4918.142	14.835	4917.148	9.05	0.99979789
Long64Vector.compress	ops/ms	36.58	0.426	36.574	0.431	0.99983598
Short128Vector.compress	ops/ms	3343.878	0.898	6813.421	4.143	2.03758062
Short64Vector.compress	ops/ms	1595.358	3.37	3390.959	3.55	2.12551603

eme64

Drive-by comments, going on vacation soon so don't depend on me fully reviewing this any time soon ;)

src/hotspot/cpu/aarch64/c2_MacroAssembler_aarch64.cpp

test/hotspot/jtreg/compiler/vectorapi/VectorCompressTest.java

eme64 · 2025-09-18T12:56:04Z

@erifan I'm going to be out of the office for 3 weeks, so feel free to ask others for reviews :)

erifan

Thanks for your review @eme64 . Have a nice trip!

src/hotspot/cpu/aarch64/c2_MacroAssembler_aarch64.cpp

test/hotspot/jtreg/compiler/vectorapi/VectorCompressTest.java

iwanowww · 2025-09-26T21:42:58Z

src/hotspot/cpu/aarch64/c2_MacroAssembler_aarch64.cpp

+  // Example input:   src   = q p n m l k j i h g f e d c b a, one character is 8 bits.
+  //                  mask  = 0 1 0 0 0 0 0 1 0 1 0 0 0 1 0 1, one character is 1 bit.
+  // Expected result: dst   = 0 0 0 0 0 0 0 0 0 0 0 p i g c a
+  sve_dup(vtmp3, B, 0);


For clarity, you could declare a local FloatRegister vzr = vtmp3 and refer to it at all use sites. That would make things clearer.

Done, thanks!

The following reads slightly better, but it's up to you how to shape it.

FloatRegister vzr = vtmp3; sve_dup(vzr, B, 0);

Done, thanks!

iwanowww · 2025-09-26T21:43:03Z

src/hotspot/cpu/aarch64/c2_MacroAssembler_aarch64.cpp

 void C2_MacroAssembler::sve_compress_short(FloatRegister dst, FloatRegister src, PRegister mask,
-                                           FloatRegister vtmp1, FloatRegister vtmp2,
-                                           PRegister pgtmp) {
+                                           FloatRegister vtmp, FloatRegister vtmp_zr,


On code style: it's confusing to see a temp register used in non-destructive way to pass a constant. If you want to save on materializing an all 0 vector constant, I suggest to name it differently (e.g., zr) and put the argument before vtmp.

erifan

@iwanowww I have addressed all of your suggestions, thanks for your review.

erifan · 2025-09-29T07:56:09Z

src/hotspot/cpu/aarch64/c2_MacroAssembler_aarch64.cpp

+  // Example input:   src   = q p n m l k j i h g f e d c b a, one character is 8 bits.
+  //                  mask  = 0 1 0 0 0 0 0 1 0 1 0 0 0 1 0 1, one character is 1 bit.
+  // Expected result: dst   = 0 0 0 0 0 0 0 0 0 0 0 p i g c a
+  sve_dup(vtmp3, B, 0);


Done, thanks!

erifan · 2025-09-29T07:58:06Z

src/hotspot/cpu/aarch64/c2_MacroAssembler_aarch64.cpp

 void C2_MacroAssembler::sve_compress_short(FloatRegister dst, FloatRegister src, PRegister mask,
-                                           FloatRegister vtmp1, FloatRegister vtmp2,
-                                           PRegister pgtmp) {
+                                           FloatRegister vtmp, FloatRegister vtmp_zr,


iwanowww

Looks good.

iwanowww · 2025-09-29T18:54:35Z

src/hotspot/cpu/aarch64/c2_MacroAssembler_aarch64.cpp

+  // Example input:   src   = q p n m l k j i h g f e d c b a, one character is 8 bits.
+  //                  mask  = 0 1 0 0 0 0 0 1 0 1 0 0 0 1 0 1, one character is 1 bit.
+  // Expected result: dst   = 0 0 0 0 0 0 0 0 0 0 0 p i g c a
+  sve_dup(vtmp3, B, 0);


The following reads slightly better, but it's up to you how to shape it.

FloatRegister vzr = vtmp3; sve_dup(vzr, B, 0);

jatin-bhateja · 2025-09-30T06:57:34Z

test/hotspot/jtreg/compiler/vectorapi/VectorCompressTest.java

+
+    @Test
+    @IR(counts = { IRNode.COMPRESS_VB, "= 1" },
+        applyIfCPUFeature = { "sve", "true" })


Hi @erifan,
Nice work!,
Can you please also enable these tests for x86? Following are the relevant features.

CompressVB -> avx512_vbmi2, avx512_vl
CompressVS -> avx512_vbmi2. avx512_vl
CompressVI/VF -> avx512f, avx512vl
ComprssVL/VD -> avx512f, avx512vl

PS: avx512_vbmi2 is missing from test/IREncodingPrinter.java

FYI , currently, we don't support sub-word compression intrinsics on AVX2/E-core targets. I created a vectorized algorithm without any x86 backend change just using vector APIs, and it showed 12x improvement.

https://github.com/jatin-bhateja/external_staging/blob/main/VectorizedAlgos/SubwordCompress/short_vector_compress.java

PROMPT>java -cp . --add-modules=jdk.incubator.vector short_vector_compress 0 WARNING: Using incubator modules: jdk.incubator.vector [ baseline time] 976 ms [res] 429507073 PROMPT>java -cp . --add-modules=jdk.incubator.vector short_vector_compress 1 WARNING: Using incubator modules: jdk.incubator.vector [ withopt time] 80 ms [res] 429507073 PROMPT>

Done, please help me check if it is correct, thank you! I have tested it locally.

erifan · 2025-10-07T06:38:50Z

Hi @iwanowww @jatin-bhateja I have addressed your comments, thanks for your review!

jatin-bhateja

Thanks @erifan ,
Verified IR test changes.

erifan · 2025-10-08T09:39:16Z

/contributor add @jatin-bhateja

openjdk · 2025-10-08T09:39:49Z

@erifan
Contributor Jatin Bhateja <jbhateja@openjdk.org> successfully added.

erifan · 2025-10-15T01:34:01Z

Hi, can I integrate this patch now? Could any Oracle friends help me with internal testing of this patch? Thanks~

XiaohongGong

LGTM! Thanks! Reviewed internally.

erifan · 2025-10-20T03:03:24Z

I have tested a lot of different configurations on both aarch64 and x64, including 128/256/512 bits SVE2/SVE/NEON, AVX3/2/1, SSE4/3/2/1. All tests passed, so I'll integrate the PR, thanks for all!
/integrate

openjdk · 2025-10-20T03:05:15Z

@erifan
Your change (at version c75df30) is now ready to be sponsored by a Committer.

XiaohongGong · 2025-10-21T01:18:52Z

/sponsor

openjdk · 2025-10-21T01:20:39Z

Going to push as commit 2de8d58.
Since your change was applied there have been 218 commits pushed to the master branch:

0522cf2: 8370123: Minor jpackage refactoring
c781a2f: 8370136: Support async execution of jpackage tests
a1302e5: 8365625: Can't change accelerator colors in Windows L&F
... and 215 more: https://git.openjdk.org/jdk/compare/eb34a117934951af075a425ce2cf8d3b1ced9700...master

Your commit was automatically rebased without conflicts.

openjdk · 2025-10-21T01:20:47Z

@XiaohongGong @erifan Pushed as commit 2de8d58.

💡 You may see a message that your pull request was closed with unmerged commits. This can be safely ignored.

openjdk bot added the merge-conflict Pull request has merge conflict with target branch label Sep 10, 2025

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src/hotspot/cpu/aarch64/c2_MacroAssembler_aarch64.cpp Show resolved Hide resolved

Merge branch 'master' into JDK-8366333-compress

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erifan added 2 commits September 23, 2025 09:36

Merge branch 'master' into JDK-8366333-compress

d087730

Improve some code style

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erifan commented Sep 23, 2025

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Improve coding style a bit

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erifan added 2 commits October 7, 2025 06:17

Merge branch 'master' into JDK-8366333-compress

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Enable the IR test for x86

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erifan deleted the JDK-8366333-compress branch October 21, 2025 01:46

8366333: AArch64: Enhance SVE subword type implementation of vector compress #27188

8366333: AArch64: Enhance SVE subword type implementation of vector compress #27188

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