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8248188: Add IntrinsicCandidate and API for Base64 decoding #293

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8248188: Add IntrinsicCandidate and API for Base64 decoding #293

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d4733af
Add HotSpotIntrinsicCandidate and API for Base64 decoding
Aug 13, 2020
755f1ff
Add HotSpot code to implement Base64 decodeBlock API
Sep 21, 2020
cb74946
Add Power9+ intrinsic implementation for Base64 decoding
Aug 14, 2020
7fea4e0
Add JMH benchmark for Base64 variable length buffer decoding
Aug 26, 2020
cd2bfb6
Expand the Base64 intrinsic regression test to cover decodeBlock
Sep 15, 2020
853ec00
TestBase64.java: Changes from PR review
Sep 28, 2020
85d7ddb
stubGenerator_ppc.cpp: Changes from PR review
Sep 29, 2020
5574336
Base64.java decodeBlock: Changes from PR review
Sep 30, 2020
e42ac7d
AOT: Revert change to aotCodeHeap.cpp for decodeBlock
Oct 5, 2020
7711d7d
library_call.cpp: Fix rebase merge error
Oct 7, 2020
1192a55
Base64.java: Make changes as per Roger Riggs and Martin Doerr's v2 Re…
Oct 7, 2020
c2942b3
TestBase64.java: Change comment as per Martin Doerr's v2 review
Oct 7, 2020
c1f6233
runtime.cpp: per Martin Doerr's review of v2, correct comment as per …
Oct 7, 2020
64f0b80
vmIntrinsics.cpp: Per Martin Doerr's v2 review: rearrange order of ca…
Oct 7, 2020
5ecac98
vm_version_ppc.cpp: per Martin Doerr's review of v2: fix copy/paste e…
Oct 7, 2020
8932c23
stubGenerator_ppc.cpp: Fix multiple issues as per Martin Doerr's v2 r…
Oct 7, 2020
c8110d1
stubGenerator_ppc.cpp: fix regression caused by change to using loop …
Oct 8, 2020
164fa2a
TestBase64.java: fix comment to correctly reflect actual intrinsic na…
Oct 8, 2020
b5acb75
Per Martin Doerr's v4 review: fix regression, and speed up return tim…
Oct 12, 2020
46cb103
stubGenerator_ppc.cpp: remove unnecessary complexity for checking < 0…
Oct 20, 2020
d9b18e9
Merge branch 'master' of https://git.openjdk.java.net/jdk into base64…
Oct 20, 2020
dcd15d5
CheckGraalIntrinsics.java: Disable testing of decodeBlock intrinsic u…
Oct 21, 2020
f93614d
CheckGraalIntrinsics.java: fix copy/paste error
Oct 21, 2020
8e15d97
TestBase64.java: remove jdk.test.lib.Utils from @build which was caus…
Oct 21, 2020
b958c02
stubGenerator_ppc.cpp: address issues with understanding the pack alg…
Nov 3, 2020
0e291be
stubGenerator_ppc.cpp: Remove the predicted branch around the xxsel i…
Nov 3, 2020
8292527
stubGenerator_ppc.cpp: fix trailing whitespace errors
Nov 3, 2020
c4d22da
stubGenerator_ppc.cpp: reduce loop_unrolls to 1 to match new benchmar…
Nov 4, 2020
9e303da
stubGenerator_ppc.cpp: fix typo (omitted 'the')
Nov 5, 2020
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21 changes: 21 additions & 0 deletions src/hotspot/cpu/ppc/assembler_ppc.hpp
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Expand Up @@ -519,6 +519,8 @@ class Assembler : public AbstractAssembler {
LVSR_OPCODE = (31u << OPCODE_SHIFT | 38u << 1),

// Vector-Scalar (VSX) instruction support.
LXV_OPCODE = (61u << OPCODE_SHIFT | 1u ),
STXV_OPCODE = (61u << OPCODE_SHIFT | 5u ),
LXVD2X_OPCODE = (31u << OPCODE_SHIFT | 844u << 1),
STXVD2X_OPCODE = (31u << OPCODE_SHIFT | 972u << 1),
MTVSRD_OPCODE = (31u << OPCODE_SHIFT | 179u << 1),
Expand All @@ -530,12 +532,16 @@ class Assembler : public AbstractAssembler {
XXMRGHW_OPCODE = (60u << OPCODE_SHIFT | 18u << 3),
XXMRGLW_OPCODE = (60u << OPCODE_SHIFT | 50u << 3),
XXSPLTW_OPCODE = (60u << OPCODE_SHIFT | 164u << 2),
XXLAND_OPCODE = (60u << OPCODE_SHIFT | 130u << 3),
XXLOR_OPCODE = (60u << OPCODE_SHIFT | 146u << 3),
XXLXOR_OPCODE = (60u << OPCODE_SHIFT | 154u << 3),
XXLEQV_OPCODE = (60u << OPCODE_SHIFT | 186u << 3),
XVDIVSP_OPCODE = (60u << OPCODE_SHIFT | 88u << 3),
XXBRD_OPCODE = (60u << OPCODE_SHIFT | 475u << 2 | 23u << 16), // XX2-FORM
XXBRW_OPCODE = (60u << OPCODE_SHIFT | 475u << 2 | 15u << 16), // XX2-FORM
XXPERM_OPCODE = (60u << OPCODE_SHIFT | 26u << 3),
XXSEL_OPCODE = (60u << OPCODE_SHIFT | 3u << 4),
XXSPLTIB_OPCODE= (60u << OPCODE_SHIFT | 360u << 1),
XVDIVDP_OPCODE = (60u << OPCODE_SHIFT | 120u << 3),
XVABSSP_OPCODE = (60u << OPCODE_SHIFT | 409u << 2),
XVABSDP_OPCODE = (60u << OPCODE_SHIFT | 473u << 2),
Expand Down Expand Up @@ -592,6 +598,7 @@ class Assembler : public AbstractAssembler {
VSPLTISH_OPCODE= (4u << OPCODE_SHIFT | 844u ),
VSPLTISW_OPCODE= (4u << OPCODE_SHIFT | 908u ),

VPEXTD_OPCODE = (4u << OPCODE_SHIFT | 1421u ),
VPERM_OPCODE = (4u << OPCODE_SHIFT | 43u ),
VSEL_OPCODE = (4u << OPCODE_SHIFT | 42u ),

Expand Down Expand Up @@ -1099,6 +1106,7 @@ class Assembler : public AbstractAssembler {
static int frs( int x) { return opp_u_field(x, 10, 6); }
static int frt( int x) { return opp_u_field(x, 10, 6); }
static int fxm( int x) { return opp_u_field(x, 19, 12); }
static int imm8( int x) { return opp_u_field(uimm(x, 8), 20, 13); }
static int l10( int x) { assert(x == 0 || x == 1, "must be 0 or 1"); return opp_u_field(x, 10, 10); }
static int l14( int x) { return opp_u_field(x, 15, 14); }
static int l15( int x) { return opp_u_field(x, 15, 15); }
Expand Down Expand Up @@ -1165,14 +1173,20 @@ class Assembler : public AbstractAssembler {
// Support Vector-Scalar (VSX) instructions.
static int vsra( int x) { return opp_u_field(x & 0x1F, 15, 11) | opp_u_field((x & 0x20) >> 5, 29, 29); }
static int vsrb( int x) { return opp_u_field(x & 0x1F, 20, 16) | opp_u_field((x & 0x20) >> 5, 30, 30); }
static int vsrc( int x) { return opp_u_field(x & 0x1F, 25, 21) | opp_u_field((x & 0x20) >> 5, 28, 28); }
static int vsrs( int x) { return opp_u_field(x & 0x1F, 10, 6) | opp_u_field((x & 0x20) >> 5, 31, 31); }
static int vsrt( int x) { return vsrs(x); }
static int vsdm( int x) { return opp_u_field(x, 23, 22); }
static int vsrs_dq( int x) { return opp_u_field(x & 0x1F, 10, 6) | opp_u_field((x & 0x20) >> 5, 28, 28); }
static int vsrt_dq( int x) { return vsrs_dq(x); }

static int vsra( VectorSRegister r) { return vsra(r->encoding());}
static int vsrb( VectorSRegister r) { return vsrb(r->encoding());}
static int vsrc( VectorSRegister r) { return vsrc(r->encoding());}
static int vsrs( VectorSRegister r) { return vsrs(r->encoding());}
static int vsrt( VectorSRegister r) { return vsrt(r->encoding());}
static int vsrs_dq(VectorSRegister r) { return vsrs_dq(r->encoding());}
static int vsrt_dq(VectorSRegister r) { return vsrt_dq(r->encoding());}

static int vsplt_uim( int x) { return opp_u_field(x, 15, 12); } // for vsplt* instructions
static int vsplti_sim(int x) { return opp_u_field(x, 15, 11); } // for vsplti* instructions
Expand Down Expand Up @@ -2119,6 +2133,7 @@ class Assembler : public AbstractAssembler {
inline void vspltish( VectorRegister d, int si5);
inline void vspltisw( VectorRegister d, int si5);
inline void vperm( VectorRegister d, VectorRegister a, VectorRegister b, VectorRegister c);
inline void vpextd( VectorRegister d, VectorRegister a, VectorRegister b);
inline void vsel( VectorRegister d, VectorRegister a, VectorRegister b, VectorRegister c);
inline void vsl( VectorRegister d, VectorRegister a, VectorRegister b);
inline void vsldoi( VectorRegister d, VectorRegister a, VectorRegister b, int ui4);
Expand Down Expand Up @@ -2235,6 +2250,8 @@ class Assembler : public AbstractAssembler {
inline void mfvscr( VectorRegister d);

// Vector-Scalar (VSX) instructions.
inline void lxv( VectorSRegister d, int si16, Register a);
inline void stxv( VectorSRegister d, int si16, Register a);
inline void lxvd2x( VectorSRegister d, Register a);
inline void lxvd2x( VectorSRegister d, Register a, Register b);
inline void stxvd2x( VectorSRegister d, Register a);
Expand All @@ -2243,6 +2260,7 @@ class Assembler : public AbstractAssembler {
inline void mfvrwz( Register a, VectorRegister d);
inline void mtvrd( VectorRegister d, Register a);
inline void mfvrd( Register a, VectorRegister d);
inline void xxperm( VectorSRegister d, VectorSRegister a, VectorSRegister b);
inline void xxpermdi( VectorSRegister d, VectorSRegister a, VectorSRegister b, int dm);
inline void xxmrghw( VectorSRegister d, VectorSRegister a, VectorSRegister b);
inline void xxmrglw( VectorSRegister d, VectorSRegister a, VectorSRegister b);
Expand All @@ -2256,6 +2274,9 @@ class Assembler : public AbstractAssembler {
inline void xxleqv( VectorSRegister d, VectorSRegister a, VectorSRegister b);
inline void xxbrd( VectorSRegister d, VectorSRegister b);
inline void xxbrw( VectorSRegister d, VectorSRegister b);
inline void xxland( VectorSRegister d, VectorSRegister a, VectorSRegister b);
inline void xxsel( VectorSRegister d, VectorSRegister a, VectorSRegister b, VectorSRegister c);
inline void xxspltib( VectorSRegister d, int ui8);
inline void xvdivsp( VectorSRegister d, VectorSRegister a, VectorSRegister b);
inline void xvdivdp( VectorSRegister d, VectorSRegister a, VectorSRegister b);
inline void xvabssp( VectorSRegister d, VectorSRegister b);
Expand Down
7 changes: 7 additions & 0 deletions src/hotspot/cpu/ppc/assembler_ppc.inline.hpp
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Expand Up @@ -776,6 +776,8 @@ inline void Assembler::lvsl( VectorRegister d, Register s1, Register s2) { emit
inline void Assembler::lvsr( VectorRegister d, Register s1, Register s2) { emit_int32( LVSR_OPCODE | vrt(d) | ra0mem(s1) | rb(s2)); }

// Vector-Scalar (VSX) instructions.
inline void Assembler::lxv( VectorSRegister d, int ui16, Register a) { assert(is_aligned(ui16, 16), "displacement must be a multiple of 16"); emit_int32( LXV_OPCODE | vsrt_dq(d) | ra0mem(a) | uimm(ui16, 16)); }
inline void Assembler::stxv( VectorSRegister d, int ui16, Register a) { assert(is_aligned(ui16, 16), "displacement must be a multiple of 16"); emit_int32( STXV_OPCODE | vsrs_dq(d) | ra0mem(a) | uimm(ui16, 16)); }
inline void Assembler::lxvd2x( VectorSRegister d, Register s1) { emit_int32( LXVD2X_OPCODE | vsrt(d) | ra(0) | rb(s1)); }
inline void Assembler::lxvd2x( VectorSRegister d, Register s1, Register s2) { emit_int32( LXVD2X_OPCODE | vsrt(d) | ra0mem(s1) | rb(s2)); }
inline void Assembler::stxvd2x( VectorSRegister d, Register s1) { emit_int32( STXVD2X_OPCODE | vsrs(d) | ra(0) | rb(s1)); }
Expand All @@ -784,7 +786,9 @@ inline void Assembler::mtvsrd( VectorSRegister d, Register a) { e
inline void Assembler::mfvsrd( Register d, VectorSRegister a) { emit_int32( MFVSRD_OPCODE | vsrs(a) | ra(d)); }
inline void Assembler::mtvsrwz( VectorSRegister d, Register a) { emit_int32( MTVSRWZ_OPCODE | vsrt(d) | ra(a)); }
inline void Assembler::mfvsrwz( Register d, VectorSRegister a) { emit_int32( MFVSRWZ_OPCODE | vsrs(a) | ra(d)); }
inline void Assembler::xxspltib(VectorSRegister d, int ui8) { emit_int32( XXSPLTIB_OPCODE | vsrt(d) | imm8(ui8)); }
inline void Assembler::xxspltw( VectorSRegister d, VectorSRegister b, int ui2) { emit_int32( XXSPLTW_OPCODE | vsrt(d) | vsrb(b) | xxsplt_uim(uimm(ui2,2))); }
inline void Assembler::xxland( VectorSRegister d, VectorSRegister a, VectorSRegister b) { emit_int32( XXLAND_OPCODE | vsrt(d) | vsra(a) | vsrb(b)); }
inline void Assembler::xxlor( VectorSRegister d, VectorSRegister a, VectorSRegister b) { emit_int32( XXLOR_OPCODE | vsrt(d) | vsra(a) | vsrb(b)); }
inline void Assembler::xxlxor( VectorSRegister d, VectorSRegister a, VectorSRegister b) { emit_int32( XXLXOR_OPCODE | vsrt(d) | vsra(a) | vsrb(b)); }
inline void Assembler::xxleqv( VectorSRegister d, VectorSRegister a, VectorSRegister b) { emit_int32( XXLEQV_OPCODE | vsrt(d) | vsra(a) | vsrb(b)); }
Expand Down Expand Up @@ -817,9 +821,11 @@ inline void Assembler::mtvrd( VectorRegister d, Register a) { em
inline void Assembler::mfvrd( Register a, VectorRegister d) { emit_int32( MFVSRD_OPCODE | vsrt(d->to_vsr()) | ra(a)); }
inline void Assembler::mtvrwz( VectorRegister d, Register a) { emit_int32( MTVSRWZ_OPCODE | vsrt(d->to_vsr()) | ra(a)); }
inline void Assembler::mfvrwz( Register a, VectorRegister d) { emit_int32( MFVSRWZ_OPCODE | vsrt(d->to_vsr()) | ra(a)); }
inline void Assembler::xxperm( VectorSRegister d, VectorSRegister a, VectorSRegister b) { emit_int32( XXPERM_OPCODE | vsrt(d) | vsra(a) | vsrb(b)); }
inline void Assembler::xxpermdi(VectorSRegister d, VectorSRegister a, VectorSRegister b, int dm) { emit_int32( XXPERMDI_OPCODE | vsrt(d) | vsra(a) | vsrb(b) | vsdm(dm)); }
inline void Assembler::xxmrghw( VectorSRegister d, VectorSRegister a, VectorSRegister b) { emit_int32( XXMRGHW_OPCODE | vsrt(d) | vsra(a) | vsrb(b)); }
inline void Assembler::xxmrglw( VectorSRegister d, VectorSRegister a, VectorSRegister b) { emit_int32( XXMRGHW_OPCODE | vsrt(d) | vsra(a) | vsrb(b)); }
inline void Assembler::xxsel( VectorSRegister d, VectorSRegister a, VectorSRegister b, VectorSRegister c) { emit_int32( XXSEL_OPCODE | vsrt(d) | vsra(a) | vsrb(b) | vsrc(c)); }

// VSX Extended Mnemonics
inline void Assembler::xxspltd( VectorSRegister d, VectorSRegister a, int x) { xxpermdi(d, a, a, x ? 3 : 0); }
Expand Down Expand Up @@ -860,6 +866,7 @@ inline void Assembler::vspltisb(VectorRegister d, int si5)
inline void Assembler::vspltish(VectorRegister d, int si5) { emit_int32( VSPLTISH_OPCODE| vrt(d) | vsplti_sim(simm(si5,5))); }
inline void Assembler::vspltisw(VectorRegister d, int si5) { emit_int32( VSPLTISW_OPCODE| vrt(d) | vsplti_sim(simm(si5,5))); }
inline void Assembler::vperm( VectorRegister d, VectorRegister a, VectorRegister b, VectorRegister c){ emit_int32( VPERM_OPCODE | vrt(d) | vra(a) | vrb(b) | vrc(c)); }
inline void Assembler::vpextd( VectorRegister d, VectorRegister a, VectorRegister b) { emit_int32( VPEXTD_OPCODE| vrt(d) | vra(a) | vrb(b)); }
inline void Assembler::vsel( VectorRegister d, VectorRegister a, VectorRegister b, VectorRegister c){ emit_int32( VSEL_OPCODE | vrt(d) | vra(a) | vrb(b) | vrc(c)); }
inline void Assembler::vsl( VectorRegister d, VectorRegister a, VectorRegister b) { emit_int32( VSL_OPCODE | vrt(d) | vra(a) | vrb(b)); }
inline void Assembler::vsldoi( VectorRegister d, VectorRegister a, VectorRegister b, int ui4) { emit_int32( VSLDOI_OPCODE| vrt(d) | vra(a) | vrb(b) | vsldoi_shb(uimm(ui4,4))); }
Expand Down