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8264543: Cross modify fence optimization for x86 #3334

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@@ -85,6 +85,7 @@
declare_constant(VM_Version::CPU_CLWB) \
declare_constant(VM_Version::CPU_AVX512_VBMI2) \
declare_constant(VM_Version::CPU_AVX512_VBMI) \
declare_constant(VM_Version::CPU_HV)
declare_constant(VM_Version::CPU_HV) \
declare_constant(VM_Version::CPU_SERIALIZE)

#endif // CPU_X86_VMSTRUCTS_X86_HPP
@@ -261,7 +261,9 @@ class VM_Version : public Abstract_VM_Version {
uint32_t : 2,
avx512_4vnniw : 1,
avx512_4fmaps : 1,
: 28;
: 10,
serialize : 1,
: 17;
} bits;
};

@@ -359,8 +361,9 @@ class VM_Version : public Abstract_VM_Version {
CPU_AVX512_VBMI2 = (1ULL << 44), // VBMI2 shift left double instructions
CPU_AVX512_VBMI = (1ULL << 45), // Vector BMI instructions
CPU_HV = (1ULL << 46), // Hypervisor instructions
CPU_SERIALIZE = (1ULL << 47), // CPU SERIALIZE

CPU_MAX_FEATURE = CPU_HV
CPU_MAX_FEATURE = CPU_SERIALIZE
};

#define FEATURES_NAMES \
@@ -375,7 +378,7 @@ class VM_Version : public Abstract_VM_Version {
"avx512bw", "avx512vl", "sha", "fma", \
"vzeroupper", "avx512_vpopcntdq", "avx512_vpclmulqdq", "avx512_vaes", \
"avx512_vnni", "clflush", "clflushopt", "clwb", \
"avx512_vmbi2", "avx512_vmbi", "hv"
"avx512_vmbi2", "avx512_vmbi", "hv", "serialize"

static const char* _features_names[];

@@ -659,6 +662,8 @@ enum Extended_Family {
if (_cpuid_info.sef_cpuid7_ebx.bits.clwb != 0) {
result |= CPU_CLWB;
}
if (_cpuid_info.sef_cpuid7_edx.bits.serialize != 0)
result |= CPU_SERIALIZE;
}

// ZX features.
@@ -912,6 +917,7 @@ enum Extended_Family {
static bool supports_avx512_vbmi() { return (_features & CPU_AVX512_VBMI) != 0; }
static bool supports_avx512_vbmi2() { return (_features & CPU_AVX512_VBMI2) != 0; }
static bool supports_hv() { return (_features & CPU_HV) != 0; }
static bool supports_serialize() { return (_features & CPU_SERIALIZE) != 0; }

// Intel features
static bool is_intel_family_core() { return is_intel() &&
@@ -25,6 +25,7 @@
#ifndef OS_CPU_LINUX_X86_ORDERACCESS_LINUX_X86_HPP
#define OS_CPU_LINUX_X86_ORDERACCESS_LINUX_X86_HPP

#include OS_HEADER_INLINE(os)
// Included in orderAccess.hpp header file.

// Compiler version last used for testing: gcc 4.8.2
@@ -56,14 +57,18 @@ inline void OrderAccess::fence() {
}

inline void OrderAccess::cross_modify_fence_impl() {
int idx = 0;
if (os::supports_serialize()) {
__asm__ volatile (".byte 0x0f, 0x01, 0xe8\n\t" : : :); //serialize
} else {
int idx = 0;
#ifdef AMD64
__asm__ volatile ("cpuid " : "+a" (idx) : : "ebx", "ecx", "edx", "memory");
__asm__ volatile ("cpuid " : "+a" (idx) : : "ebx", "ecx", "edx", "memory");
#else
// On some x86 systems EBX is a reserved register that cannot be
// clobbered, so we must protect it around the CPUID.
__asm__ volatile ("xchg %%esi, %%ebx; cpuid; xchg %%esi, %%ebx " : "+a" (idx) : : "esi", "ecx", "edx", "memory");
// On some x86 systems EBX is a reserved register that cannot be
// clobbered, so we must protect it around the CPUID.
__asm__ volatile ("xchg %%esi, %%ebx; cpuid; xchg %%esi, %%ebx " : "+a" (idx) : : "esi", "ecx", "edx", "memory");
#endif
}
}

#endif // OS_CPU_LINUX_X86_ORDERACCESS_LINUX_X86_HPP
@@ -458,6 +458,10 @@ bool os::supports_sse() {
#endif // AMD64
}

bool os::supports_serialize(){
return VM_Version::supports_serialize();
}

juint os::cpu_microcode_revision() {
juint result = 0;
char data[2048] = {0}; // lines should fit in 2K buf
@@ -27,6 +27,7 @@

static void setup_fpu();
static bool supports_sse();
static bool supports_serialize();
static juint cpu_microcode_revision();

static jlong rdtsc();
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