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8262916: Merge LShiftCntV and RShiftCntV into a single node #3371

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@@ -5069,29 +5069,52 @@ instruct vxor16B(vecX dst, vecX src1, vecX src2)

// ------------------------------ Shift ---------------------------------------

instruct vshiftcnt8B(vecD dst, iRegIorL2I cnt) %{
instruct lvshiftcnt8B(vecD dst, iRegIorL2I cnt) %{
predicate(n->as_Vector()->length_in_bytes() == 4 ||
n->as_Vector()->length_in_bytes() == 8);
match(Set dst (LShiftCntV cnt));
match(Set dst (RShiftCntV cnt));
format %{ "dup $dst, $cnt\t# shift count vector (8B)" %}
ins_encode %{
__ dup(as_FloatRegister($dst$$reg), __ T8B, as_Register($cnt$$reg));
%}
ins_pipe(vdup_reg_reg64);
%}

instruct vshiftcnt16B(vecX dst, iRegIorL2I cnt) %{
instruct lvshiftcnt16B(vecX dst, iRegIorL2I cnt) %{
predicate(n->as_Vector()->length_in_bytes() == 16);
match(Set dst (LShiftCntV cnt));
match(Set dst (RShiftCntV cnt));
format %{ "dup $dst, $cnt\t# shift count vector (16B)" %}
ins_encode %{
__ dup(as_FloatRegister($dst$$reg), __ T16B, as_Register($cnt$$reg));
%}
ins_pipe(vdup_reg_reg128);
%}

instruct rvshiftcnt8B(vecD dst, iRegIorL2I cnt, vecD tmp) %{
predicate(n->as_Vector()->length_in_bytes() == 4 ||
n->as_Vector()->length_in_bytes() == 8);
match(Set dst (RShiftCntV cnt));
effect(TEMP tmp);
format %{ "dup $dst, $cnt\t# shift count vector (8B)" %}
ins_encode %{
__ dup(as_FloatRegister($tmp$$reg), __ T8B, as_Register($cnt$$reg));
__ negr(as_FloatRegister($dst$$reg), __ T8B, as_FloatRegister($tmp$$reg));
%}
ins_pipe(vdup_reg_reg64);
%}

instruct rvshiftcnt16B(vecX dst, iRegIorL2I cnt, vecX tmp) %{
predicate(n->as_Vector()->length_in_bytes() == 16);
match(Set dst (RShiftCntV cnt));
effect(TEMP tmp);
format %{ "dup $dst, $cnt\t# shift count vector (16B)" %}
ins_encode %{
__ dup(as_FloatRegister($tmp$$reg), __ T16B, as_Register($cnt$$reg));
__ negr(as_FloatRegister($dst$$reg), __ T16B, as_FloatRegister($tmp$$reg));
%}
ins_pipe(vdup_reg_reg128);
%}

instruct vsll8B(vecD dst, vecD src, vecD shift) %{
predicate(n->as_Vector()->length() == 4 ||
n->as_Vector()->length() == 8);
@@ -5140,72 +5163,56 @@ instruct vsll16B(vecX dst, vecX src, vecX shift) %{
// RShiftVI
//

instruct vsra8B(vecD dst, vecD src, vecD shift, vecD tmp) %{
instruct vsra8B(vecD dst, vecD src, vecD shift) %{
predicate(n->as_Vector()->length() == 4 ||
n->as_Vector()->length() == 8);
match(Set dst (RShiftVB src shift));
ins_cost(INSN_COST);
effect(TEMP tmp);
format %{ "negr $tmp,$shift\t"
"sshl $dst,$src,$tmp\t# vector (8B)" %}
format %{ "sshl $dst,$src,$shift\t# vector (8B)" %}
ins_encode %{
__ negr(as_FloatRegister($tmp$$reg), __ T8B,
as_FloatRegister($shift$$reg));
__ sshl(as_FloatRegister($dst$$reg), __ T8B,
as_FloatRegister($src$$reg),
as_FloatRegister($tmp$$reg));
as_FloatRegister($shift$$reg));
%}
ins_pipe(vshift64);
%}

instruct vsra16B(vecX dst, vecX src, vecX shift, vecX tmp) %{
instruct vsra16B(vecX dst, vecX src, vecX shift) %{
predicate(n->as_Vector()->length() == 16);
match(Set dst (RShiftVB src shift));
ins_cost(INSN_COST);
effect(TEMP tmp);
format %{ "negr $tmp,$shift\t"
"sshl $dst,$src,$tmp\t# vector (16B)" %}
format %{ "sshl $dst,$src,$shift\t# vector (16B)" %}
ins_encode %{
__ negr(as_FloatRegister($tmp$$reg), __ T16B,
as_FloatRegister($shift$$reg));
__ sshl(as_FloatRegister($dst$$reg), __ T16B,
as_FloatRegister($src$$reg),
as_FloatRegister($tmp$$reg));
as_FloatRegister($shift$$reg));
%}
ins_pipe(vshift128);
%}

instruct vsrl8B(vecD dst, vecD src, vecD shift, vecD tmp) %{
instruct vsrl8B(vecD dst, vecD src, vecD shift) %{
predicate(n->as_Vector()->length() == 4 ||
n->as_Vector()->length() == 8);
match(Set dst (URShiftVB src shift));
ins_cost(INSN_COST);
effect(TEMP tmp);
format %{ "negr $tmp,$shift\t"
"ushl $dst,$src,$tmp\t# vector (8B)" %}
format %{ "ushl $dst,$src,$shift\t# vector (8B)" %}
ins_encode %{
__ negr(as_FloatRegister($tmp$$reg), __ T8B,
as_FloatRegister($shift$$reg));
__ ushl(as_FloatRegister($dst$$reg), __ T8B,
as_FloatRegister($src$$reg),
as_FloatRegister($tmp$$reg));
as_FloatRegister($shift$$reg));
%}
ins_pipe(vshift64);
%}

instruct vsrl16B(vecX dst, vecX src, vecX shift, vecX tmp) %{
instruct vsrl16B(vecX dst, vecX src, vecX shift) %{
predicate(n->as_Vector()->length() == 16);
match(Set dst (URShiftVB src shift));
ins_cost(INSN_COST);
effect(TEMP tmp);
format %{ "negr $tmp,$shift\t"
"ushl $dst,$src,$tmp\t# vector (16B)" %}
format %{ "ushl $dst,$src,$shift\t# vector (16B)" %}
ins_encode %{
__ negr(as_FloatRegister($tmp$$reg), __ T16B,
as_FloatRegister($shift$$reg));
__ ushl(as_FloatRegister($dst$$reg), __ T16B,
as_FloatRegister($src$$reg),
as_FloatRegister($tmp$$reg));
as_FloatRegister($shift$$reg));
%}
ins_pipe(vshift128);
%}
@@ -5344,72 +5351,56 @@ instruct vsll8S(vecX dst, vecX src, vecX shift) %{
ins_pipe(vshift128);
%}

instruct vsra4S(vecD dst, vecD src, vecD shift, vecD tmp) %{
instruct vsra4S(vecD dst, vecD src, vecD shift) %{
predicate(n->as_Vector()->length() == 2 ||
n->as_Vector()->length() == 4);
match(Set dst (RShiftVS src shift));
ins_cost(INSN_COST);
effect(TEMP tmp);
format %{ "negr $tmp,$shift\t"
"sshl $dst,$src,$tmp\t# vector (4H)" %}
format %{ "sshl $dst,$src,$shift\t# vector (4H)" %}
ins_encode %{
__ negr(as_FloatRegister($tmp$$reg), __ T8B,
as_FloatRegister($shift$$reg));
__ sshl(as_FloatRegister($dst$$reg), __ T4H,
as_FloatRegister($src$$reg),
as_FloatRegister($tmp$$reg));
as_FloatRegister($shift$$reg));
%}
ins_pipe(vshift64);
%}

instruct vsra8S(vecX dst, vecX src, vecX shift, vecX tmp) %{
instruct vsra8S(vecX dst, vecX src, vecX shift) %{
predicate(n->as_Vector()->length() == 8);
match(Set dst (RShiftVS src shift));
ins_cost(INSN_COST);
effect(TEMP tmp);
format %{ "negr $tmp,$shift\t"
"sshl $dst,$src,$tmp\t# vector (8H)" %}
format %{ "sshl $dst,$src,$shift\t# vector (8H)" %}
ins_encode %{
__ negr(as_FloatRegister($tmp$$reg), __ T16B,
as_FloatRegister($shift$$reg));
__ sshl(as_FloatRegister($dst$$reg), __ T8H,
as_FloatRegister($src$$reg),
as_FloatRegister($tmp$$reg));
as_FloatRegister($shift$$reg));
%}
ins_pipe(vshift128);
%}

instruct vsrl4S(vecD dst, vecD src, vecD shift, vecD tmp) %{
instruct vsrl4S(vecD dst, vecD src, vecD shift) %{
predicate(n->as_Vector()->length() == 2 ||
n->as_Vector()->length() == 4);
match(Set dst (URShiftVS src shift));
ins_cost(INSN_COST);
effect(TEMP tmp);
format %{ "negr $tmp,$shift\t"
"ushl $dst,$src,$tmp\t# vector (4H)" %}
format %{ "ushl $dst,$src,$shift\t# vector (4H)" %}
ins_encode %{
__ negr(as_FloatRegister($tmp$$reg), __ T8B,
as_FloatRegister($shift$$reg));
__ ushl(as_FloatRegister($dst$$reg), __ T4H,
as_FloatRegister($src$$reg),
as_FloatRegister($tmp$$reg));
as_FloatRegister($shift$$reg));
%}
ins_pipe(vshift64);
%}

instruct vsrl8S(vecX dst, vecX src, vecX shift, vecX tmp) %{
instruct vsrl8S(vecX dst, vecX src, vecX shift) %{
predicate(n->as_Vector()->length() == 8);
match(Set dst (URShiftVS src shift));
ins_cost(INSN_COST);
effect(TEMP tmp);
format %{ "negr $tmp,$shift\t"
"ushl $dst,$src,$tmp\t# vector (8H)" %}
format %{ "ushl $dst,$src,$shift\t# vector (8H)" %}
ins_encode %{
__ negr(as_FloatRegister($tmp$$reg), __ T16B,
as_FloatRegister($shift$$reg));
__ ushl(as_FloatRegister($dst$$reg), __ T8H,
as_FloatRegister($src$$reg),
as_FloatRegister($tmp$$reg));
as_FloatRegister($shift$$reg));
%}
ins_pipe(vshift128);
%}
@@ -5547,70 +5538,54 @@ instruct vsll4I(vecX dst, vecX src, vecX shift) %{
ins_pipe(vshift128);
%}

instruct vsra2I(vecD dst, vecD src, vecD shift, vecD tmp) %{
instruct vsra2I(vecD dst, vecD src, vecD shift) %{
predicate(n->as_Vector()->length() == 2);
match(Set dst (RShiftVI src shift));
ins_cost(INSN_COST);
effect(TEMP tmp);
format %{ "negr $tmp,$shift\t"
"sshl $dst,$src,$tmp\t# vector (2S)" %}
format %{ "sshl $dst,$src,$shift\t# vector (2S)" %}
ins_encode %{
__ negr(as_FloatRegister($tmp$$reg), __ T8B,
as_FloatRegister($shift$$reg));
__ sshl(as_FloatRegister($dst$$reg), __ T2S,
as_FloatRegister($src$$reg),
as_FloatRegister($tmp$$reg));
as_FloatRegister($shift$$reg));
%}
ins_pipe(vshift64);
%}

instruct vsra4I(vecX dst, vecX src, vecX shift, vecX tmp) %{
instruct vsra4I(vecX dst, vecX src, vecX shift) %{
predicate(n->as_Vector()->length() == 4);
match(Set dst (RShiftVI src shift));
ins_cost(INSN_COST);
effect(TEMP tmp);
format %{ "negr $tmp,$shift\t"
"sshl $dst,$src,$tmp\t# vector (4S)" %}
format %{ "sshl $dst,$src,$shift\t# vector (4S)" %}
ins_encode %{
__ negr(as_FloatRegister($tmp$$reg), __ T16B,
as_FloatRegister($shift$$reg));
__ sshl(as_FloatRegister($dst$$reg), __ T4S,
as_FloatRegister($src$$reg),
as_FloatRegister($tmp$$reg));
as_FloatRegister($shift$$reg));
%}
ins_pipe(vshift128);
%}

instruct vsrl2I(vecD dst, vecD src, vecD shift, vecD tmp) %{
instruct vsrl2I(vecD dst, vecD src, vecD shift) %{
predicate(n->as_Vector()->length() == 2);
match(Set dst (URShiftVI src shift));
ins_cost(INSN_COST);
effect(TEMP tmp);
format %{ "negr $tmp,$shift\t"
"ushl $dst,$src,$tmp\t# vector (2S)" %}
format %{ "ushl $dst,$src,$shift\t# vector (2S)" %}
ins_encode %{
__ negr(as_FloatRegister($tmp$$reg), __ T8B,
as_FloatRegister($shift$$reg));
__ ushl(as_FloatRegister($dst$$reg), __ T2S,
as_FloatRegister($src$$reg),
as_FloatRegister($tmp$$reg));
as_FloatRegister($shift$$reg));
%}
ins_pipe(vshift64);
%}

instruct vsrl4I(vecX dst, vecX src, vecX shift, vecX tmp) %{
instruct vsrl4I(vecX dst, vecX src, vecX shift) %{
predicate(n->as_Vector()->length() == 4);
match(Set dst (URShiftVI src shift));
ins_cost(INSN_COST);
effect(TEMP tmp);
format %{ "negr $tmp,$shift\t"
"ushl $dst,$src,$tmp\t# vector (4S)" %}
format %{ "ushl $dst,$src,$shift\t# vector (4S)" %}
ins_encode %{
__ negr(as_FloatRegister($tmp$$reg), __ T16B,
as_FloatRegister($shift$$reg));
__ ushl(as_FloatRegister($dst$$reg), __ T4S,
as_FloatRegister($src$$reg),
as_FloatRegister($tmp$$reg));
as_FloatRegister($shift$$reg));
%}
ins_pipe(vshift128);
%}
@@ -5706,36 +5681,28 @@ instruct vsll2L(vecX dst, vecX src, vecX shift) %{
ins_pipe(vshift128);
%}

instruct vsra2L(vecX dst, vecX src, vecX shift, vecX tmp) %{
instruct vsra2L(vecX dst, vecX src, vecX shift) %{
predicate(n->as_Vector()->length() == 2);
match(Set dst (RShiftVL src shift));
ins_cost(INSN_COST);
effect(TEMP tmp);
format %{ "negr $tmp,$shift\t"
"sshl $dst,$src,$tmp\t# vector (2D)" %}
format %{ "sshl $dst,$src,$shift\t# vector (2D)" %}
ins_encode %{
__ negr(as_FloatRegister($tmp$$reg), __ T16B,
as_FloatRegister($shift$$reg));
__ sshl(as_FloatRegister($dst$$reg), __ T2D,
as_FloatRegister($src$$reg),
as_FloatRegister($tmp$$reg));
as_FloatRegister($shift$$reg));
%}
ins_pipe(vshift128);
%}

instruct vsrl2L(vecX dst, vecX src, vecX shift, vecX tmp) %{
instruct vsrl2L(vecX dst, vecX src, vecX shift) %{
predicate(n->as_Vector()->length() == 2);
match(Set dst (URShiftVL src shift));
ins_cost(INSN_COST);
effect(TEMP tmp);
format %{ "negr $tmp,$shift\t"
"ushl $dst,$src,$tmp\t# vector (2D)" %}
format %{ "ushl $dst,$src,$shift\t# vector (2D)" %}
ins_encode %{
__ negr(as_FloatRegister($tmp$$reg), __ T16B,
as_FloatRegister($shift$$reg));
__ ushl(as_FloatRegister($dst$$reg), __ T2D,
as_FloatRegister($src$$reg),
as_FloatRegister($tmp$$reg));
as_FloatRegister($shift$$reg));
%}
ins_pipe(vshift128);
%}
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