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8280867: Cpuid1Ecx feature parsing is incorrect for AMD CPUs
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Reviewed-by: mdoerr
Backport-of: a18beb4797a1ca6fc6b31e997be48b2bd91c6ac0
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GoeLin committed Apr 5, 2022
1 parent fee03ea commit 7f8a11b
Showing 1 changed file with 9 additions and 10 deletions.
19 changes: 9 additions & 10 deletions src/hotspot/cpu/x86/vm_version_x86.hpp
@@ -1,5 +1,5 @@
/*
* Copyright (c) 1997, 2021, Oracle and/or its affiliates. All rights reserved.
* Copyright (c) 1997, 2022, Oracle and/or its affiliates. All rights reserved.
* DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
*
* This code is free software; you can redistribute it and/or modify it
Expand Down Expand Up @@ -147,12 +147,11 @@ class VM_Version : public Abstract_VM_Version {
uint32_t LahfSahf : 1,
CmpLegacy : 1,
: 3,
lzcnt_intel : 1,
lzcnt : 1,
sse4a : 1,
misalignsse : 1,
prefetchw : 1,
: 22;
: 23;
} bits;
};

Expand Down Expand Up @@ -588,21 +587,21 @@ class VM_Version : public Abstract_VM_Version {
result |= CPU_SSE4A;
}
// Intel features.
if(is_intel()) {
if(_cpuid_info.ext_cpuid1_ecx.bits.lzcnt_intel != 0)
if (is_intel()) {
if (_cpuid_info.ext_cpuid1_ecx.bits.lzcnt != 0) {
result |= CPU_LZCNT;
// for Intel, ecx.bits.misalignsse bit (bit 8) indicates support for prefetchw
if (_cpuid_info.ext_cpuid1_ecx.bits.misalignsse != 0) {
}
if (_cpuid_info.ext_cpuid1_ecx.bits.prefetchw != 0) {
result |= CPU_3DNOW_PREFETCH;
}
}

// ZX features.
if (is_zx()) {
if (_cpuid_info.ext_cpuid1_ecx.bits.lzcnt_intel != 0)
if (_cpuid_info.ext_cpuid1_ecx.bits.lzcnt != 0) {
result |= CPU_LZCNT;
// for ZX, ecx.bits.misalignsse bit (bit 8) indicates support for prefetchw
if (_cpuid_info.ext_cpuid1_ecx.bits.misalignsse != 0) {
}
if (_cpuid_info.ext_cpuid1_ecx.bits.prefetchw != 0) {
result |= CPU_3DNOW_PREFETCH;
}
}
Expand Down

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